WO1997022138A2 - Flip-chip process for producing a multi-chip module - Google Patents
Flip-chip process for producing a multi-chip module Download PDFInfo
- Publication number
- WO1997022138A2 WO1997022138A2 PCT/DE1996/002218 DE9602218W WO9722138A2 WO 1997022138 A2 WO1997022138 A2 WO 1997022138A2 DE 9602218 W DE9602218 W DE 9602218W WO 9722138 A2 WO9722138 A2 WO 9722138A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- heat sink
- component
- multilayer circuit
- substrate
- chip
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Definitions
- the invention relates to a flip-chip method for producing a multi-chip module according to the method steps of the main claim.
- Multi-chip modules are generally known. They are suitable as a particularly economical embodiment of a component module.
- the external contacts of the chips are connected to further chips and possibly additional electrical components to form an electrical circuit.
- the inventive method according to the main claim it is possible to produce the shortest chip to chip connections with a high packing density of the individual components.
- Small conductor capacitance and conductor inductance improve the high-frequency properties of the modules while at the same time having a very good thermal load capacity of the circuit parts of the module.
- the electromagnetic Compatibility and mechanical protection of the components are significantly improved.
- the costs are reduced if the substrate can be used as a housing part. It is also possible to automate individual, several or all process steps by a common process.
- the measures disclosed in the subclaims provide further improvements and advantages.
- To increase the thermal load capacity it is expedient to provide thermal plated-through holes from the substrate to the components.
- the thermal adhesive can function as the housing of one or more components after curing.
- the figure shows a section of a multichip module 10 which was produced with a component (chip) 15 using the method according to the invention.
- the module 10 can also have more than one chip IL.
- Conductor tracks 25 are applied to a substrate 20.
- the conductor track surfaces 30 are connected to the contact surfaces 40 of the plated-through holes 55, which are built into the base layer 50 of the multilayer circuit 50, 60, 70, by contacts 35 made of solder or conductive adhesive.
- Vias 75 are built into the top layer 70 of the multilayer circuit 50, 60, 70, and conductor tracks 65 are built into the middle layer 60.
- the plated-through holes 75 in the cover layer 70 are electrically conductively connected to the plated-through holes 55 in the base layer 50 by means of the conductor tracks 65 in the middle layer 60 of the multilayer circuit 50, 60, 70.
- the component 15 sits with the interposition of a thin solder or conductive adhesive layer 76 with foot contacts 80 on the surfaces of the plated-through holes 75 of the cover layer 70 of the multilayer circuit 50, 60, 70 and is installed in a recess 100 in the heat sink 85.
- the heat sink 85 is arranged on the cover layer 70 of the multi-layer circuit 50, 60, 70 with the insertion of the conductive adhesive layer 76 and is connected in a heat-conducting manner to the component 15 by a heat-conducting adhesive composition 90 in the free space 95 of the recess remaining between the component 15 and the heat sink 85 100 of the heat sink 85 is shed.
- the heat sink 85 is connected in a heat-conducting manner to a conductor track 25 on the substrate 20 via heat-conducting through-contacts 130, 125 and 120 and the heat-conducting contact 135.
- a housing 105 is arranged above the component 15 on the heat sink 85 and the heat-conducting adhesive composition 90.
- the exposed surface of the plated-through holes 55 and 120 is provided with the reference symbol 40.
- the base layer 50 and the cover layer 70 of the multilayer circuit are preferably made of polyimide.
- the parts of the middle layer 60 not occupied by conductor tracks 65 are filled with adhesive.
- Modules 10 with multilayer circuits with more than three layers 50, 60 and 70 can also be produced using the method according to the invention.
- the housing 105 can also serve to encapsulate more than one component 15.
- a multilayer circuit is produced from solid polyimide layers with plated-through holes according to the known method of vacuum-assisted thick-film technology, the base and top layers being connected to one another outside of the conductor track areas by adhesive.
- a recess (100) is punched out of an aluminum plate into which the component (15) fits.
- the heat sink (85) is glued to the multilayer circuit (50, 60, 70) by means of solder or conductive adhesive (76), which is preferably applied by screen printing.
- the multilayer circuit is fitted with the component by inserting solder or conductive adhesive (76).
- Steps 3 and 4 can also be interchanged. 5.
- the component (15) and the heat sink (85) are cast with a thermal adhesive (90).
- Copper conductor tracks (25) are produced on the substrate (20) using known etching technology.
- the substrate (20) consists of an FR4 circuit board made of epoxy resin reinforced with glass fiber fabric.
- the conductor tracks (25) of the substrate (20) are electrically connected by solder or conductive adhesive (35) to the plated-through holes (55) of the base layer (50) of the multilayer circuit.
- Example 2 The procedure is as in exemplary embodiment 1, but a thermal plated-through hole (VIAS) (120, 125, 130) is installed between the substrate (20) and the heat sink (85).
- VIAS thermal plated-through hole
- a multichip module is cast in epoxy resin after it has been produced in accordance with exemplary embodiment 1.
- the thermal adhesive is injection molded, creating a shape with cooling fins that form the housing of the module.
- Embodiment 6 Between steps 3 and 4 of embodiment 1, resistors or capacitors are or are printed on the underside of the base layer (50) of the multilayer circuit.
- Embodiment 7 The multilayer circuit is manufactured with more than three layers. It is possible to use layers of base material of different thicknesses. In rare cases, it may be necessary to use different base materials.
- Multi-chip modules were manufactured with the materials and properties listed in the table below.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP96945743A EP0865668A2 (en) | 1995-12-09 | 1996-11-21 | Flip-chip process for producing a multi-chip module |
JP09521598A JP2000501885A (en) | 1995-12-09 | 1996-11-21 | Flip chip method for manufacturing multi-chip module |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE1995146045 DE19546045C1 (en) | 1995-12-09 | 1995-12-09 | Flip-chip method for producing a multichip module |
DE19546045.6 | 1995-12-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1997022138A2 true WO1997022138A2 (en) | 1997-06-19 |
WO1997022138A3 WO1997022138A3 (en) | 1997-07-31 |
Family
ID=7779701
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1996/002218 WO1997022138A2 (en) | 1995-12-09 | 1996-11-21 | Flip-chip process for producing a multi-chip module |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0865668A2 (en) |
JP (1) | JP2000501885A (en) |
DE (1) | DE19546045C1 (en) |
WO (1) | WO1997022138A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19912441A1 (en) * | 1999-03-19 | 2000-09-21 | Elfo Ag Sachseln Sachseln | Multi-chip module |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1684341A3 (en) | 2005-01-21 | 2007-01-10 | Robert Bosch Gmbh | Electric circuit and method of manufacturing an electric circuit |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5090609A (en) * | 1989-04-28 | 1992-02-25 | Hitachi, Ltd. | Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals |
WO1994027318A1 (en) * | 1993-05-11 | 1994-11-24 | Micromodule Systems | Packaging and interconnect system for integrated circuits |
US5375042A (en) * | 1990-11-30 | 1994-12-20 | Hitachi, Ltd. | Semiconductor package employing substrate assembly having a pair of thin film circuits disposed one on each of oppositely facing surfaces of a thick film circuit |
US5397921A (en) * | 1993-09-03 | 1995-03-14 | Advanced Semiconductor Assembly Technology | Tab grid array |
EP0685878A2 (en) * | 1994-04-28 | 1995-12-06 | Fujitsu Limited | Semiconductor package and method of forming the same |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5155661A (en) * | 1991-05-15 | 1992-10-13 | Hewlett-Packard Company | Aluminum nitride multi-chip module |
JPH0758254A (en) * | 1993-08-19 | 1995-03-03 | Fujitsu Ltd | Multichip module and manufacture thereof |
-
1995
- 1995-12-09 DE DE1995146045 patent/DE19546045C1/en not_active Expired - Fee Related
-
1996
- 1996-11-21 WO PCT/DE1996/002218 patent/WO1997022138A2/en not_active Application Discontinuation
- 1996-11-21 EP EP96945743A patent/EP0865668A2/en not_active Ceased
- 1996-11-21 JP JP09521598A patent/JP2000501885A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5090609A (en) * | 1989-04-28 | 1992-02-25 | Hitachi, Ltd. | Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals |
US5375042A (en) * | 1990-11-30 | 1994-12-20 | Hitachi, Ltd. | Semiconductor package employing substrate assembly having a pair of thin film circuits disposed one on each of oppositely facing surfaces of a thick film circuit |
WO1994027318A1 (en) * | 1993-05-11 | 1994-11-24 | Micromodule Systems | Packaging and interconnect system for integrated circuits |
US5397921A (en) * | 1993-09-03 | 1995-03-14 | Advanced Semiconductor Assembly Technology | Tab grid array |
EP0685878A2 (en) * | 1994-04-28 | 1995-12-06 | Fujitsu Limited | Semiconductor package and method of forming the same |
Non-Patent Citations (1)
Title |
---|
L'ONDE ELECTRIQUE, Bd. 73, Nr. 6, 1.November 1993, Seiten 48-54, XP000412768 NICOLAS G ET AL: "EVOLUTION DES TECHNOLOGIES D'ONTERCONNEXION ET D'ENCAPSULATION DES COMPOSANTS ELECTRONIQUES EVOLUTION OF INTERCONNECT AND PACKAGING TECHNOLOGIES IN ELECTRONIC COMPONENTS" * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19912441A1 (en) * | 1999-03-19 | 2000-09-21 | Elfo Ag Sachseln Sachseln | Multi-chip module |
Also Published As
Publication number | Publication date |
---|---|
EP0865668A2 (en) | 1998-09-23 |
JP2000501885A (en) | 2000-02-15 |
WO1997022138A3 (en) | 1997-07-31 |
DE19546045C1 (en) | 1997-05-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0642166B1 (en) | On circuit board mounted multichip module | |
US5319159A (en) | Double-sided printed wiring board and method of manufacture thereof | |
DE112004001727B4 (en) | Method of manufacturing an electronic module | |
DE10138278C1 (en) | Electronic component with electronic components stacked on top of one another and method for producing the same | |
DE60032067T2 (en) | Multilayer printed circuit board and method for its production | |
EP2524394A2 (en) | Electronic device, method for producing the latter, and printed circuit board comprising electronic device | |
DE2536316C2 (en) | Circuit card for integrated semiconductor circuits | |
EP3231262B1 (en) | Semi-flexible printed circuit board with embedded component | |
DE2330732A1 (en) | CIRCUIT CARD FOR INTEGRATED CIRCUITS | |
WO2003075347A2 (en) | Electronic module, panel with individual electronic modules and method for the production thereof | |
WO2016091992A1 (en) | Circuit board having an asymmetric layer structure | |
DE3837975A1 (en) | ELECTRONIC CONTROL UNIT | |
DE102006044369B4 (en) | Method for producing a substrate with a cavity | |
EP1192841B1 (en) | Intelligent power module | |
US6316291B1 (en) | Method of fabricating a non-laminate carrier substrate utilizing a mold | |
DE19642488A1 (en) | Thin-layer circuit board for e.g. chip card | |
US20040168314A1 (en) | Process for manufacture of printed circuit boards with thick copper power circuitry and thin copper signal circuitry on the same layer | |
DE19546045C1 (en) | Flip-chip method for producing a multichip module | |
DE4223371A1 (en) | Electronic component mounting method for circuit board assembly - with openings in cover layer overlapping each component receiving conductive paste providing required electrical connections | |
DE102015112451B4 (en) | Power semiconductor module | |
DE102008009220A1 (en) | Method for producing a printed circuit board | |
WO2017089213A1 (en) | Circuit carrier for an electrical circuit and associated production method | |
DE202009009950U1 (en) | Electronic module | |
WO2007080027A1 (en) | Arrangement for cooling power components on printed circuit boards and method for producing the same | |
DE19841996B4 (en) | Semiconductor component in chip format and method for its production |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
AK | Designated states |
Kind code of ref document: A3 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1996945743 Country of ref document: EP |
|
ENP | Entry into the national phase in: |
Ref country code: JP Ref document number: 1997 521598 Kind code of ref document: A Format of ref document f/p: F |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWP | Wipo information: published in national office |
Ref document number: 1996945743 Country of ref document: EP |
|
WWR | Wipo information: refused in national office |
Ref document number: 1996945743 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1996945743 Country of ref document: EP |