WO1997021272A1 - Circuit comprising a bus conductor and a bus interface circuit - Google Patents
Circuit comprising a bus conductor and a bus interface circuit Download PDFInfo
- Publication number
- WO1997021272A1 WO1997021272A1 PCT/IB1996/001269 IB9601269W WO9721272A1 WO 1997021272 A1 WO1997021272 A1 WO 1997021272A1 IB 9601269 W IB9601269 W IB 9601269W WO 9721272 A1 WO9721272 A1 WO 9721272A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- transistor
- coupled
- ouφut
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
Definitions
- an object of the invention to provide a circuit which comprises an interface stage coupled to a bus conductor and in which the interface stage can be actively driven without adverse effects when the overvoltage state occurs. It is a further object of the invention to provide a bus-hold circuit coupled to a bus conductor on which the overvoltage state can occur.
- control circuit is coupled, by way of an input, to the bus conductor and has a logic inverting transfer function between its input and output.
- control circuit thus constitutes a latch which serves as a bus-hold circuit and which can remain active while other circuit components control the bus potential.
- the overvoltage detection circuit 21 which detects the overvoltage state.
- the PMOS transistor 34 whose channel is situated between the bus conductor 1 and the backbias ou ⁇ ut BG is turned on when the bus potential exceeds the potential of the power supply terminal Vdd by more than a threshold voltage; this channel is turned off in the normal state.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP96935297A EP0807334A1 (en) | 1995-12-01 | 1996-11-21 | Circuit comprising a bus conductor and a bus interface circuit |
| JP52110697A JP3865408B2 (ja) | 1995-12-01 | 1996-11-21 | バス導線及びバスインタフェース回路を具えている回路 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP95203314 | 1995-12-01 | ||
| EP95203314.0 | 1995-12-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1997021272A1 true WO1997021272A1 (en) | 1997-06-12 |
Family
ID=8220899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB1996/001269 Ceased WO1997021272A1 (en) | 1995-12-01 | 1996-11-21 | Circuit comprising a bus conductor and a bus interface circuit |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5764468A (enExample) |
| EP (1) | EP0807334A1 (enExample) |
| JP (1) | JP3865408B2 (enExample) |
| KR (1) | KR19980701948A (enExample) |
| TW (1) | TW318913B (enExample) |
| WO (1) | WO1997021272A1 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6150845A (en) * | 1999-06-01 | 2000-11-21 | Fairchild Semiconductor Corp. | Bus hold circuit with overvoltage tolerance |
| US7064593B2 (en) * | 2004-09-20 | 2006-06-20 | Texas Instruments Incorporated | Bus-hold circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3916262A (en) * | 1974-07-23 | 1975-10-28 | Us Navy | Low voltage bus-operated overvoltage protection system |
| US5019720A (en) * | 1990-03-12 | 1991-05-28 | Ncr Corporation | Integrated circuit driver for serial bus having output overvoltage protection |
| EP0614279A2 (en) * | 1993-03-02 | 1994-09-07 | National Semiconductor Corporation | Overvoltage tolerant output buffer circuit |
| EP0621692A2 (en) * | 1993-04-19 | 1994-10-26 | Koninklijke Philips Electronics N.V. | Overvoltage protection circuitry |
| WO1994029963A1 (en) * | 1993-06-07 | 1994-12-22 | National Semiconductor Corporation | Voltage translation and overvoltage protection |
| US5387826A (en) * | 1993-02-10 | 1995-02-07 | National Semiconductor Corporation | Overvoltage protection against charge leakage in an output driver |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100282287B1 (ko) * | 1993-06-07 | 2001-02-15 | 클라크 3세 존 엠. | 과전압에 대한 보호 |
| US5444397A (en) * | 1994-10-05 | 1995-08-22 | Pericom Semiconductor Corp. | All-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages |
| JP2959449B2 (ja) * | 1995-10-16 | 1999-10-06 | 日本電気株式会社 | 出力回路 |
-
1996
- 1996-11-21 JP JP52110697A patent/JP3865408B2/ja not_active Expired - Fee Related
- 1996-11-21 WO PCT/IB1996/001269 patent/WO1997021272A1/en not_active Ceased
- 1996-11-21 EP EP96935297A patent/EP0807334A1/en not_active Ceased
- 1996-11-21 KR KR1019970705345A patent/KR19980701948A/ko not_active Abandoned
- 1996-12-02 US US08/758,654 patent/US5764468A/en not_active Expired - Lifetime
- 1996-12-05 TW TW085115039A patent/TW318913B/zh active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3916262A (en) * | 1974-07-23 | 1975-10-28 | Us Navy | Low voltage bus-operated overvoltage protection system |
| US5019720A (en) * | 1990-03-12 | 1991-05-28 | Ncr Corporation | Integrated circuit driver for serial bus having output overvoltage protection |
| US5387826A (en) * | 1993-02-10 | 1995-02-07 | National Semiconductor Corporation | Overvoltage protection against charge leakage in an output driver |
| US5450025A (en) * | 1993-02-10 | 1995-09-12 | National Semiconductor Corporation | Tristate driver for interfacing to a bus subject to overvoltage conditions |
| EP0614279A2 (en) * | 1993-03-02 | 1994-09-07 | National Semiconductor Corporation | Overvoltage tolerant output buffer circuit |
| EP0621692A2 (en) * | 1993-04-19 | 1994-10-26 | Koninklijke Philips Electronics N.V. | Overvoltage protection circuitry |
| WO1994029963A1 (en) * | 1993-06-07 | 1994-12-22 | National Semiconductor Corporation | Voltage translation and overvoltage protection |
Also Published As
| Publication number | Publication date |
|---|---|
| US5764468A (en) | 1998-06-09 |
| JPH11502046A (ja) | 1999-02-16 |
| KR19980701948A (ko) | 1998-06-25 |
| TW318913B (enExample) | 1997-11-01 |
| JP3865408B2 (ja) | 2007-01-10 |
| EP0807334A1 (en) | 1997-11-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5381061A (en) | Overvoltage tolerant output buffer circuit | |
| US5406140A (en) | Voltage translation and overvoltage protection | |
| EP1024597B1 (en) | Output circuit for use in a semiconductor integrated circuit | |
| US5128560A (en) | Boosted supply output driver circuit for driving an all N-channel output stage | |
| KR100269643B1 (ko) | 전력소비 억제회로 | |
| US5555149A (en) | Overvoltage protection | |
| US6040729A (en) | Digital output buffer for multiple voltage system | |
| US6351158B1 (en) | Floating gate circuit for backwards driven MOS output driver | |
| US6781413B2 (en) | Level conversion circuit for which an operation at power voltage rise time is stabilized | |
| US5598107A (en) | Current switching circuit having reduced current noise operation | |
| US5796281A (en) | Input buffer circuit with hysteresis for noise control | |
| US6859089B2 (en) | Power switching circuit with controlled reverse leakage | |
| JP3566773B2 (ja) | パワーダウン機能を有する出力バッファ回路 | |
| US6046617A (en) | CMOS level detection circuit with hysteresis having disable/enable function and method | |
| US6265896B1 (en) | Level transfer circuit for LVCMOS applications | |
| US6236195B1 (en) | Voltage variation correction circuit | |
| US5966044A (en) | Pull-up circuit and semiconductor device using the same | |
| KR20010050477A (ko) | 집적 반도체 회로의 인풋-버퍼 | |
| US6414521B1 (en) | Sense amplifier systems and methods | |
| US6636089B2 (en) | Power supply detection device | |
| US5764468A (en) | Circuit comprising a bus conductor and a bus interface circuit | |
| US6268759B1 (en) | Low-power 5-volt input/output tolerant circuit with power-down control for a low voltage CMOS crossbar switch | |
| US5767696A (en) | Tri-state devices having exclusive gate output control | |
| US6154058A (en) | Output buffer | |
| US6150844A (en) | High voltage tolerance output stage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP KR |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 1996935297 Country of ref document: EP |
|
| ENP | Entry into the national phase |
Ref country code: JP Ref document number: 1997 521106 Kind code of ref document: A Format of ref document f/p: F |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 1019970705345 Country of ref document: KR |
|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
| WWP | Wipo information: published in national office |
Ref document number: 1996935297 Country of ref document: EP |
|
| WWP | Wipo information: published in national office |
Ref document number: 1019970705345 Country of ref document: KR |
|
| WWR | Wipo information: refused in national office |
Ref document number: 1996935297 Country of ref document: EP |
|
| WWW | Wipo information: withdrawn in national office |
Ref document number: 1996935297 Country of ref document: EP |
|
| WWG | Wipo information: grant in national office |
Ref document number: 1019970705345 Country of ref document: KR |