WO1997012402A1 - Semiconductor charge potential wells with integrated diffusions - Google Patents

Semiconductor charge potential wells with integrated diffusions Download PDF

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Publication number
WO1997012402A1
WO1997012402A1 PCT/US1996/015285 US9615285W WO9712402A1 WO 1997012402 A1 WO1997012402 A1 WO 1997012402A1 US 9615285 W US9615285 W US 9615285W WO 9712402 A1 WO9712402 A1 WO 9712402A1
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Prior art keywords
charge
diffusion
conductivity type
well
potential
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PCT/US1996/015285
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French (fr)
Inventor
Scott C. Munroe
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Analog Devices, Inc.
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Publication date
Application filed by Analog Devices, Inc. filed Critical Analog Devices, Inc.
Priority to AU73704/96A priority Critical patent/AU7370496A/en
Publication of WO1997012402A1 publication Critical patent/WO1997012402A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76816—Output structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42396—Gate electrodes for field effect devices for charge coupled devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS

Definitions

  • the present invention relates to the use of integrated diffusions within the potential wells of semiconductor devices, such as charge-coupled devices (CCDs), bucket brigade devices, or any MOS-type device.
  • CCDs charge-coupled devices
  • bucket brigade devices or any MOS-type device.
  • FIG. 1 shows an exemplary conventional two-phase buried n-channel CCD 100.
  • the exemplary CCD includes a lightly doped p-type substrate 102, a lightly doped n-type layer 104, and an insulating layer 106 of oxide.
  • On the surface of the insulating layer there is provided a series of electrode gates including an input gate 108, a barrier phase gate 110, a storage phase gate 112, an output gate 114, and a reset gate 116.
  • a highly doped input diffusion n + 118 provides charge to the potential well associated with the input gate, which is subsequently passed to the storage wells, in accordance with a predetermined clocking scheme.
  • a highly doped output sense diffusion n + 120 serves to detect the charge packets. By strongly reverse biasing the sense diffusion, it acts as a sink for any charge arriving from the potential well associated with the last electrode in the structure.
  • the output gate is held at a fixed bias and serves to minimize the electrostatic noise created by clock pulses on the electrode previous to the output gate.
  • the simplest way to detect the arrival of charge at the sense diffusion is to measure the current through, or the voltage across, a series resistor connecting the diffusion to the bias supply.
  • the forward time constants are proportional to L/W, or ⁇ F KL/W.
  • the lateral time constants are proportional to W/L, or r L «W/L. Accordingly, the first reaction is to help the forward time constant by making the lateral width W and length L of each gate short. However, this is exactly the wrong thing to do in terms of the lateral time constants.
  • FIG. 2 shows a portion 20 of a CCD structure which includes a first barrier phase gate 22 and its associated storage phase gate 23 which are biased at 4> deposit-. Adjacent thereto is a transfer barrier phase gate 24 and the associated storage phase gate 25.
  • a charge splitter 26 is implemented with the transfer barrier and storage phases and an isolation region in the CCD channel. Charge splitters are used, for example, in A/D converters. The splitters operate to split a charge packet into Q/2 halves, one of which is passed on for further processing. In the binary domain, one Q/2 charge is going to move forward, while the other needs to transfer laterally. However, this lateral transfer is very slow due to the large lateral time constants.
  • a further set of problems that needs to be addressed relates to the actual sensing of the charge that is present in the storage wells. This is probably the most difficult task faced in CCD design at the present time. Most problems with CCD structures have been dealt with effectively, but sensing the charge non-destructively in a well is still a serious problem.
  • the conventional sensing method in devices using relatively high voltages and deep wells, was to basically utilize a floating gate which operates as follows. During an empty well condition, the floating polysilicon gate is set to a known potential through a reset switch. Once the switch is opened, the charge in the CCD channel moves forward into the well beneath the floating gate. If one then measured the voltage change ( ⁇ V) on this floating gate, it would then be proportional to the amount of charge in the storage well underneath.
  • the floating gate cannot be operated to sense the charge as previously described because it tends to collapse the storage well. Once charge is dumped into the floating gate well, the potential of the gate drops. This drop in gate potential leads to a raising of the bottom of the storage well, thereby decreasing its capacity. Therefore, it is possible to create a situation where the charge transferring into the well collapses the very well that is supposed to contain it. The result is that part of the charge packet actually spills beyond the storage well. Accordingly, it is desirable to develop a charge sensing technique that does not use a floating gate.
  • a semiconductor device having a semiconductor region including a material of a first predetermined conductivity type; an insulating layer provided on the semiconductor region; a gate electrode provided on the insulating layer, the gate electrode forming a potential well within the semiconductor region in response to a potential being applied thereto; and a diffusion of highly doped material of a second predetermined conductivity type being positioned within the semiconductor region, and which is applied through an opening in the gate electrode and the insulating layer, the diffusion being in direct ohmic contact with the potential well.
  • the diffusion can be either a n + or p + diffusion. The diffusion accommodates a reduction in lateral time constants of charge redistribution within the potential well, direct sensing of the charge in the well, and injection and extraction of charge to and from the well.
  • Fig. 1 illustrates a cross-sectional view of a diagrammatic representation of a conventional buried channel CCD structure
  • Fig. 2 illustrates a top diagrammatic view of CCD structure including a set of barrier and storage phase gates including a charge splitter;
  • Fig. 3 illustrates a top diagrammatic view of a CCD structure including a storage phase gate with a slot and n + diffusion in accordance with an exemplary embodiment of the present invention
  • Fig. 4 illustrates a cross-sectional view of a diagrammatic representation of a buried channel CCD structure including a storage phase gate with a slot and n * diffusion in accordance with an exemplary embodiment of the present invention
  • Fig. 5 illustrates a potential well diagram of the CCD structure of Fig. 4 including an extended potential well associated with the n + diffusion in accordance with the present invention
  • Fig. 6 shows a plan view of a block diagram of an MOS capacitor
  • Fig. 7 shows a cross-sectional view of the block diagram of the MOS capacitor shown in Fig. 6;
  • Fig. 8 shows a cross-sectional view of a block diagram of a quantum well device constructed from an insulated-gate FET.
  • a CCD structure 30 is shown as an exemplary embodiment of the present invention, which includes a storage phase gate 32 and a barrier phase gate 38.
  • the barrier and storage phase gates are provided on an insulating layer 40, which in turn lies atop a semiconductor region including lightly doped n " layer 42 and a lightly doped p" substrate 44.
  • an opening or slot 34 is positioned in the storage phase gate 32 and the underlying insulating layer 40, thus exposing the semiconductor region.
  • a highly doped n + diffusion 36 is disposed proximate to the slot 34 within the semiconductor region, in the illustrated example the layer 42.
  • CCDs are a configuration of MOS capacitors that are placed closely enough together to allow charge underneath one plate to transfer to the other plate, thus the charge coupling effect. Normally it is desirable to be able to fully deplete the potential wells beneath the capacitor plates. However, in certain instances it is advantageous to have regions of highly-doped silicon, even though these regions can never be depleted of mobile charge .
  • the technique of the present invention is implemented by cutting the slot or hole in the gate, for example polysilicon, and through the dielectric or insulating layer underneath. A diffusion of n + -type material is then made at the same time as the standard drain/source diffusion. Providing contacts to the diffusion is done by conventional methods well known in the art.
  • a storage or potential well 50 which corresponds to the channel potential under gate 32 is shown.
  • the n + diffusion 36 creates an extended well 52 of great depth which cannot be fully depleted with the range of voltages typically used in IC operations.
  • the sea of mobile charge present in the extended well creates a region of high conductivity which is in direct ohmic contact with the storage well. Such a region is utilized to reduce lateral time constants to orders of magnitude shorter than gates not having the n + diffusion.
  • charge is transferred into and out of the storage well having the n * diffusion 36.
  • the potential of the charge in the diffusion equilibrates to that of the empty well. Since the carriers in the diffusion have associated thermal energy, the diffusion can be a source of thermal noise. Hence, the area and perimeter of the diffusion is minimized.
  • n + diffusion 36 within the gate is the dramatic reduction in the lateral charge redistribution time constants across the width of the storage well.
  • the n + diffusion effectively operates as an electrical shorting bar within the well.
  • the resultant short time constants are critical in applications such as 2- D CCDs, where lateral charge transfer is required, and for CCD devices where it is desirable to split a charge packet, and in which the potential of the charge packets in the two receiving wells must be maintained equal despite their being transferred at unequal rates.
  • n + diffusion 36 Another advantage of the n + diffusion 36 is the resultant ability to directly sense the potential of the charge within the storage well, or extract or inject charge into the well.
  • the use of the n + diffusion does not suffer from the drawbacks of the presently used floating gate method, including non-linearities, reset noise, and signal attenuation.
  • source or drain diffusions are conventionally implemented at the extremes of the CCD. These types of diffusions have far more capacitance associated with them, and are less linear in capacitance than a diffusion placed directly in the storage well itself.
  • n + diffusion 36 in accordance with the present invention accommodates direct access to the charge within the storage well, thus allowing for the associated use of a conventional contact for external signal processing.
  • the gate associated with the storage well does not change potential, and in fact it serves to shield the well from the charge dump that occurs because of the capacitive coupling between the transfer phase and the DC storage phase. Accordingly, pinning the gate to a DC level shields the charge in the well and prevents capacitive coupling from the adjacent transfer clock phase.
  • n + diffusion 36 is in perfect ohmic contact with any charge that is in the underlying channel.
  • the n + diffusion takes on the potential of the signal charge present in the channel as shown in Fig. 5. Thus, there is no need for reset, and no charge dump from the reset switch.
  • the n + diffusion provides the sea of mobile electrons in the extended well 52 which in effect creates an internal conductor.
  • the extended well of mobile charge associated with the n + diffusion cannot be depleted under normal operating conditions. In order to deplete the extended well of the n" diffusion, it would require putting tens of volts across the gate, thus pulling the charge level so far down into the well as to fully deplete the mobile charge.
  • the electrons at the top of the extended well actually have thermal energy, and therefore the charge transfer efficiency of the device is effected.
  • Thermal energy can occasionally drive an electron out of the extended well and into the empty well.
  • the electron can migrate back to the extended well, but if the device is operating to transfer charge to a subsequent phase, the migrating electron that is driven from the extended well can actually migrate into the next storage well. This is an effect that is not present in wells not having the n + diffusion. Hence, care must be exercised in the design and operation of the structure so as to minimize the degradation of the charge transfer efficiency.
  • the storage well 50 is emptied by transferring out all of the charge present in the well, thus charging the n + extended well 52, to a potential corresponding to that present at the bottom of the empty well 50. Thereafter, a subsequent charge packet is injected into the storage well.
  • the charge in the extended well of the n + diffusion is now in intimate contact with all of the charge present in the storage well, and hence the potential of the extended well becomes equivalent to the potential in the storage well. This potential change accommodates the sensing of the amount of charge present in the channel.
  • Sensing the charge potential using the n + diffusion 36 is more accurate than the method utilizing a floating gate in that there is noise associated with both the switch that resets the floating gate and with the coupling of the transfer clock from the next gate onto the floating gate. In other words, there is only an indirect sensing of the charge in a floating gate structure. With the n + diffusion, there is a direct relationship between the potential of the charge in the storage well and the potential of the electrode plate above the charge. The poly gate, which will now be pinned to a predetermined DC reference, effects shielding of the charge packet from the coupling associated with the adjacent transfer clock. In addition, there is no reset noise, and there is no concern regarding linearity being degraded by the floating gate changing potential as charge is transferred to the storage well.
  • n * diffusion is that of water in a hose.
  • an exemplary serial to parallel type charge transfer where the charge is drained laterally from a particular storage well. Following the lateral drainage of the charge from the well, there may be mobile electrons left behind as a result of a weak electric field. If a n + diffusion is present in the gate, the mobile electrons will be attracted to the diffusion. Accordingly, rather than requiring the electrons to traverse the entire well, the entrance of the electrons into one end of the extended well effects a nearly instantaneous equal discharge of electrons from the opposite end of the extended well for transfer out of the gate, thus reducing lateral time constants.
  • the n + diffusion can also be used in a gate having a split in the channel to maintain the split portions of a charge packet at the same potential. Due to the presence of a diffusion in each of the two channels, the two resultant potential wells can be tied together to maintain their charge packets at identical potentials.
  • the n + diffusion has many other possible applications in CCDs.
  • conventional CCDs typically include discrete input and output diffusions.
  • the n + diffusions in accordance with the present invention can be utilized as the input and output regions. In the conventional devices using separate diffusion regions, problems arise if those diffusions are not connected to voltage sources.
  • n + diffusion input region there is a limit as to how small the n + diffusion input region can be made, and there are capacitances and non-linearities associated with the diffusion. Most p-n junctions are quite non-linear with respect to their voltage to charge relationships. These problems are avoided by gaining direct access to the first storage well and the final storage well with the use of the n + diffusions of the present invention. In other words, the n + diffusions in the gates accommodate direct charge injection and extraction.
  • n + diffusion can be provided in a p-type substrate to form a surface n- channel device.
  • a p + diffusion can be provided in a n-type substrate as part of a surface p- channel device, or the p + diffusion can be provided in a p- type layer of a buried p-channel device. Accordingly, the p + diffusion provides the same functions and advantages as described for the n + diffusion.
  • n + or p + diffusion in accordance with the present invention can be utilized in a quantum well structure. In such a structure, the diffusion would serve to modulate the current through the established potential well.
  • the use of diffusions through openings or slots in gate material can also be carried out in MOS capacitor devices, but for different functional reasons than specified heretofore.
  • the purpose of an MOS capacitor is to store a voltage, not a charge packet.
  • An MOS capacitor does not include potential barriers and wells to allow containment of signal-dependent charge packets. The two terminals of such a capacitor are typically connected to voltage sources (sometimes switched), which cause the charge on the capacitor plates to adjust to the potential applied.
  • Figs. 6 and 7 respectively show a plan view and a cross-sectional view of a block diagram of an MOS capacitor 60.
  • the MOS capacitor includes a continuous gate (top plate) 62 and underlying dielectric layer 63 with openings 64 to accommodate internal diffusions 66.
  • FIG. 8 shows a cross section of a block diagram of a quantum well device 80 constructed from an insulated-gate FET.
  • the FET includes, as is well known in the art, a gate 82, a source diffusion 84, and a drain diffusion 86.
  • a very narrow slot 88 is cut into the gate 82, and thereafter a diffusion 89 is then provided through the slot into the underlying channel.
  • the slot cross section must be very narrow, for example, less than approximately 0.1 ⁇ m for silicon. Once such dimensions are achieved, the charge flowing from the source can pass through the potential well (and on to the drain) only if the charge has distinct, discrete energy levels. These energy levels are determined by the depth and dimensions of the diffusion in the slot. Multiple slots, appropriately spaced, can be used to create more complex quantum-well devices with a variety of transfer functions.

Abstract

A semiconductor device having a semiconductor region including a material of a first predetermined conductivity type; an insulating layer (40) provided on the semiconductor region; a gate electrode (32, 34, 38) provided on the insulating layer, the gate electrode forming a potential well within the semiconductor region in response to a potential being applied thereto; and a diffusion (36) of highly doped material of a second predetermined conductivity type being positioned within the semiconductor region, and which is applied through an opening in the gate electrode and the insulating layer (40), the diffusion (36) being in direct ohmic contact with the potential well. The diffusion (36) can be either a n+ or p+ diffusion. The diffusion (36) accommodates a reduction in lateral time constants of charge redistribution within the potential well, direct sensing of the charge in the well, and injection and extraction of charge to and from the well.

Description

SEMICONDUCTOR CHARGE POTENTIAL HELLS WITH INTEGRATED DIFFUSIONS
BACKGROUND OF THE INVENTION The present invention relates to the use of integrated diffusions within the potential wells of semiconductor devices, such as charge-coupled devices (CCDs), bucket brigade devices, or any MOS-type device.
In conventional multi-phase CCD structures, there is usually a barrier phase with an accompanying storage phase. Typically, the storage phase includes a longer gate electrode than the barrier phase, however, this is not true in all instances. Fig. 1 shows an exemplary conventional two-phase buried n-channel CCD 100. The exemplary CCD includes a lightly doped p-type substrate 102, a lightly doped n-type layer 104, and an insulating layer 106 of oxide. On the surface of the insulating layer there is provided a series of electrode gates including an input gate 108, a barrier phase gate 110, a storage phase gate 112, an output gate 114, and a reset gate 116.
A highly doped input diffusion n+ 118 provides charge to the potential well associated with the input gate, which is subsequently passed to the storage wells, in accordance with a predetermined clocking scheme. A highly doped output sense diffusion n+ 120 serves to detect the charge packets. By strongly reverse biasing the sense diffusion, it acts as a sink for any charge arriving from the potential well associated with the last electrode in the structure. Typically, the output gate is held at a fixed bias and serves to minimize the electrostatic noise created by clock pulses on the electrode previous to the output gate. The simplest way to detect the arrival of charge at the sense diffusion is to measure the current through, or the voltage across, a series resistor connecting the diffusion to the bias supply. Resetting the potential of the sense diffusion after the arrival of each charge packet is achieved by pulsing the reset gate 116 and positively biasing a highly doped reset diffusion n+ 122. A large amount of time and design efforts have been spent in conventional CCD technology in arranging for all of the charge in a given storage well to be able to transfer very fast and very efficiently to a subsequent or next storage well. Unfortunately, problems arise for several situations involving conventional CCDs.
One problem occurs when it is desirable to move the charge laterally across the gate rather than in a forward direction. The difficulty lies in the inherently large lateral time constants. It will be appreciated that the forward time constants are proportional to L/W, or ΓFKL/W. In turn, the lateral time constants are proportional to W/L, or rL«W/L. Accordingly, the first reaction is to help the forward time constant by making the lateral width W and length L of each gate short. However, this is exactly the wrong thing to do in terms of the lateral time constants.
Additional problems occur when it desirable to move the charge from a given storage well forward into an adjacent CCD stage. The problem is amplified when charge splitters are utilized. Fig. 2 shows a portion 20 of a CCD structure which includes a first barrier phase gate 22 and its associated storage phase gate 23 which are biased at 4>„-. Adjacent thereto is a transfer barrier phase gate 24 and the associated storage phase gate 25. A charge splitter 26 is implemented with the transfer barrier and storage phases and an isolation region in the CCD channel. Charge splitters are used, for example, in A/D converters. The splitters operate to split a charge packet into Q/2 halves, one of which is passed on for further processing. In the binary domain, one Q/2 charge is going to move forward, while the other needs to transfer laterally. However, this lateral transfer is very slow due to the large lateral time constants.
A further set of problems that needs to be addressed relates to the actual sensing of the charge that is present in the storage wells. This is probably the most difficult task faced in CCD design at the present time. Most problems with CCD structures have been dealt with effectively, but sensing the charge non-destructively in a well is still a serious problem. The conventional sensing method, in devices using relatively high voltages and deep wells, was to basically utilize a floating gate which operates as follows. During an empty well condition, the floating polysilicon gate is set to a known potential through a reset switch. Once the switch is opened, the charge in the CCD channel moves forward into the well beneath the floating gate. If one then measured the voltage change (ΔV) on this floating gate, it would then be proportional to the amount of charge in the storage well underneath.
Unfortunately, with more modern technologies in which the supply voltages and the well depths are being reduced, the floating gate cannot be operated to sense the charge as previously described because it tends to collapse the storage well. Once charge is dumped into the floating gate well, the potential of the gate drops. This drop in gate potential leads to a raising of the bottom of the storage well, thereby decreasing its capacity. Therefore, it is possible to create a situation where the charge transferring into the well collapses the very well that is supposed to contain it. The result is that part of the charge packet actually spills beyond the storage well. Accordingly, it is desirable to develop a charge sensing technique that does not use a floating gate.
An additional disadvantage of this floating gate methodology is that the reset switch inherently has some capacitance associated with it. As the reset switch is turned off, a charge is dumped onto the floating gate which causes its potential to decrease. Hence, this effect also tends to collapse the storage well even before the signal charge arrives.
It is therefore an object of the present invention to provide a diffusion which is in direct ohmic contact with the potential or storage well which accommodates a reduction in lateral time constants of charge redistribution within the well, direct sensing of the charge in the well, and injection and extraction of charge to and from the well. It is another object of the present invention to provide a modification to the storage phase of a CCD structure to overcome the aforementioned drawbacks.
SUMMARY OF THE INVENTION
In accordance with an exemplary embodiment of the present invention, there is provided a semiconductor device having a semiconductor region including a material of a first predetermined conductivity type; an insulating layer provided on the semiconductor region; a gate electrode provided on the insulating layer, the gate electrode forming a potential well within the semiconductor region in response to a potential being applied thereto; and a diffusion of highly doped material of a second predetermined conductivity type being positioned within the semiconductor region, and which is applied through an opening in the gate electrode and the insulating layer, the diffusion being in direct ohmic contact with the potential well. The diffusion can be either a n+ or p+ diffusion. The diffusion accommodates a reduction in lateral time constants of charge redistribution within the potential well, direct sensing of the charge in the well, and injection and extraction of charge to and from the well.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 illustrates a cross-sectional view of a diagrammatic representation of a conventional buried channel CCD structure;
Fig. 2 illustrates a top diagrammatic view of CCD structure including a set of barrier and storage phase gates including a charge splitter;
Fig. 3 illustrates a top diagrammatic view of a CCD structure including a storage phase gate with a slot and n+ diffusion in accordance with an exemplary embodiment of the present invention;
Fig. 4 illustrates a cross-sectional view of a diagrammatic representation of a buried channel CCD structure including a storage phase gate with a slot and n* diffusion in accordance with an exemplary embodiment of the present invention; Fig. 5 illustrates a potential well diagram of the CCD structure of Fig. 4 including an extended potential well associated with the n+ diffusion in accordance with the present invention;
Fig. 6 shows a plan view of a block diagram of an MOS capacitor; and
Fig. 7 shows a cross-sectional view of the block diagram of the MOS capacitor shown in Fig. 6; and
Fig. 8 shows a cross-sectional view of a block diagram of a quantum well device constructed from an insulated-gate FET.
DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
With reference to Figs. 3 and 4, a CCD structure 30 is shown as an exemplary embodiment of the present invention, which includes a storage phase gate 32 and a barrier phase gate 38. The barrier and storage phase gates are provided on an insulating layer 40, which in turn lies atop a semiconductor region including lightly doped n" layer 42 and a lightly doped p" substrate 44. In accordance with the present invention, an opening or slot 34 is positioned in the storage phase gate 32 and the underlying insulating layer 40, thus exposing the semiconductor region. A highly doped n+ diffusion 36 is disposed proximate to the slot 34 within the semiconductor region, in the illustrated example the layer 42.
It is well understood that CCDs are a configuration of MOS capacitors that are placed closely enough together to allow charge underneath one plate to transfer to the other plate, thus the charge coupling effect. Normally it is desirable to be able to fully deplete the potential wells beneath the capacitor plates. However, in certain instances it is advantageous to have regions of highly-doped silicon, even though these regions can never be depleted of mobile charge .
The technique of the present invention is implemented by cutting the slot or hole in the gate, for example polysilicon, and through the dielectric or insulating layer underneath. A diffusion of n+-type material is then made at the same time as the standard drain/source diffusion. Providing contacts to the diffusion is done by conventional methods well known in the art.
In the potential diagram illustrated in Fig. 5, a storage or potential well 50 which corresponds to the channel potential under gate 32 is shown. The n+ diffusion 36 creates an extended well 52 of great depth which cannot be fully depleted with the range of voltages typically used in IC operations. The sea of mobile charge present in the extended well creates a region of high conductivity which is in direct ohmic contact with the storage well. Such a region is utilized to reduce lateral time constants to orders of magnitude shorter than gates not having the n+ diffusion. During normal CCD operation, charge is transferred into and out of the storage well having the n* diffusion 36. When transferring out charge, the potential of the charge in the diffusion equilibrates to that of the empty well. Since the carriers in the diffusion have associated thermal energy, the diffusion can be a source of thermal noise. Hence, the area and perimeter of the diffusion is minimized.
One advantage of using the n+ diffusion 36 within the gate is the dramatic reduction in the lateral charge redistribution time constants across the width of the storage well. The n+ diffusion effectively operates as an electrical shorting bar within the well. The resultant short time constants are critical in applications such as 2- D CCDs, where lateral charge transfer is required, and for CCD devices where it is desirable to split a charge packet, and in which the potential of the charge packets in the two receiving wells must be maintained equal despite their being transferred at unequal rates.
Another advantage of the n+ diffusion 36 is the resultant ability to directly sense the potential of the charge within the storage well, or extract or inject charge into the well. The use of the n+ diffusion does not suffer from the drawbacks of the presently used floating gate method, including non-linearities, reset noise, and signal attenuation. With respect to extracting or injecting charge, source or drain diffusions are conventionally implemented at the extremes of the CCD. These types of diffusions have far more capacitance associated with them, and are less linear in capacitance than a diffusion placed directly in the storage well itself.
The n+ diffusion 36 in accordance with the present invention accommodates direct access to the charge within the storage well, thus allowing for the associated use of a conventional contact for external signal processing. The gate associated with the storage well does not change potential, and in fact it serves to shield the well from the charge dump that occurs because of the capacitive coupling between the transfer phase and the DC storage phase. Accordingly, pinning the gate to a DC level shields the charge in the well and prevents capacitive coupling from the adjacent transfer clock phase.
It will be appreciated by those skilled in the art that the n+ diffusion 36 is in perfect ohmic contact with any charge that is in the underlying channel. The n+ diffusion takes on the potential of the signal charge present in the channel as shown in Fig. 5. Thus, there is no need for reset, and no charge dump from the reset switch.
Any charge that is in the n-type well, the channel well, is in ohmic contact with the n+ diffusion 36. In the potential diagram, there is shown an empty, in other words no free charge under the gate. However, the n+ diffusion provides the sea of mobile electrons in the extended well 52 which in effect creates an internal conductor. The extended well of mobile charge associated with the n+ diffusion cannot be depleted under normal operating conditions. In order to deplete the extended well of the n" diffusion, it would require putting tens of volts across the gate, thus pulling the charge level so far down into the well as to fully deplete the mobile charge.
The electrons at the top of the extended well actually have thermal energy, and therefore the charge transfer efficiency of the device is effected. Thermal energy can occasionally drive an electron out of the extended well and into the empty well. The electron can migrate back to the extended well, but if the device is operating to transfer charge to a subsequent phase, the migrating electron that is driven from the extended well can actually migrate into the next storage well. This is an effect that is not present in wells not having the n+ diffusion. Hence, care must be exercised in the design and operation of the structure so as to minimize the degradation of the charge transfer efficiency.
In operation, initially the storage well 50 is emptied by transferring out all of the charge present in the well, thus charging the n+ extended well 52, to a potential corresponding to that present at the bottom of the empty well 50. Thereafter, a subsequent charge packet is injected into the storage well. The charge in the extended well of the n+ diffusion is now in intimate contact with all of the charge present in the storage well, and hence the potential of the extended well becomes equivalent to the potential in the storage well. This potential change accommodates the sensing of the amount of charge present in the channel.
Sensing the charge potential using the n+ diffusion 36 is more accurate than the method utilizing a floating gate in that there is noise associated with both the switch that resets the floating gate and with the coupling of the transfer clock from the next gate onto the floating gate. In other words, there is only an indirect sensing of the charge in a floating gate structure. With the n+ diffusion, there is a direct relationship between the potential of the charge in the storage well and the potential of the electrode plate above the charge. The poly gate, which will now be pinned to a predetermined DC reference, effects shielding of the charge packet from the coupling associated with the adjacent transfer clock. In addition, there is no reset noise, and there is no concern regarding linearity being degraded by the floating gate changing potential as charge is transferred to the storage well. The operational analogy of the n* diffusion is that of water in a hose. Consider, for example, an exemplary serial to parallel type charge transfer where the charge is drained laterally from a particular storage well. Following the lateral drainage of the charge from the well, there may be mobile electrons left behind as a result of a weak electric field. If a n+ diffusion is present in the gate, the mobile electrons will be attracted to the diffusion. Accordingly, rather than requiring the electrons to traverse the entire well, the entrance of the electrons into one end of the extended well effects a nearly instantaneous equal discharge of electrons from the opposite end of the extended well for transfer out of the gate, thus reducing lateral time constants. As described earlier, the n+ diffusion can also be used in a gate having a split in the channel to maintain the split portions of a charge packet at the same potential. Due to the presence of a diffusion in each of the two channels, the two resultant potential wells can be tied together to maintain their charge packets at identical potentials. The n+ diffusion has many other possible applications in CCDs. For example, conventional CCDs typically include discrete input and output diffusions. The n+ diffusions in accordance with the present invention can be utilized as the input and output regions. In the conventional devices using separate diffusion regions, problems arise if those diffusions are not connected to voltage sources. For example, there is a limit as to how small the n+ diffusion input region can be made, and there are capacitances and non-linearities associated with the diffusion. Most p-n junctions are quite non-linear with respect to their voltage to charge relationships. These problems are avoided by gaining direct access to the first storage well and the final storage well with the use of the n+ diffusions of the present invention. In other words, the n+ diffusions in the gates accommodate direct charge injection and extraction.
It will be appreciated by those of skill in the art that while the exemplary embodiments described herein refer to the use of a n+ diffusion in a buried n-channel structure, other channel structures can be configured in accordance with the present invention. For example, the n+ diffusion can be provided in a p-type substrate to form a surface n- channel device. Alternatively, a p+ diffusion can be provided in a n-type substrate as part of a surface p- channel device, or the p+ diffusion can be provided in a p- type layer of a buried p-channel device. Accordingly, the p+ diffusion provides the same functions and advantages as described for the n+ diffusion. Furthermore, the use of a n+ or p+ diffusion in accordance with the present invention can be utilized in a quantum well structure. In such a structure, the diffusion would serve to modulate the current through the established potential well. The use of diffusions through openings or slots in gate material can also be carried out in MOS capacitor devices, but for different functional reasons than specified heretofore. The purpose of an MOS capacitor is to store a voltage, not a charge packet. An MOS capacitor does not include potential barriers and wells to allow containment of signal-dependent charge packets. The two terminals of such a capacitor are typically connected to voltage sources (sometimes switched), which cause the charge on the capacitor plates to adjust to the potential applied. In a charge-storage structure, signal-dependent charge packets are stored in potential wells, the potential of which adjusts to accommodate the charge. Hence, the operation of an MOS capacitor is distinctly different from that of a charge-storage structure. One reason for including diffusions through a slot or opening in an MOS capacitor device is to decrease the effective series resistance. Figs. 6 and 7 respectively show a plan view and a cross-sectional view of a block diagram of an MOS capacitor 60. The MOS capacitor includes a continuous gate (top plate) 62 and underlying dielectric layer 63 with openings 64 to accommodate internal diffusions 66. In large area MOS capacitors, access to the bottom plate (not shown) solely through diffusions on the edges of the gate results in high series resistance, long time constants, and therefore poor high-frequency response. By opening slots 64 in the gate and adding diffusions 66, the distance that charge must travel under the gate (in response to voltage changes) is greatly reduced. This lowers the series resistance and increases the frequency response. The shape of these slots or openings can range from small, square openings periodically spaced vertically and horizontally, to rectangular slots also arranged periodically.
A further use for the diffusions in accordance with the present invention in charge storage wells is to implement quantum-well effects. Fig. 8 shows a cross section of a block diagram of a quantum well device 80 constructed from an insulated-gate FET. The FET includes, as is well known in the art, a gate 82, a source diffusion 84, and a drain diffusion 86. According to the present invention, a very narrow slot 88 is cut into the gate 82, and thereafter a diffusion 89 is then provided through the slot into the underlying channel.
For the device 80 to exhibit quantum behavior, the slot cross section must be very narrow, for example, less than approximately 0.1 μm for silicon. Once such dimensions are achieved, the charge flowing from the source can pass through the potential well (and on to the drain) only if the charge has distinct, discrete energy levels. These energy levels are determined by the depth and dimensions of the diffusion in the slot. Multiple slots, appropriately spaced, can be used to create more complex quantum-well devices with a variety of transfer functions.
The foregoing description has been set forth to illustrate the invention and is not intended to be limiting. Since modifications of the described embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the scope of the invention should be limited solely with reference to the appended claims and equivalents thereof. What is claimed is:

Claims

I. A semiconductor device comprising: a semiconductor region including a material of a first predetermined conductivity type; an insulating layer provided on said semiconductor region; a gate electrode provided on said insulating layer, said gate electrode forming a potential well within said semiconductor region in response to a potential being applied thereto; and a diffusion of highly doped material of a second predetermined conductivity type being positioned within said semiconductor region, and which is applied through an opening in said gate electrode and said insulating layer, said diffusion being in direct ohmic contact with said potential well.
2. The semiconductor device of claim 1, wherein said device comprises a charge-coupled device.
3. The semiconductor device of claim 2, wherein said semiconductor region is a substrate which defines a surface channel.
4. The semiconductor device of claim 2, wherein said semiconductor region is a doped layer disposed on a substrate which defines a buried channel.
5. The semiconductor device of claim 1, wherein said diffusion effects a reduction in lateral time constants for the redistribution of charge across the width of the potential well.
6. The semiconductor device of claim 1 further comprising a conductive contact provided on said diffusion.
7. The semiconductor device of claim 6, wherein the potential of charge within the potential well is directly sensed via said conductive contact.
8. The semiconductor device of claim 6, wherein charge is directly injected or extracted from said potential well via said conductive contact.
9. The semiconductor device of claim 1, wherein said first predetermined conductivity type is p-type, and said second predetermined conductivity type is n-type.
10. The semiconductor device of claim 1, wherein said first and second predetermined conductivity types are n- type.
11. The semiconductor device of claim 1, wherein said first predetermined conductivity type is n-type, and said second predetermined conductivity type is p-type.
12. The semiconductor device of claim 1, wherein said first and second predetermined conductivity types are p- type.
13. The semiconductor device of claim 1, wherein said device comprises bucket-brigade device.
14. The semiconductor device of claim 1, wherein said device comprises an MOS capacitor.
15. The semiconductor device of claim 1, wherein said device comprises a quantum well device.
16. A charge-coupled device comprising: a storage phase including a gate electrode, an insulating layer, and a semiconductor region with a storage potential well, said gate electrode and insulating layer including an opening to said underlying semiconductor region; and a diffusion of a predetermined conductivity type disposed in said semiconductor region proximate to said opening and being in direct ohmic contact with said storage potential well.
17. The charge-coupled device of claim 16, wherein said predetermined conductivity type is n+.
18. The charge-coupled device of claim 16, wherein said predetermined conductivity type is p+.
19. A charge-coupled device comprising: a semiconductor substrate which is lightly doped with a material of a first conductivity type; a doped layer which is lightly doped with a material of a second conductivity type provided on said substrate to form a buried channel; an insulating layer provided on said doped layer; a gate electrode provided on said insulating layer, said gate electrode forming a potential well within said substrate in response to a potential being applied thereto; and a diffusion of highly doped material of said second conductivity type positioned within said doped layer, and applied through an opening in said gate electrode and said insulating layer, said diffusion being in direct ohmic contact with said potential well.
20. The charge-coupled device of claim 19, wherein said diffusion effects a reduction in lateral time constants for the redistribution of charge across the width of the potential well.
21. The charge-coupled device of claim 19 further comprising a conductive contact provided on said diffusion.
22. The charge-coupled device of claim 21, wherein the potential of charge within the potential well is directly sensed via said conductive contact.
23. The charge-coupled device of claim 21, wherein charge is directly injected or extracted from said potential well via said conductive contact.
24. The charge-coupled device of claim 19, wherein said first conductivity type is p-type and said second conductivity type is n-type.
25. The charge-coupled device of claim 19, wherein said first conductivity type is n-type and said second conductivity type is p-type.
PCT/US1996/015285 1995-09-29 1996-09-24 Semiconductor charge potential wells with integrated diffusions WO1997012402A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2628532A1 (en) * 1975-06-26 1977-02-10 Philips Nv SEMI-CONDUCTOR ARRANGEMENT
US4024514A (en) * 1975-06-30 1977-05-17 Honeywell Information Systems, Inc. Multiphase series-parallel-series charge-coupled device registers with simplified input clocking
DE2654316A1 (en) * 1976-11-30 1978-06-01 Siemens Ag Charge coupled semiconductor device with insulating layer capacitors - has several contacts on substrate surface with adjacent majority carrier depletion zones
US4594604A (en) * 1983-10-21 1986-06-10 Westinghouse Electric Corp. Charge coupled device with structures for forward scuppering to reduce noise
EP0309748A1 (en) * 1987-09-28 1989-04-05 Siemens Aktiengesellschaft Low feedback MOS triode

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2628532A1 (en) * 1975-06-26 1977-02-10 Philips Nv SEMI-CONDUCTOR ARRANGEMENT
US4024514A (en) * 1975-06-30 1977-05-17 Honeywell Information Systems, Inc. Multiphase series-parallel-series charge-coupled device registers with simplified input clocking
DE2654316A1 (en) * 1976-11-30 1978-06-01 Siemens Ag Charge coupled semiconductor device with insulating layer capacitors - has several contacts on substrate surface with adjacent majority carrier depletion zones
US4594604A (en) * 1983-10-21 1986-06-10 Westinghouse Electric Corp. Charge coupled device with structures for forward scuppering to reduce noise
EP0309748A1 (en) * 1987-09-28 1989-04-05 Siemens Aktiengesellschaft Low feedback MOS triode

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