Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2007—Display of intermediate tones
  • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
  • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
  • H04N3/12—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
  • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
  • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
  • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
  • G09G2300/0857—Static memory circuit, e.g. flip-flop
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/0266—Reduction of sub-frame artefacts
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2007—Display of intermediate tones
  • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
  • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2007—Display of intermediate tones
  • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
  • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
  • G09G3/2033—Display of intermediate tones by time modulation using two or more time intervals using sub-frames with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
  • G09G3/346—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on modulation of the reflection angle, e.g. micromirrors

Definitions

• the invention relates to the utilization of an array of digital light modulating elements to display an image.
• a digital light modulating element is one which is capable of modulating incident light to two different luminance levels. In the simplest case, either a bright or a dark light level would be produced. Typically the element is either light reflective or light transmissive.
• An advantage of this type of element is that it enables a display apparatus to be constructed which can be operated totally by the application of digital signals. This facilitates integration of the display and of associated digital drive circuitry on a chip.
• Examples of devices having light modulating elements of tiiis type are the well known hquid crystal device (LCD) and the less well known deformable-mirror spatial light modulator.
• a particular type of the spatial light modulator is the deformable-mirror device (DMD), which is described by Larry J. Hombeck in "Deformable-Mirror Spatial Light Modulators", SPIE, Vol. 1150, pages 86-102 (1990), which is hereby incorporated by reference.
• the DMD incorporates, on an integrated circuit chip, a matrix array of individually-addressable, electrostatically-deflectable mirrors. Each mirror produces one light-modulated pixel of an image (e.g. figures, symbols or text) to be presented to a viewer.
• Patent 5,079,544 which is hereby incorporated by reference, describes in detail various display apparatus which utilize DMDs as digital light modulating elements. Three of the drawing figures from that patent are included herein, in slightly modified form as Figures 1, 2 and 3, to facilitate a general explanation of the operation of an exemplary DMD.
• Figure 1 is a diagram of a typical DMD integrated circuit chip including a timing circuit 14, an array 16 of deformable mirror cells, a register 18 (e.g. a shift register), and first and second decoders 22 and 24, respectively.
• the deformable mirror cells may be disposed in a matrix arrangement or in some other convenient arrangement.
• a typical arrangement is a row-and-column matrix where each cell is disposed at a crossing of a respective row and column conductor or line. This type of arrangement is presumed for purposes of describing and explaining the operation of the array 16.
• a memory cell including a plurality of sub-cells for storing respective bits of a multi-bit display code, is associated with each mirror cell.
• the register 18 has a number of taps 20 for electrical connection to a bus (not shown) to enable data to be loaded into the register for transfer to respective memory cells in the array.
• the bus may provide data from a variety of different sources, such as an A/D converter driven by a video source (e.g. a television), a computer or a graphics system.
• the register 18 also has a number of outputs which are connected to respective column lines Cj, C 2 ... C N of the array 16.
• the decoder 22 has a number of outputs which are connected to respective row lines R,, R 2 ... R M of the array.
• the timing circuit 14 is electrically connected to the register 18 and to the decoders 22 and 24.
• the decoders themselves each include means, such as shift registers, for sequentially selecting the memory sub-cells in response to timing pulses from the timing circuit.
• register 18 and decoder 22 sequentially select row and column lines to direct data from the register to the memory cells associated with selected mirror cells; - decoder 22 also sequentially selects the memory sub-cells into which data from the register 18 is to be written; and decoder 24 sequentially reads the data from the memory sub-cells to activate the associated mirror cells.
• Figure 2 shows schematically an arbitrary three-bit memory cell of the DMD array 16, electrically connected to row line R,,, and column line C n .
• This figure also shows integrated circuitry associated with this memory cell, the mirror cell DM,,,,, located at the crossing of row line R,,, and column line C n , with which the memory cell is associated, and connections to the register 18 and to the decoders 22 and 24.
• This and each other memory cell in the array is formed by three single-bit inverting memory sub-cells 54,55,56 for storing respective bits of a three-bit binary display code.
• the data to be written into this memory cell is provided over column line C n from a respective output of register 18 to three electrically connected data lines 46,47,48 which, in turn, are selectively connected to inputs of the sub-cells through WRITE switching transistors 36,37,38, respectively. Selection of these transistors is controlled via row line R,, which is formed by a group of three row conductors that are electrically connected to gates of the transistors 36,37,38 via gating lines 32,31,30 respectively.
• column line is electrically connected to the data lines 46,47,48 of every memory cell in column n.
• row line R, principal is electrically connected to the gating lines 32,31,30 of every memory cell in row m.
• Reading of the stored data from the memory sub-cells is controlled by the decoder 24 having three outputs which are electrically connected via gating lines 84,85,86 to respective gates of three READ switching transistors 68,69,70.
• Outputs of the memory sub- cells are selectively connected via these transistors to an input 72 of a single-bit inverting memory cell 74.
• gating lines 84,85,86 are electrically connected to conesponding READ switching transistors for every memory cell in the array.
• the single-bit inverting memory cell 74 has an output electrically connected to the associated minor cell DMTM. Specifically, the output of memory cell 74 is directly electrically connected to a control electrode 128 and is electrically connected through an inverter 129 to a control electrode 130. As is explained in detail in the SPIE article by Hornbeck and in U.S. Patent 5,079,544, which have been incorporated by reference, when memory cell 74 produces a voltage representative of a logical ONE, this voltage effects deflection of reflective minor element 116 to an ON position represented by the dashed line 118.
• minor element 116 when memory cell 74 produces a voltage representative of a logical ZERO, this voltage effects deflection of reflective minor element 116 to an OFF position represented by the dashed line 134.
• the minor element 116 In the ON position, the minor element 116 reflects light (from a source not shown in Figure 2) and directs it toward a pixel at row m and column n on a display screen, which conesponds with the pixel represented by the memory cell. Conversely, in the OFF position, minor element 116 directs the light away from the display screen.
• Figure 3 illustrates an example of a way in which different luminance levels are achieved for each pixel, while using the simple ON and OFF approach described above.
• This figure illustrates the successive illumination of an arbitrary pixel on the display screen via the conesponding deformable minor over six successive image frame periods of duration T. Each frame period is divided into four sub-periods. During the successive periods, the minor is deflected to achieve a variety of different luminance levels as follows:
• the minor is in its OFF position, directs the light from the source of illumination away from the display screen, and effects the production of a dark pixel.
• the minor is in its ON position, directs the light toward the conesponding pixel on the display screen, and illuminates the pixel to its brightest (100%) state.
• the minor is in its OFF position for half of the frame period and is in its ON position for the remaining half of the frame period.
• the minor is in its OFF position for one quarter of the frame period and is in its ON position for the remaining three quarters of the frame period.
• the viewer looking at this pixel, time averages this off and on illumination and sees the pixel at approximately 75% of its brightest state.
• the remaining sub-periods (T 17 -T 20 and T ⁇ -T ⁇ ) illustrate operation of the minor for the same relative on and off durations as in sub-periods T 13 -T 16 and T 9 -T 12 , respectively, but in the opposite on-off sequence.
• time-weighted display codes are stored in the conesponding memory cell.
• a simple three-bit binary code may be utilized, with each higher order bit having twice the weight of the last.
• this type of weighting eight different values can be represented by a three-bit binary display code.
• the binary codes would be "000" (dark), "100” (50% brightness), "110" (75% brightness),and "111" (100% brightness).
• the decoder 24 then effects reading of the three bits by successively applying time-weighted pulses to the gating lines 84,85,86 to cause successive transfer of the bits into the single-bit memory cell 74.
• the logical values of these bits i.e. ONE or ZERO, during their storage in memory cell 74, effect conesponding deflections of the minor element 116.
• the minor element cannot be activated 100% of a frame time. Rather, a small part of each frame time T must be devoted to writing the codes into the memory sub-cells. Utilizing the four millisecond frame period set forth as an example in U.S. Patent 5,079,544, one-half millisecond could be devoted to writing the display codes into the respective pixel memory cells, leaving 3.5 milliseconds for deflecting the minor elements.
• the time-weighted pulses applied by decoder 24 to gating lines 84,85, and 86 would then have durations of two milliseconds, one millisecond, and one-half millisecond, respectively.
• the eight different binary codes obtainable with three bits would effect ON times for the minor element 116 as listed in the following table:
• DMD display apparatus in accordance with the method illustrated in Figure 3 is satisfactory.
• An improved version of that method employs longer display codes (e.g. seven-bit codes which are stored in seven-bit memory cells) to provide a greater variety of luminance levels. While this improves the quality of images displayed by the apparatus, it does not conect a disturbing artifact which occurs whenever the eyes of the viewer scan across the image, e.g. to follow a moving object. In this situation, the viewer's visual system inconectly quantifies the luminance values of certain pixels which are momentarily viewed by the human eye. In other words, the brightness of these pixels seen by the human visual system is in enor. It is an object of the invention to eliminate this artifact from images presented by arrays of digital light modulating elements.
• a first aspect of the invention provides a method of operating a display apparatus, as claimed in Claim 1.
• a second aspect of the invention provides a method of operating a display apparatus, as claimed in Claim 2.
• a third aspect of the invention provides a method of operating a display apparatus, as claimed in Claim 3.
• a fourth aspect of the invention provides a method of operating a display apparatus, as claimed in Claim 7.
• a fifth aspect of the invention provides a method of operating a display apparatus, as claimed in Claim 12.
• the digital light elements may be digital light modulating elements as present in a LCD or DMD.
• the digital light elements may also comprise plasma pixels which can be in an on-state to generate light or in an off-state in which no light is generated. It is believed that this occurs because, as the eye scans, it views each pixel only during a portion of a frame period.
• the perceived brightness of the pixel will be in enor. For example, if the eye views the pixel represented by Figure 3 during only sub-period T , the viewer will inconectly see the pixel at 100% brightness. Alternatively, if the eye views the same pixel during the last half of sub-period T 22 and the first half of sub-period T ⁇ the viewer will conectly see the pixel at 50% brightness. Conversely, the eye will conectly perceive the brightness of the pixel regardless of when it is viewed during either the first (T T 4 ) or second (T 5 -T g ) frame period.
• each bit of a display code has a value representing either a first state, such as an ON position of a DMD minor, or a second state, such as an OFF position of a DMD minor.
• each bit of the code has a respective weight conesponding to a duration that is equal to a predefined percentage of the frame period.
• the activation of the element into the state represented by a first bit is interrupted at least once while the element is activated into the state represented by a different one of the bits in the code.
• the above mentioned first bit need not be the most significant bit of the code.
• each display code comprises a group of bits having respective values representing either an ON state or an OFF state, and a sub ⁇ group of the bits has a collective weight conesponding to a collective activation duration which is greater than one-half of the frame period. While activating the associated digital light modulating element into the states represented by the bits in the group, for the respective activation durations conesponding to the weights of the bits, the element is repeatedly sequentially activated into the states represented by the bits in the sub-group to cumulatively achieve the collective activation duration.
• each display code also comprises a group of bits having respective values representing either an ON state or an OFF state.
• One of the has a weight conesponding to a minimum duration which is no greater than the weight of any of the other bits in the group.
• a sub-group of the bits each has a respective weight conesponding to a duration which is at least twice the minimum duration and collectively have a weight conesponding to a collective duration.
• the element While activating the associated digital light modulating element into the states represented by the bits in the group, for the respective activation durations conesponding to the weights of the bits, the element is repeatedly sequentially activated into the states represented by the bits in the sub-group for respective periods which are at least equal to the minimum duration to cumulatively achieve the collective activation duration.
• each display code comprises a group of bits having respective values representing either an ON or an OFF state
• the group comprises first and second sub-groups of bits.
• the first sub-group one of the bits has a weight conesponding to a minimum duration which is no greater than the weight of any of the other bits in this sub-group.
• each of the bits has a weight conesponding to a duration which is at least twice the minimum duration, and the bits in this sub-group have a collective weight conesponding to a collective activation duration.
• the element While activating the associated digital light modulating element into the states represented by the bits of the associated code, the element is repeatedly sequentially activated into the states represented by the bits in the second sub-group for respective periods which are at least equal to the minimum duration to cumulatively achieve the collective activation duration.
• Figure 1 is a diagram of a.known deformable minor device constructed on a single substrate.
• Figure 2 is a schematic diagram of a single cell of the device of Figure 1.
• Figure 3 is a generalized timing diagram showing a prior art method of duty- cycle modulating cells in the deformable minor device of Figure 1.
• Figure 4 is a timing diagram showing a prior art method of duty-cycle modulating cells in the deformable minor device of Figure 1, using a seven-bit display code.
• Figure 5 is a timing diagram showing distributed duty-cycle modulation in accordance with an embodiment of the invention, using a seven-bit display code.
• Figure 6 is a timing diagram showing distributed duty-cycle modulation in accordance with another embodiment of the invention, using a seven-bit display code.
• Figures 4 and 5 illustrate two exemplary methods of operation of a DMD having a seven-bit memory cell associated with each minor cell. Specifically, Figure 4 illustrates operation in accordance with the prior art method described in the Background of the Invention, while Figure 5 illustrates operation in accordance with a first embodiment of the invention.
• each frame period T would have a duration of approximately 16.7 ms for presenting a monochromatic image or approximately 5.6 ms for presenting each of three successive red-green-blue (RGB) images to produce a composite polychromatic image.
• RGB red-green-blue
• each of the RGB images would be produced in a respective frame period having READ and WRITE portions of 4.2 and 1.3 ms, respectively.
• the READ and WRITE portions could occupy different portions of the frame period, depending on the particular display apparatus.
• the READ and WRITE cycles could occur simultaneously, with the READ cycle occupying the entire frame period.
• each higher order bit of the display code has a value conesponding to twice that of the last, with the least significant bit Bo having a weight conesponding to a duration of either 0.1 ms for a monochromatic frame period or 0.0333 ms for a polychromatic frame period.
• the exemplary 1001101 display code would activate the associated minor into its ON state for approximately 61% of the READ portion of the frame period. This is also 61 % of the maximum brightness obtainable, which occurs when the minor is in its ON state for 100% of the READ portion.
• Figure 5 illustrates how this artifact is avoided by activating the minor in accordance with a first embodiment of the invention. That is, activation of the minor into the state represented by most significant bit B 6 is interrupted while the minor is activated into the states represented by the bits B 5 and B 4 .
• the minor is sequentially activated into the states represented by the bits B 6 B 5 B 4 for respective periods of .4 ms, .2 ms and .1 ms, and this sequence is repeated until it occurs sixteen times to cumulatively achieve the full activation duration of 11.2 ms for these three bits.
• each of these three bit durations is separated into sixteen periods which are uniformly distributed throughout the cumulative 11.2 ms duration for the three bits.
• the viewer is likely to see the pixel at an approximately conect brightness level. That is, if the eye views the pixel for any .7 ms or longer portion of the 11.2 ms activation duration for the most significant bits B «B 5 B 4 , the viewer will see an approximately conect brightness.
• the brightness seen after viewing the pixel for any .7 ms portion of the 11.2 ms duration will be 60% rather than the conect brightness of 61%.
• Figure 6 illustrates an embodiment of the invention which produces an accurate brightness interpretation regardless of when the eye views the pixel. This is achieved by separating each of the six most-significant-bit durations into multiple minor-activation periods and by distributing these periods and the minor-activation duration for the least significant bit B 0 uniformly throughout the READ portion of the frame period.
• the same binary-weighted display code and READ and WRITE durations are used to facilitate comparison with Figures 4 and 5.
• the minor is sequentially activated into the states represented by the bits B 6 B 5 B 4 and this sequence is repeated until it occurs sixteen times. However, the sixteen B 6 B 5 B 4 sequences are now distributed throughout the entire minor activation duration, conesponding to the READ portion of the frame period.
• the minor is sequentially activated into the states represented by the bits for the respective periods of .4 ms, .2 ms and .1 ms, and the sixteen occunences of this sequence again utilize 11.2 ms of the complete 12.7 ms minor activation duration.
• the first occunence of this B 6 B 5 B 4 sequence is labelled.
• the minor activation durations for more- significant bits B 3 , B 2 , and Bj are each separated into multiple minor-activation periods, and these periods and the minor-activation duration for the least significant bit B 0 are inserted between the B 6 B 5 B 4 sequences.
• each of these periods is .1 ms long, which is equal to the B 0 duration.
• the invention is not limited to such pattems. Rather, the distribution pattems may be adapted to the type of imagery with which the invention is used and may be, for example, random or some other type of non-uniform distribution. Altematively, the pattem could be optimized to reduce the number of times which the minors must be switched from one state to the other during each frame period, thereby prolonging minor life.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)
• Liquid Crystal Display Device Control (AREA)
• Control Of El Displays (AREA)

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• 1995
  • 1995-06-27 US US08/495,290 patent/US5751264A/en not_active Expired - Fee Related
• 1996
  • 1996-05-31 JP JP9504273A patent/JPH10505436A/ja not_active Ceased
  • 1996-05-31 WO PCT/IB1996/000526 patent/WO1997001839A2/en not_active Ceased

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