WO1996039710A2 - Method for etching photolithographically produced quartz crystal blanks for singulation - Google Patents

Method for etching photolithographically produced quartz crystal blanks for singulation Download PDF

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Publication number
WO1996039710A2
WO1996039710A2 PCT/US1996/004565 US9604565W WO9639710A2 WO 1996039710 A2 WO1996039710 A2 WO 1996039710A2 US 9604565 W US9604565 W US 9604565W WO 9639710 A2 WO9639710 A2 WO 9639710A2
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WO
WIPO (PCT)
Prior art keywords
quartz
wafer
blank
channel
channels
Prior art date
Application number
PCT/US1996/004565
Other languages
French (fr)
Other versions
WO1996039710A3 (en
Inventor
Kevin L. Haas
Robert S. Witte
Charles L. Zimnicki
Iyad Alhayek
Original Assignee
Motorola Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc. filed Critical Motorola Inc.
Priority to EP96912542A priority Critical patent/EP0830732A4/en
Priority to JP9500458A priority patent/JPH11509052A/en
Publication of WO1996039710A2 publication Critical patent/WO1996039710A2/en
Publication of WO1996039710A3 publication Critical patent/WO1996039710A3/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/08—Shaping or machining of piezoelectric or electrostrictive bodies
    • H10N30/082—Shaping or machining of piezoelectric or electrostrictive bodies by etching, e.g. lithography

Definitions

  • the present invention relates generally to piezoelectric devices and, in particular, to a method for etching photolithographically produced quartz crystal blanks for singulation.
  • Piezoelectric elements are known to include various types and shapes of devices produced from various piezoelectric materials. Typical piezoelectric elements consist of substantially rectangular or round plates made from quartz. These piezoelectric elements are commonly used for frequency control in electronic devices such as, computers, cellular phones, pagers, radios and wireless data devices, etc. As consumer demand continually drives down the size and cost of this equipment, the need for piezoelectric devices to be smaller, lower cost and automatable has become even greater.
  • Automated mounting equipment typically requires that each piezoelectric element, as presented to the mounting equipment, be uniform in size and shape.
  • this equipment can include a robotic machine with a vision system, a pick-and-place system, and the like.
  • automation systems require tighter and tighter tolerances from the elements to be mounted in order to reduce breakage, misplacement and jamming.
  • FIG. 1 prior art photolithographically produced piezoelectric elements 10 are shown before being singulated. These elements 10 are defined by etching a pattern through a parent wafer 12 but leaving each element 10 connected to the wafer 12 by one or more relatively thin bridge sections 16. "These bridges 16 have been designed to retain the full thickness of the parent wafer 12, and are necessary in order to have each element 10 remain in place so that further wafer 12 processing can be done in bulk. The use of bridges 16 avoids a handling problem that would occur with individual elements 10, as shown in FIG. 2.
  • Photolithographic processing of piezoelectric wafers 12 includes coating a piezoelectric wafer 12 with metal 24 and photoresist 26, respectively, as shown in FIG. 4. This is followed by developing the photoresist 26, etching the metal 24, and etching through the piezoelectric wafer 12 to define each element 10. Additional processing may include photoresist stripping, wafer cleaning and element 10 testing procedures which are much easier to accomplish when all the elements 10 are held in known positions on the parent wafer 12. However, after fully processing the wafer 12 it eventually becomes necessary to singulate the elements 10 from the parent wafer 12 in order to mount the elements 10 in individual packages. To assist in singulation, a relatively large relief area 20 (in FIG.
  • FIG. 2 shows a prior art singulated piezoelectric element 10. Singulation of the elements 10 from their parent wafer 12 by breaking the bridges 16 near the separation edges 14 can cause unpredictable damage. Many times, the body of the element 10 will fracture instead of the bridges 16. This type of breakage destroys the usability of the element 10, increasing scrap, lowering yields and raising costs. Even when the bridges 16 fracture as required, there occasionally remains irregular spurs 18 on the separation edge 14 of the piezoelectric element 10 where the bridges 16 did not break cleanly. Often, these irregular spurs 18 on the separation edge 14 are so pronounced that it is not possible to mount the element on that edge 14. Therefore, it is necessary to visually observe the quality of the edges of the piezoelectric element in order to mount the element on it's best edge, usually being the opposite edge 28. This type of visual inspection is a hindrance to automation.
  • FIG. 3 shows a cross-sectional view across the relief area 20 used in prior art etching of piezoelectric elements 10.
  • the widths of the etched-through relief areas 20 and boundaries 22 are so large that anisotropic etching of the piezoelectric material and alignment of the top and bottom photolithographic patterning are essentially not a consideration in the prior art.
  • the prior art assumes that all areas etched from both the top and bottom of a wafer 12 should always intersect (shown as item 20), to etch through the wafer 12.
  • piezoelectric elements are very sensitive to their environment. Any particulates that contact the surface of the piezoelectric element can alter its frequency. Typically, an element is hermetically sealed under very controlled conditions. However, these sealing processes do not address particulate contamination that may occur during singulation.
  • Prior art cleaning can include mechanical brushing, wet processing, ultrasonic cleaner, plasma cleaner and the like. These solutions are problematic in that there is the potential of introducing more contamination than was originally present, unless these cleaning processes are very well controlled and monitored.
  • the present invention solves this problem by minimizing the generation of particulate matter before potential problems occur. In addition, extra cleaning processes can be avoided, thus lowering costs.
  • a significant portion of the cost of a quartz blank is in processing, yield and labor. Scrap costs due to yield losses are to be minimized if at all possible. Yields losses result from breakage and contamination of blanks. Reducing inspection steps and operator involvement can save money and reduce the possibility for error. Improvements in automatability, yield, cost and quality can be achieved if an inherently clean and repeatable method for singulating uniform quartz blanks is used.
  • FIG. 1 shows a perspective view of a prior art photolithographically produced quartz wafer before singulation
  • FIG. 2 shows a perspective view of a prior art quartz blank after singulation
  • FIG. 3 shows a cross-sectional view along lines 3-3 in FIG. 1 , of a prior art quartz wafer showing the etched through area between the quartz blank and wafer;
  • FIG. 4 shows a cross-sectional view of a quartz wafer as coated with metal and photoresist layers, respectively, in accordance with the present invention
  • FIG. 5 shows a cross-sectional view of the quartz wafer with the photoresist and metal layers removed from a predetermined pattern, in ' accordance with the present invention
  • FIG. 6 shows a cross-sectional view of the quartz wafer with channels etched in alignment with the crystalographic orientation of the quartz, in accordance with the present invention
  • FIG. 7 shows a perspective view of a photolithographically produced quartz wafer before singulation, with an enlarged detailed view of the etched channels, in accordance with the present invention.
  • FIG. 8 shows a block diagram for a method of singulating photolithographically produced quartz crystal blanks, in accordance with the present invention.
  • the present invention provides a method for etching photolithographically produced quartz crystal blanks and similar piezoelectric elements for singulation.
  • a quartz wafer 102 is provided having a metal layer 108 subsequently coated with a photoresist layer 110 on both sides of the wafer 102.
  • the metal layer 108 may include various numbers or configurations of conductive materials, metals or alloys in various numbers of layers. Most commonly, gold, silver, copper or aluminum is used for the metal layer 108 because of the enhanced conductivity that these materials possess over most other materials.
  • the metal layers 108 are comprised of a first layer of chromium and a second layer of gold on each side of the quartz wafer 102.
  • the amount, type and number of conductive layers used can vary.
  • the metal layers 108 should be substantially impervious to quartz etchants because the photoresist layers 110 will not completely inhibit the quartz etchants.
  • the metal layers 108 may be deposited on the wafer 102 using various conventional methods known in the art, including, but not limited to, evaporative deposition, sputter deposition, chemical vapor deposition, e-beam deposition and ion deposition.
  • e-beam evaporative deposition equipment is used to deposit the metal layers 108, such as the evaporators available from CHA Industries (of Menlo Park, CA).
  • the photoresist layers 110 may be of a negative or positive exposure type. It should be recognized that most types of photoresist will work equally well for this invention. This is because the line widths being used, about 0.5 mils or larger, are much larger and easier to work with than thin applications.
  • the photoresist may be spun on using conventional, commercial photoresist spinner equipment, such as those manufactured by Solitec (of Santa Clara, CA).
  • metal and photoresist layers 108, 110 are provided on both sides of the quartz wafer 102.
  • a photoresist layer 110 may be provided on only one surface of the quartz wafer 102. In this case, the quartz wafer 102 would be patterned only on the side coated with the photoresist layer 110.
  • the photoresist layer 1 10 is cured in a convection type, air vented oven (such as one manufactured by Blue-M Electric of Watertown, Wl).
  • the quartz wafer 102 is shown after selected portions of the photoresist and metal layers 108, 1 10 have been patterned, developed and etched.
  • the photoresist layer 110 was first exposed to a predetermined pattern 1 12 with ultraviolet light.
  • the predetermined pattern 112 is defined on the wafer 102 by an ultraviolet exposure system using a photomask.
  • a Hybrid Technology Group, Inc. Series 80 mask aligner manufactured by HTG, Inc. of San Jose, CA
  • HTG, Inc. of San Jose, CA a Hybrid Technology Group, Inc. Series 80 mask aligner
  • various other mask aligner systems could be utilized, since line width tolerances are not critical in this application.
  • the photoresist layer 110 is developed in a photoresist developer bath, and rinsed in a deionized water bath. Then the metal layers 108 are etched away in a metal etch bath followed by a rinse in a deionized water bath. This process reveals a portion of the surface of the quartz wafer 102.
  • each of the developer, rinse and metal etch baths are manufactured by Semifab, Inc. (of Hollister, CA). However, as should be understood, other equipment can be utilized in this connection. In fact, most suitable photolithographic processing equipment may be used in connection with this invention.
  • the quartz wafers 102 are then transferred to a quartz etchant bath for etching the revealed portions of the quartz wafer 102 (as shown in FIG. 6). After quartz etching, the wafers 102 are rinsed in deionized water. The wafers 102 are then stripped of their photoresist layers in a stripping bath, and again rinsed in the deionized water bath.
  • each of the quartz etch, rinse and stripper baths are manufactured by Semifab, Inc. (of Hollister, CA). Other suitable photolithographic processing equipment may be used.
  • the quartz blanks 100 are then cleaved from the quartz wafer 102 in a simple manual singulation jig (shown as item 130 in the insert of FIG. 7).
  • the jig 130 clamps the wafer near a breakout edge 106 of each quartz blank 100, and a bending force 134 is manually applied near a free edge 104 of each quartz blank 100 to fracture 132 a quartz channel 1 14, singulating the blank 100.
  • the precise configuration of the clamp 130 is not critical to the invention. However it is important that the bending force 134 is applied so as to prevent scratching of the surface of the blank 100. Preferably, the bending force 134 is applied directly at or near the free edge 104 of the quartz blank 100. In a preferred embodiment, this operation is automated.
  • the first major step of the invention is providing a quartz wafer 102 with metal and photoresist layers 108, 110, identified as item 202.
  • the quartz wafer 102 is evaporated with at least 10 A of chromium followed by at least 200 A of gold.
  • the exact thickness of the metal layers 108 are not critical to the invention.
  • the chromium layer should be at least thick enough to prevent the subsequent gold layer from penetrating through the chromium layer during deposition, and the gold layer should be thick enough to be electrically conductive and substantially nonporous to the quartz etchant.
  • the metal layers 108 should be nonporous to quartz etchants because the photoresist layers 1 10 may not sufficiently inhibit penetration of the quartz etchants to areas of the quartz wafer 102 that should remain unetched.
  • about 500 A of chromium is deposited followed by about 4000 A of gold.
  • a photoresist layer 110 is then spun on per the manufacturer's recommendations.
  • a Shipley MicropositTM S1400-31 photoresist (available from Shipley of Newton, MA) is used for the photoresist layers 110.
  • This is followed by baking in a convection type, air vented oven (such as one manufactured by Blue-M Electric of Watertown, Wl) at a temperature of about 90° C for about 15 minutes for each side of the wafer 102.
  • a convection type, air vented oven such as one manufactured by Blue-M Electric of Watertown, Wl
  • Other similar photoresists may be used with acceptable results.
  • both sides of the wafer 102 are provided with photoresist layers 110.
  • the photoresist layer 110 may be provided on only one side of the wafer 102.
  • the next process step 204 provides for removing a predetermined pattern 112 from portions of the quartz wafer 102.
  • the quartz wafer 102 is exposed to ultraviolet light, through a glass photomask, at a light concentration of about 25 milliwatts per square centimeter for a period of about 6 seconds.
  • the predetermined pattern 112 defining the channel 114 is of about 0.5 mils in width for a quartz wafer thickness 128 of about 3.9 mils.
  • the quartz wafer 102 is placed in a developing bath of Shipley MicropositTM 351 developer (available from Shipley of Newton, MA) at about 25° C for about 1.5 minutes, followed by a deionized water rinse for at least 30 seconds.
  • Shipley MicropositTM 351 developer available from Shipley of Newton, MA
  • the quartz wafer is then placed in a gold etchant bath of Techni-stripTM AU (sodium cyanide type) (available from Lawrence Packaging Supply of Newark, NJ) at about 25° C for about 1 to about 5 minutes, depending on the thickness of the metal layer 108.
  • Techni-stripTM AU sodium cyanide type
  • the use of a preferred 4000 A thick gold layer requires about 4 minutes of gold etch time.
  • This process step is followed by a deionized water rinse for at least 30 seconds.
  • the quartz wafer is then placed in a commercial chrome etchant such as type TFD at about 25° C for about 2 minutes followed by a deionized water rinse for at least 30 seconds.
  • the next process step 206 provides for the etching of the quartz wafer 102.
  • the quartz wafer 102 is placed into a supersaturated solution of about 60 percent hydrofluoric acid and about 40 percent ammonium fluoride at about 80° C for about 45 minutes, depending on the starting quartz wafer thickness 128.
  • Other commercially available quartz etchants will work equally well.
  • the quartz etchant will etch preferentially substantially along the atomic planes 122 of the quartz wafer 102. During etching, the atomic planes eventually define etched walls 124 of the channel 114. The confines of the narrow channel 114 cause a localized depletion of active quartz etchant in the channel 114.
  • the depletion of the active quartz etchant causes the bottom of the narrow channel 1 16 to etch more slowly than the wider periphery 118 around the remainder of the quartz blank 100.
  • the bottom of the channel 116 will have penetrated to about 25% percent of the quartz wafer thickness 128 while the periphery 118 around the quartz blank 100 shall have etched completely through the wafer 102.
  • the quartz wafer is originally provided with the Z-axis of the quartz aligned substantially perpendicular 136 to the channel 114.
  • This particular alignment provides for non-intersecting etched walls 124 of the channels 1 14 due to the particular alignment of the atomic planes 122.
  • the non- intersecting, partially etched channels 114 provide at least a partial mechanical weakening of the quartz wafer 102 near the breakout edge 106 of the quartz blank 100 so that a clean singulation may be obtained when a bending force 134 is applied to the quartz blank 100.
  • non-intersecting channels 114 allow deeper etching without mechanically weakening the quartz wafer 102 as much as co-linear etch channels 114 would mechanically weakening the wafer 102. Also, non- intersecting channels 114 require less etch rate discrimination between the narrow channel 1 14 and the wider periphery 1 18 defining the remainder of the quartz blank 100.
  • this invention allows the use of a wider channel 114 geometry than might otherwise be needed.
  • the deeper etching allows a substantially uniform bottom of the quartz channel 116 to be established for cleaner fracturing 132.
  • this invention can be used to etch intersecting, co-linear etch channels 114, but co-linear etch channels 114 may weaken the quartz wafer 102 before a substantially uniform channel bottom 1 16 is established.
  • the next process step provides for the stripping 208 of the photoresist layer 1 10 from the quartz wafer 102, as shown in block 208 in FIG. 8.
  • the photoresist may be stripped in a Shipley MicropositTM 142A Remover (available from Shipley of
  • the final major process step provides for the cleaving 210 of each quartz blank 100 from the quartz wafer 102 by clamping 130 the wafer 102 near the breakout edge 106 of each quartz blank 100 and applying a bending force 134 to the quartz blank 100.
  • the bending force 134 causes a tensile stress concentration in the bottom of the channel 116. This stress propagates a fracture 132 substantially along the atomic planes 122 of the quartz wafer 102 thereby singulating the blank 100 from the wafer 102.
  • the bending force 134 is applied in a manner so as to substantially prevent scratching of the surface of the blank 100.
  • the bending force 134 is applied at the free edge 104 of the quartz blank 100.
  • the advantage provided by the fracturing 132 the bottom of the channel 116 along atomic planes 122, is to minimize fragmentation of the quartz wafer 102, which minimizes particulate contamination on the surface of the quartz blank 100. Also, this fracturing 132 provides a cleaner and more efficiently and effectively singulated quartz blank 100, which has a smooth breakout edge 106 which can be mounted equally as well as the free edge 104 of the blank 100. Less inspection and quality control processing are required, and the clean singulation of the quartz blank 100 contributes to increasing yields and can subsequently lower costs since fewer quartz blanks 100 are broken during the singulation process. Also, the uniform dimension of the breakout edge 106 of the quartz blank 100 readily allows the use of automation without placement problems due to blank 100 irregularities.

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Abstract

A method for etching (200) photolithographically produced quartz crystal blanks for singulation. First, a quartz wafer is plated on both sides with metal and subsequently coated on both sides with photoresist (202). Second, the photoresist is patterned and developed and the metal layers etched to define the periphery of a quartz blank with a narrow quartz channel exposed between the blank to be singulated and the parent quartz wafer (204). Third, the quartz channel is preferentially etched partially into the wafer along parallel atomic planes to provide a mechanically weak junction between the quartz wafer and the blank to be singulated, while the periphery around the remainder of the quartz blank is etched completely through the parent quartz wafer (206). Fourth, the photoresist layers are stripped from the quartz wafer (208). Finally, the quartz blank is cleaved substantially along the bottom of the quartz channel to singulate the crystal blank from the wafer (210).

Description

METHOD FOR ETCHING PHOTOLITHOGRAPHICALLY PRODUCED QUARTZ CRYSTAL BLANKS FOR SINGULATION
Field of the Invention
The present invention relates generally to piezoelectric devices and, in particular, to a method for etching photolithographically produced quartz crystal blanks for singulation.
Background of the Invention
Piezoelectric elements are known to include various types and shapes of devices produced from various piezoelectric materials. Typical piezoelectric elements consist of substantially rectangular or round plates made from quartz. These piezoelectric elements are commonly used for frequency control in electronic devices such as, computers, cellular phones, pagers, radios and wireless data devices, etc. As consumer demand continually drives down the size and cost of this equipment, the need for piezoelectric devices to be smaller, lower cost and automatable has become even greater.
Automated mounting equipment typically requires that each piezoelectric element, as presented to the mounting equipment, be uniform in size and shape. Typically, this equipment can include a robotic machine with a vision system, a pick-and-place system, and the like. As the size of the devices to be mounted shrink, automation systems require tighter and tighter tolerances from the elements to be mounted in order to reduce breakage, misplacement and jamming.
In FIG. 1 , prior art photolithographically produced piezoelectric elements 10 are shown before being singulated. These elements 10 are defined by etching a pattern through a parent wafer 12 but leaving each element 10 connected to the wafer 12 by one or more relatively thin bridge sections 16. "These bridges 16 have been designed to retain the full thickness of the parent wafer 12, and are necessary in order to have each element 10 remain in place so that further wafer 12 processing can be done in bulk. The use of bridges 16 avoids a handling problem that would occur with individual elements 10, as shown in FIG. 2.
Photolithographic processing of piezoelectric wafers 12 is known in the art and includes coating a piezoelectric wafer 12 with metal 24 and photoresist 26, respectively, as shown in FIG. 4. This is followed by developing the photoresist 26, etching the metal 24, and etching through the piezoelectric wafer 12 to define each element 10. Additional processing may include photoresist stripping, wafer cleaning and element 10 testing procedures which are much easier to accomplish when all the elements 10 are held in known positions on the parent wafer 12. However, after fully processing the wafer 12 it eventually becomes necessary to singulate the elements 10 from the parent wafer 12 in order to mount the elements 10 in individual packages. To assist in singulation, a relatively large relief area 20 (in FIG. 1 ), is etched through the parent wafer 12 near the separation edge 14 at the same time the element 10 is being defined, by etching through a remaining boundary 22 around the periphery of the element 10. This etching process leaves the element 10 connected to the parent wafer 12 by one or more bridges 16 which retain the full thickness of the parent wafer 12. The use of a relief area 20 near the separation edge 14 of the element 10 concentrates the breaking stresses of singulation at or near the bridges 16.
FIG. 2 shows a prior art singulated piezoelectric element 10. Singulation of the elements 10 from their parent wafer 12 by breaking the bridges 16 near the separation edges 14 can cause unpredictable damage. Many times, the body of the element 10 will fracture instead of the bridges 16. This type of breakage destroys the usability of the element 10, increasing scrap, lowering yields and raising costs. Even when the bridges 16 fracture as required, there occasionally remains irregular spurs 18 on the separation edge 14 of the piezoelectric element 10 where the bridges 16 did not break cleanly. Often, these irregular spurs 18 on the separation edge 14 are so pronounced that it is not possible to mount the element on that edge 14. Therefore, it is necessary to visually observe the quality of the edges of the piezoelectric element in order to mount the element on it's best edge, usually being the opposite edge 28. This type of visual inspection is a hindrance to automation.
FIG. 3 shows a cross-sectional view across the relief area 20 used in prior art etching of piezoelectric elements 10. The widths of the etched-through relief areas 20 and boundaries 22 are so large that anisotropic etching of the piezoelectric material and alignment of the top and bottom photolithographic patterning are essentially not a consideration in the prior art. The prior art assumes that all areas etched from both the top and bottom of a wafer 12 should always intersect (shown as item 20), to etch through the wafer 12.
Another consideration in the singulation of photolithographically produced blanks is that piezoelectric elements are very sensitive to their environment. Any particulates that contact the surface of the piezoelectric element can alter its frequency. Typically, an element is hermetically sealed under very controlled conditions. However, these sealing processes do not address particulate contamination that may occur during singulation.
Previously, on photolithographically produced elements, singulation of the elements caused unpredictable fragmentation of the bridges (shown as 16 in FIG 1 ). These bridges would fragment into pieces having a large variety of sizes. The smallest fragments adhere to the surface of the piezoelectric element by cohesive forces. The presence of this microscopic particulate matter on the surface of an element causes alterations of the frequency response of the element at varying input power levels. This phenomenon is known is "drive level dependence" or "starting resistance" in the art.
The most common method for eliminating this microscopic particulate is to add various cleaning stages to the process. Prior art cleaning can include mechanical brushing, wet processing, ultrasonic cleaner, plasma cleaner and the like. These solutions are problematic in that there is the potential of introducing more contamination than was originally present, unless these cleaning processes are very well controlled and monitored. The present invention solves this problem by minimizing the generation of particulate matter before potential problems occur. In addition, extra cleaning processes can be avoided, thus lowering costs.
A significant portion of the cost of a quartz blank is in processing, yield and labor. Scrap costs due to yield losses are to be minimized if at all possible. Yields losses result from breakage and contamination of blanks. Reducing inspection steps and operator involvement can save money and reduce the possibility for error. Improvements in automatability, yield, cost and quality can be achieved if an inherently clean and repeatable method for singulating uniform quartz blanks is used.
There is a need for an improved method for singulating quartz blanks, that: (i) is low cost; (ii) improves yields; (iii) minimizes the potential for damage to the piezoelectric element; (iv) reduces particulate contamination on the piezoelectric element due to ineffectual breakout of the piezoelectric element; (v) reduces processing; and (vi) produces substantially uniform blank dimensions, which can contribute to simplifying mounting and reducing the need for inspection.
Brief Description of the Drawings
FIG. 1 shows a perspective view of a prior art photolithographically produced quartz wafer before singulation;
FIG. 2 shows a perspective view of a prior art quartz blank after singulation;
FIG. 3 shows a cross-sectional view along lines 3-3 in FIG. 1 , of a prior art quartz wafer showing the etched through area between the quartz blank and wafer;
FIG. 4 shows a cross-sectional view of a quartz wafer as coated with metal and photoresist layers, respectively, in accordance with the present invention;
FIG. 5 shows a cross-sectional view of the quartz wafer with the photoresist and metal layers removed from a predetermined pattern, in' accordance with the present invention;
FIG. 6 shows a cross-sectional view of the quartz wafer with channels etched in alignment with the crystalographic orientation of the quartz, in accordance with the present invention;
FIG. 7 shows a perspective view of a photolithographically produced quartz wafer before singulation, with an enlarged detailed view of the etched channels, in accordance with the present invention; and
FIG. 8 shows a block diagram for a method of singulating photolithographically produced quartz crystal blanks, in accordance with the present invention.
Detailed Description of the Preferred Embodiment
The present invention provides a method for etching photolithographically produced quartz crystal blanks and similar piezoelectric elements for singulation.
As shown in FIG. 4, a quartz wafer 102 is provided having a metal layer 108 subsequently coated with a photoresist layer 110 on both sides of the wafer 102. The metal layer 108 may include various numbers or configurations of conductive materials, metals or alloys in various numbers of layers. Most commonly, gold, silver, copper or aluminum is used for the metal layer 108 because of the enhanced conductivity that these materials possess over most other materials. Preferably, the metal layers 108 are comprised of a first layer of chromium and a second layer of gold on each side of the quartz wafer 102. However, it should be recognized that the amount, type and number of conductive layers used can vary. In this instance, chromium provides the advantage of good adhesion to the quartz wafer 102, and gold has the advantages of good conductivity and corrosion resistance. Preferably, the metal layers 108 should be substantially impervious to quartz etchants because the photoresist layers 110 will not completely inhibit the quartz etchants. The metal layers 108 may be deposited on the wafer 102 using various conventional methods known in the art, including, but not limited to, evaporative deposition, sputter deposition, chemical vapor deposition, e-beam deposition and ion deposition. Preferably, e-beam evaporative deposition equipment is used to deposit the metal layers 108, such as the evaporators available from CHA Industries (of Menlo Park, CA).
The photoresist layers 110 may be of a negative or positive exposure type. It should be recognized that most types of photoresist will work equally well for this invention. This is because the line widths being used, about 0.5 mils or larger, are much larger and easier to work with than thin applications. The photoresist may be spun on using conventional, commercial photoresist spinner equipment, such as those manufactured by Solitec (of Santa Clara, CA).
In a preferred embodiment, metal and photoresist layers 108, 110 are provided on both sides of the quartz wafer 102. Alternatively, a photoresist layer 110 may be provided on only one surface of the quartz wafer 102. In this case, the quartz wafer 102 would be patterned only on the side coated with the photoresist layer 110. After coating the wafer 102 with the photoresist layer 1 10, the photoresist layer 1 10 is cured in a convection type, air vented oven (such as one manufactured by Blue-M Electric of Watertown, Wl).
Referring to FIG. 5, the quartz wafer 102 is shown after selected portions of the photoresist and metal layers 108, 1 10 have been patterned, developed and etched. The photoresist layer 110 was first exposed to a predetermined pattern 1 12 with ultraviolet light. The predetermined pattern 112 is defined on the wafer 102 by an ultraviolet exposure system using a photomask. In a preferred embodiment, a Hybrid Technology Group, Inc. Series 80 mask aligner (manufactured by HTG, Inc. of San Jose, CA) is used, to define the predetermined pattern 112 on one or both sides of the quartz wafer 102. However, it should be understood that various other mask aligner systems could be utilized, since line width tolerances are not critical in this application.
After exposure, the photoresist layer 110 is developed in a photoresist developer bath, and rinsed in a deionized water bath. Then the metal layers 108 are etched away in a metal etch bath followed by a rinse in a deionized water bath. This process reveals a portion of the surface of the quartz wafer 102. In a preferred embodiment, each of the developer, rinse and metal etch baths are manufactured by Semifab, Inc. (of Hollister, CA). However, as should be understood, other equipment can be utilized in this connection. In fact, most suitable photolithographic processing equipment may be used in connection with this invention.
The quartz wafers 102 are then transferred to a quartz etchant bath for etching the revealed portions of the quartz wafer 102 (as shown in FIG. 6). After quartz etching, the wafers 102 are rinsed in deionized water. The wafers 102 are then stripped of their photoresist layers in a stripping bath, and again rinsed in the deionized water bath. In a preferred embodiment, each of the quartz etch, rinse and stripper baths are manufactured by Semifab, Inc. (of Hollister, CA). Other suitable photolithographic processing equipment may be used.
The quartz blanks 100 are then cleaved from the quartz wafer 102 in a simple manual singulation jig (shown as item 130 in the insert of FIG. 7). The jig 130 clamps the wafer near a breakout edge 106 of each quartz blank 100, and a bending force 134 is manually applied near a free edge 104 of each quartz blank 100 to fracture 132 a quartz channel 1 14, singulating the blank 100. The precise configuration of the clamp 130 is not critical to the invention. However it is important that the bending force 134 is applied so as to prevent scratching of the surface of the blank 100. Preferably, the bending force 134 is applied directly at or near the free edge 104 of the quartz blank 100. In a preferred embodiment, this operation is automated.
Referring to FIGs. 4 and 8, the first major step of the invention is providing a quartz wafer 102 with metal and photoresist layers 108, 110, identified as item 202. In a preferred embodiment, the quartz wafer 102 is evaporated with at least 10 A of chromium followed by at least 200 A of gold. The exact thickness of the metal layers 108 are not critical to the invention. However, the chromium layer should be at least thick enough to prevent the subsequent gold layer from penetrating through the chromium layer during deposition, and the gold layer should be thick enough to be electrically conductive and substantially nonporous to the quartz etchant. The metal layers 108 should be nonporous to quartz etchants because the photoresist layers 1 10 may not sufficiently inhibit penetration of the quartz etchants to areas of the quartz wafer 102 that should remain unetched. In a preferred embodiment, about 500 A of chromium is deposited followed by about 4000 A of gold.
A photoresist layer 110 is then spun on per the manufacturer's recommendations. In a preferred embodiment, a Shipley Microposit™ S1400-31 photoresist (available from Shipley of Newton, MA) is used for the photoresist layers 110. This is followed by baking in a convection type, air vented oven (such as one manufactured by Blue-M Electric of Watertown, Wl) at a temperature of about 90° C for about 15 minutes for each side of the wafer 102. Other similar photoresists may be used with acceptable results. Preferably, both sides of the wafer 102 are provided with photoresist layers 110. However, the photoresist layer 110 may be provided on only one side of the wafer 102.
Referring to FIGs. 5 and 8, the next process step 204 provides for removing a predetermined pattern 112 from portions of the quartz wafer 102. The quartz wafer 102 is exposed to ultraviolet light, through a glass photomask, at a light concentration of about 25 milliwatts per square centimeter for a period of about 6 seconds. In a preferred embodiment, the predetermined pattern 112 defining the channel 114 is of about 0.5 mils in width for a quartz wafer thickness 128 of about 3.9 mils. Then the quartz wafer 102 is placed in a developing bath of Shipley Microposit™ 351 developer (available from Shipley of Newton, MA) at about 25° C for about 1.5 minutes, followed by a deionized water rinse for at least 30 seconds. The quartz wafer is then placed in a gold etchant bath of Techni-strip™ AU (sodium cyanide type) (available from Lawrence Packaging Supply of Newark, NJ) at about 25° C for about 1 to about 5 minutes, depending on the thickness of the metal layer 108. The use of a preferred 4000 A thick gold layer requires about 4 minutes of gold etch time. This process step is followed by a deionized water rinse for at least 30 seconds. The quartz wafer is then placed in a commercial chrome etchant such as type TFD at about 25° C for about 2 minutes followed by a deionized water rinse for at least 30 seconds.
Referring to FIGs. 6 and 8, the next process step 206 provides for the etching of the quartz wafer 102. The quartz wafer 102 is placed into a supersaturated solution of about 60 percent hydrofluoric acid and about 40 percent ammonium fluoride at about 80° C for about 45 minutes, depending on the starting quartz wafer thickness 128. Other commercially available quartz etchants will work equally well. The quartz etchant will etch preferentially substantially along the atomic planes 122 of the quartz wafer 102. During etching, the atomic planes eventually define etched walls 124 of the channel 114. The confines of the narrow channel 114 cause a localized depletion of active quartz etchant in the channel 114. The depletion of the active quartz etchant causes the bottom of the narrow channel 1 16 to etch more slowly than the wider periphery 118 around the remainder of the quartz blank 100. Preferably, after quartz etching is completed, the bottom of the channel 116 will have penetrated to about 25% percent of the quartz wafer thickness 128 while the periphery 118 around the quartz blank 100 shall have etched completely through the wafer 102.
In a preferred embodiment, the quartz wafer is originally provided with the Z-axis of the quartz aligned substantially perpendicular 136 to the channel 114. This particular alignment provides for non-intersecting etched walls 124 of the channels 1 14 due to the particular alignment of the atomic planes 122. More particularly, the non- intersecting, partially etched channels 114, provide at least a partial mechanical weakening of the quartz wafer 102 near the breakout edge 106 of the quartz blank 100 so that a clean singulation may be obtained when a bending force 134 is applied to the quartz blank 100.
The advantage of non-intersecting channels 114 is to allow deeper etching without mechanically weakening the quartz wafer 102 as much as co-linear etch channels 114 would mechanically weakening the wafer 102. Also, non- intersecting channels 114 require less etch rate discrimination between the narrow channel 1 14 and the wider periphery 1 18 defining the remainder of the quartz blank 100.
This allows the use of a wider channel 114 geometry than might otherwise be needed. In addition, the deeper etching allows a substantially uniform bottom of the quartz channel 116 to be established for cleaner fracturing 132. However, it should be recognized that this invention can be used to etch intersecting, co-linear etch channels 114, but co-linear etch channels 114 may weaken the quartz wafer 102 before a substantially uniform channel bottom 1 16 is established.
After quartz etching, the next process step provides for the stripping 208 of the photoresist layer 1 10 from the quartz wafer 102, as shown in block 208 in FIG. 8. In one embodiment, the photoresist may be stripped in a Shipley Microposit™ 142A Remover (available from Shipley of
Newton, MA) at about 70 °C for about 15 minutes. However, acetone, alcohol or other suitable commercially available strippers may be used equally well.
Referring to FIGs. 7 and 8, the final major process step provides for the cleaving 210 of each quartz blank 100 from the quartz wafer 102 by clamping 130 the wafer 102 near the breakout edge 106 of each quartz blank 100 and applying a bending force 134 to the quartz blank 100. The bending force 134 causes a tensile stress concentration in the bottom of the channel 116. This stress propagates a fracture 132 substantially along the atomic planes 122 of the quartz wafer 102 thereby singulating the blank 100 from the wafer 102. The bending force 134 is applied in a manner so as to substantially prevent scratching of the surface of the blank 100. Preferably, the bending force 134 is applied at the free edge 104 of the quartz blank 100.
The advantage provided by the fracturing 132 the bottom of the channel 116 along atomic planes 122, is to minimize fragmentation of the quartz wafer 102, which minimizes particulate contamination on the surface of the quartz blank 100. Also, this fracturing 132 provides a cleaner and more efficiently and effectively singulated quartz blank 100, which has a smooth breakout edge 106 which can be mounted equally as well as the free edge 104 of the blank 100. Less inspection and quality control processing are required, and the clean singulation of the quartz blank 100 contributes to increasing yields and can subsequently lower costs since fewer quartz blanks 100 are broken during the singulation process. Also, the uniform dimension of the breakout edge 106 of the quartz blank 100 readily allows the use of automation without placement problems due to blank 100 irregularities. Although various embodiments of this invention have been shown and described, it should be understood that various modifications and substitutions, as well as rearrangements and combinations of the preceding embodiments, can be made by those skilled in the art, without departing from novel spirit and scope of this invention.
What is claimed is:

Claims

Claims
1. A method of etching photolithographically produced quartz crystal blanks for singulation, comprising:
providing a quartz wafer coated with at least one metal layer and a photoresist layer, respectively;
removing a predetermined pattern from the photoresist and the metal layer to expose a quartz channel having a bottom and connecting to a remaining quartz periphery defining a quartz blank;
etching the bottom of the channel along substantially parallel quartz atomic planes, whereby the bottom of the channel does not etch through the quartz wafer;
stripping the remaining photoresist layer from the metal layer; and
cleaving substantially along the bottom of the channel and substantially aligned with a quartz crystal atomic plane, to singulate the quartz blank from the quartz wafer.
2. The method of claim 1 , wherein the etching step includes:
exposing the bottom of the channel to etchant for a sufficiently long time to at least partially mechanically weaken the quartz wafer in proximity to the channel and exposing the bottom of the channel to etchant for a sufficiently short time so as not to etch through the quartz wafer; and
exposing the periphery defining the quartz blank for a sufficiently long time to etch through the quartz wafer.
3. The method of claim 1 , wherein the cleaving step includes singulating the quartz blank from the quartz wafer by applying a tensile force to an interior portion of the channel, whereby fragmentation of the quartz is minimized.
4. The method of claim 1 , wherein the removing and etching steps are provided on both sides of the quartz wafer to include substantially opposite channels.
5. The method of claim 4, wherein the removing step includes providing a predetermined pattern having the two substantially opposite channels in substantial alignment before the etching step.
6. The method of claim 1 , wherein the cleaving step includes rigidly clamping the quartz wafer and applying a bending force to the quartz blank to tensilely fracture the bottom of the channel substantially along an atomic plane to singulate the quartz blank from the quartz wafer.
7. A method of etching photolithographically produced quartz crystal blanks for singulation, comprising:
providing a quartz wafer coated with a metal layer and a photoresist layer, respectively, on both sides of the wafer;
removing a predetermined pattern from the photoresist and the metal layers on both sides of the quartz wafer to expose two opposing quartz channels each having a bottom and connecting to a remaining quartz periphery defining a quartz blank;
etching the peripheries defining the quartz blank and the bottoms of the two channels along substantially parallel quartz atomic planes, whereby etched walls of the channels are formed and defined by the substantially parallel atomic planes and the bottoms of the channels do not etch through the quartz wafer;
stripping the photoresist from the metal layers; and
cleaving substantially along the bottom of one channel and substantially aligning with a quartz crystal atomic plane to singulate the quartz blank from the quartz wafer, whereby fragmentation of the quartz is minimized.
8. The method of claim 7, wherein the etching step includes:
exposing the bottom of the channels to etchant for a sufficiently long time to at least partially mechanically weaken the quartz wafer in proximity to the channels and exposing the bottom of the channels to etchant for a sufficiently short time so as not to etch through the quartz wafer; and
exposing the peripheries on opposing sides of the quartz wafer and defining the quartz blank for a sufficiently long time to etch through the wafer.
9. The method of claim 7, wherein the removing step includes the predetermined pattern on opposing sides of the quartz wafer having the two channels in substantial alignment before the etching step and the two channels do not share an intersecting atomic plane.
10. The method of claim 7, wherein the predetermined patterns on opposing sides of the quartz wafer are chosen to define at least one channel width substantially narrower than the width of the peripheries defining the quartz blank, whereby the bottom of the narrower channel will etch slower than the wider peripheries defining the quartz blank due to the increased depletion rate of active etchant in the narrower channel.
PCT/US1996/004565 1995-05-30 1996-04-11 Method for etching photolithographically produced quartz crystal blanks for singulation WO1996039710A2 (en)

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EP96912542A EP0830732A4 (en) 1995-05-30 1996-04-11 Method for etching photolithographically produced quartz crystal blanks for singulation
JP9500458A JPH11509052A (en) 1995-05-30 1996-04-11 Method of individually separating quartz pieces made by photolithography by etching

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006013419A1 (en) * 2006-03-14 2007-09-27 Institut Für Mikroelektronik Stuttgart Integrated electronic circuit manufacturing method, involves subjecting porous silicon in wafer to thermal treatment, and closing pores at process of treatment, where material needed for closing is derived from low lying layer of silicon
US8466037B2 (en) 2006-03-14 2013-06-18 Institut Fuer Mikroelektronik Stuttgart Method for producing a thin chip comprising an integrated circuit

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5650075A (en) * 1995-05-30 1997-07-22 Motorola, Inc. Method for etching photolithographically produced quartz crystal blanks for singulation
US5942443A (en) 1996-06-28 1999-08-24 Caliper Technologies Corporation High throughput screening assay systems in microscale fluidic devices
US20060000722A1 (en) * 1996-06-28 2006-01-05 Caliper Life Sciences, Inc. High throughput screening assay systems in microscale fluidic devices
CN1173776C (en) 1996-06-28 2004-11-03 卡钳技术有限公司 High-throughput screening assay systems in microscale fluidic devices
US6604086B1 (en) 1998-07-20 2003-08-05 Usa Technologies, Inc. Electronic commerce terminal connected to a vending machine operable as a telephone
US6604087B1 (en) 1998-07-20 2003-08-05 Usa Technologies, Inc. Vending access to the internet, business application software, e-commerce, and e-business in a hotel room
US6609102B2 (en) 1998-07-20 2003-08-19 Usa Technologies, Inc. Universal interactive advertizing and payment system for public access electronic commerce and business related products and services
US6601038B1 (en) 1998-07-20 2003-07-29 Usa Technologies, Inc. Delivery of goods and services resultant from an electronic commerce transaction by way of a pack and ship type company
US6601037B1 (en) 1998-07-20 2003-07-29 Usa Technologies, Inc. System and method of processing credit card, e-commerce, and e-business transactions without the merchant incurring transaction processing fees or charges worldwide
US6615183B1 (en) 1998-07-20 2003-09-02 Usa Technologies, Inc. Method of warehousing user data entered at an electronic commerce terminal
US6807532B1 (en) 1998-07-20 2004-10-19 Usa Technologies, Inc. Method of soliciting a user to input survey data at an electronic commerce terminal
US6763336B1 (en) 1998-07-20 2004-07-13 Usa Technologies, Inc. Method of transacting an electronic mail, an electronic commerce, and an electronic business transaction by an electronic commerce terminal using a wirelessly networked plurality of portable digital devices
US6601039B1 (en) 1998-07-20 2003-07-29 Usa Technologies, Inc. Gas pump control system having access to the internet for the purposes of transacting e-mail, e-commerce, and e-business, and for conducting vending transactions
US6132685A (en) 1998-08-10 2000-10-17 Caliper Technologies Corporation High throughput microfluidic systems and methods
US6162565A (en) 1998-10-23 2000-12-19 International Business Machines Corporation Dilute acid rinse after develop for chrome etch
US6172443B1 (en) 1998-11-24 2001-01-09 Cts Corporation Quartz crystal resonator with improved temperature performance and method therefor
US6420202B1 (en) * 2000-05-16 2002-07-16 Agere Systems Guardian Corp. Method for shaping thin film resonators to shape acoustic modes therein
US6544810B1 (en) 2000-08-31 2003-04-08 Motorola, Inc. Capacitively sensed micromachined component and method of manufacturing
JP2002141576A (en) * 2000-11-02 2002-05-17 Fujitsu Ltd Jointing method piezo element and electrode, and piezo micro actuator using it
US20020116705A1 (en) * 2001-02-20 2002-08-22 Perlman Stephen G. System and method for processing conditional access data
US7805338B2 (en) * 2001-03-26 2010-09-28 Usa Technologies, Inc. Method of constructing a digital content play list for transmission and presentation on a public access electronic terminal
US7195715B2 (en) * 2003-05-27 2007-03-27 Citizen Watch Co., Ltd. Method for manufacturing quartz oscillator
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US20050064679A1 (en) * 2003-09-19 2005-03-24 Farnworth Warren M. Consolidatable composite materials, articles of manufacture formed therefrom, and fabrication methods
US7713841B2 (en) * 2003-09-19 2010-05-11 Micron Technology, Inc. Methods for thinning semiconductor substrates that employ support structures formed on the substrates
US20050064683A1 (en) * 2003-09-19 2005-03-24 Farnworth Warren M. Method and apparatus for supporting wafers for die singulation and subsequent handling
US7244665B2 (en) * 2004-04-29 2007-07-17 Micron Technology, Inc. Wafer edge ring structures and methods of formation
US7547978B2 (en) 2004-06-14 2009-06-16 Micron Technology, Inc. Underfill and encapsulation of semiconductor assemblies with materials having differing properties
US7235431B2 (en) 2004-09-02 2007-06-26 Micron Technology, Inc. Methods for packaging a plurality of semiconductor dice using a flowable dielectric material
FR2880987B1 (en) * 2005-01-18 2007-04-06 Sagem PROCESS FOR ETCHING A CRYSTALLINE MATERIAL
JP2006311230A (en) * 2005-04-28 2006-11-09 Kyocera Kinseki Corp Manufacturing method of lame mode crystal vibrator
FR2880985B1 (en) * 2005-05-26 2007-04-13 Sagem METHOD FOR THE ETCHING OF A CRYSTALLINE WAFER
JP4569450B2 (en) * 2005-11-22 2010-10-27 エプソントヨコム株式会社 Assembly of AT-cut crystal piece, AT-cut crystal device, and manufacturing method of AT-cut crystal device
US7923298B2 (en) * 2007-09-07 2011-04-12 Micron Technology, Inc. Imager die package and methods of packaging an imager die on a temporary carrier
GB2483402B (en) 2009-06-04 2014-04-09 Lockheed Corp Multiple-sample microfluidic chip for DNA analysis
TWI396311B (en) * 2010-08-20 2013-05-11 Txc Corp Manufacturing Method of Wafer - level Packaging Structure for Through - hole Oscillator
US8430482B2 (en) 2010-09-29 2013-04-30 Lexmark International, Inc. Singulating ejection chips for micro-fluid applications
US8961764B2 (en) 2010-10-15 2015-02-24 Lockheed Martin Corporation Micro fluidic optic design
US20140021400A1 (en) 2010-12-15 2014-01-23 Sun Chemical Corporation Printable etchant compositions for etching silver nanoware-based transparent, conductive film
US9322054B2 (en) 2012-02-22 2016-04-26 Lockheed Martin Corporation Microfluidic cartridge
CN105390935B (en) * 2015-12-03 2018-03-06 长江大学 A kind of preparation method of the chip of laser with mark function
JP7077539B2 (en) * 2017-06-23 2022-05-31 セイコーエプソン株式会社 Vibrating elements, oscillators, oscillators, electronic devices and moving objects
KR20220115676A (en) * 2021-02-09 2022-08-18 삼성디스플레이 주식회사 Jig for fabricating window and fabricating method of window using the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4035674A (en) * 1974-11-09 1977-07-12 Kabushiki Kaisha Suwa Seikosha Quartz crystal vibrator
JPS5788100A (en) * 1980-11-21 1982-06-01 Citizen Watch Co Ltd Etching method for quartz substrate
JPS57181219A (en) * 1981-04-30 1982-11-08 Citizen Watch Co Ltd Manufacture of quartz oscillator
US4632898A (en) * 1985-04-15 1986-12-30 Eastman Kodak Company Process for fabricating glass tooling
US4732647A (en) * 1984-10-24 1988-03-22 Aine Harry E Batch method of making miniature capacitive force transducers assembled in wafer form
US5447601A (en) * 1993-04-07 1995-09-05 British Aerospace Plc Method of manufacturing a motion sensor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5829210A (en) * 1981-08-14 1983-02-21 Citizen Watch Co Ltd Manufacture of tuning fork type quartz oscillating bar
US4542397A (en) * 1984-04-12 1985-09-17 Xerox Corporation Self aligning small scale integrated circuit semiconductor chips to form large area arrays
US4604161A (en) * 1985-05-02 1986-08-05 Xerox Corporation Method of fabricating image sensor arrays
US4897360A (en) * 1987-12-09 1990-01-30 Wisconsin Alumni Research Foundation Polysilicon thin film process
DE69129957T2 (en) * 1990-04-27 1998-12-24 Seiko Epson Corp Crystal oscillator element cut in the AT direction and its production method
JP3423014B2 (en) * 1992-10-02 2003-07-07 アルプス電気株式会社 Method and apparatus for dividing ceramic substrate
US5585069A (en) * 1994-11-10 1996-12-17 David Sarnoff Research Center, Inc. Partitioned microelectronic and fluidic device array for clinical diagnostics and chemical synthesis
US5650075A (en) * 1995-05-30 1997-07-22 Motorola, Inc. Method for etching photolithographically produced quartz crystal blanks for singulation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4035674A (en) * 1974-11-09 1977-07-12 Kabushiki Kaisha Suwa Seikosha Quartz crystal vibrator
JPS5788100A (en) * 1980-11-21 1982-06-01 Citizen Watch Co Ltd Etching method for quartz substrate
JPS57181219A (en) * 1981-04-30 1982-11-08 Citizen Watch Co Ltd Manufacture of quartz oscillator
US4732647A (en) * 1984-10-24 1988-03-22 Aine Harry E Batch method of making miniature capacitive force transducers assembled in wafer form
US4632898A (en) * 1985-04-15 1986-12-30 Eastman Kodak Company Process for fabricating glass tooling
US5447601A (en) * 1993-04-07 1995-09-05 British Aerospace Plc Method of manufacturing a motion sensor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0830732A2 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006013419A1 (en) * 2006-03-14 2007-09-27 Institut Für Mikroelektronik Stuttgart Integrated electronic circuit manufacturing method, involves subjecting porous silicon in wafer to thermal treatment, and closing pores at process of treatment, where material needed for closing is derived from low lying layer of silicon
DE102006013419B4 (en) * 2006-03-14 2008-05-29 Institut Für Mikroelektronik Stuttgart Method for producing an integrated circuit
US8466037B2 (en) 2006-03-14 2013-06-18 Institut Fuer Mikroelektronik Stuttgart Method for producing a thin chip comprising an integrated circuit

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US5650075A (en) 1997-07-22
CN1096626C (en) 2002-12-18
US5833869A (en) 1998-11-10
JPH11509052A (en) 1999-08-03
WO1996039710A3 (en) 1997-04-17
CN1185870A (en) 1998-06-24
EP0830732A4 (en) 2001-01-31
EP0830732A2 (en) 1998-03-25

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