WO1996034469A1 - Commutateur de reseau atm a amenagement de trafic - Google Patents

Commutateur de reseau atm a amenagement de trafic Download PDF

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Publication number
WO1996034469A1
WO1996034469A1 PCT/US1996/005606 US9605606W WO9634469A1 WO 1996034469 A1 WO1996034469 A1 WO 1996034469A1 US 9605606 W US9605606 W US 9605606W WO 9634469 A1 WO9634469 A1 WO 9634469A1
Authority
WO
WIPO (PCT)
Prior art keywords
cell
atm
time
onward transmission
transmission time
Prior art date
Application number
PCT/US1996/005606
Other languages
English (en)
Inventor
Trevor Jones
Original Assignee
General Datacomm, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB9508225.1A external-priority patent/GB9508225D0/en
Application filed by General Datacomm, Inc. filed Critical General Datacomm, Inc.
Priority to AU55657/96A priority Critical patent/AU5565796A/en
Priority to EP96913033A priority patent/EP0823158A4/fr
Priority to US08/913,815 priority patent/US6044060A/en
Publication of WO1996034469A1 publication Critical patent/WO1996034469A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection or protection within a single switching element
    • H04L49/501—Overload detection
    • H04L49/503—Policing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports

Definitions

  • This invention relates to an asynchronous transfer mode (ATM) network switch. More particularly, this invention relates to a switch having means for controlling the flow of ATM cells constituting an individual virtual connection (VC) .
  • ATM asynchronous transfer mode
  • cells of data conventionally comprising fifty-three bytes (forty-eight bytes carrying data and the remaining five bytes defining the cell header, the address and related information) pass through the network on a virtual connection at an agreed upon rate related to the available bandwidth and the level or service paid for.
  • the agreed upon rate will relate not only to the steady average flow of data, but will also limit the peak flow rates.
  • the network will include, for example at the boundary between different networks, means for policing the flow.
  • the flow policing means typically includes a "leaky bucket" device which assesses the peak and average flow rates of cells on a VC and if required either downgrades the cells' priority or discards cells.
  • a "leaky bucket” device which assesses the peak and average flow rates of cells on a VC and if required either downgrades the cells' priority or discards cells.
  • traffic shaping Since policing can result in the discarding of cells which should not be discarded, it is desirable to effect "traffic shaping" to space out the cells on a VC sufficiently so as to ensure that they meet the agreed upon rates, and in particular the peak rates.
  • traffic shaping is that it is desirable to delay the transmission of cells by variable amounts in an attempt to avoid cell loss. In practice, however, variable cell delay has been difficult to implement.
  • an ATM network switch is provided with a traffic shaping means on the input or output side thereof.
  • the traffic shaping means broadly comprises means for determining for each cell received at the traffic shaping means an onward transmission time dependent upon the time interval between the arrival of the cell and the time of arrival of the preceding cell on the same VC, buffer means for storing each new cell at an address corresponding to the onward transmission time, and means for outputting cells from the buffer means at a time corresponding to the address thereof.
  • the switch comprises a cross-point switch (switch fabric) having a plurality of input ports (cell receiving means for receiving ATM cells from a data link) and a plurality of output ports (cell transmitting means for transmitting ATM cells outwardly on the data link) , and one or more controllers (which are often called “slot controllers' or “link controllers”) for switching data cells from any input port to any output port.
  • switch fabric cross-point switch
  • input ports cell receiving means for receiving ATM cells from a data link
  • output ports cell transmitting means for transmitting ATM cells outwardly on the data link
  • controllers which are often called "slot controllers' or "link controllers"
  • the cell transmitting means of each controller includes the traffic shaping means arranged to set, for each cell presented to the transmitting means, a current onward transmission time when onward transmission at the input rate meets a predetermined flow rate criterion, and a delayed onward transmission time when onward transmission at the current time would cause the traffic on a VC to exceed a predetermined flow rate criterion.
  • the traffic shaping means comprises at least one leaky bucket processor for determining an onward transmission time, buffer means for storing each new cell at an address corresponding to the onward transmission time, and means for outputting cells from the buffer means at a time corresponding to the address thereof.
  • each leaky bucket processor of the traffic shaping means comprises: a timer means for timing the arrival of each ATM cell presented to the transmitting means; memory means for storing a predetermined regular bucket increment, a current bucket level value and a bucket maximum value, being the maximum capacity of the bucket; calculating means for calculating the time difference between the arrival time of the cell and a stored onward transmission time for the preceding cell on the same VC, and for calculating a new bucket level from the time difference, the current bucket level, and the bucket increment; subtraction means for subtracting the maximum level from the new level to give an overflow value and, if the overflow value is negative, for setting the value of the overflow to zero; and means for adding the overflow value to the current time to give the onward transmission time for the cell and for storing the onward transmission time in the memory or buffer means.
  • the traffic shaping means comprises a leaky bucket processor which carries on two leaky bucket calculations, and means for comparing the overflow values calculated in the two leaky bucket calculations and for passing only the greater of the two values to the adding means.
  • a first of the two leaky bucket calculations monitors peak cell flow rates, while the second leaky buckt calculation monitors average cell flow rates.
  • the buffer means comprises a FIFO for each VC for storing cells on that VC, and memory means for storing at an address corresponding to the onward transmission time for each cell the address of the cell.
  • the buffer means is suitably configured dynamically in Random Access Memory (RAM) , so that the VC FIFOs are set up as new VCs are set up.
  • the output means is preferably arranged to output cells from the FIFOs in accordance with the data stored in the memory means.
  • FIG. 1 is a representation of an ATM switch in accordance with the invention.
  • FIG. 2 is a more detailed representation of one of the slot controllers of the switch shown in Figure 1;
  • Figure 3 is a representation of the buffer memory arrangement forming part of the traffic shaping means within the slot controller shown in Figure 2;
  • Figure 4 is a representation of an alternative buffer arrangement which can be used with the traffic shaping means within the slot controller shown in Figure 2; and Figure 5 is a flow diagram of the leaky bucket algorithm used in the traffic shaping means shown in Figure 3.
  • an ATM network switch comprising a plurality of slot controllers lla-llf and two separate switch fabrics 14a and 14b.
  • slot controllers lla-llf
  • switch fabrics 14a and 14b are of a dynamic crosspoint type with input and output connections 15 and 16 respectively to each of the slot controllers 11. This type of arrangement is described in more detail in co-owned application #GB9507454.8 which is hereby incorporated by reference herein in its entirety.
  • the structure of the slot controllers is, for example, of the general type described and claimed in previously incorporated patent application #GB9505358.3, and ATM cells arriving on a input link 12 may be processed in the general manner described in that application.
  • FIG. 2 shows the structure of a slot controller 11 in more detail.
  • the slot controller 11 comprises an input cell processor 21, whose structure will not be described further since it has no bearing on the present invention.
  • the input cell processor 21 is connected to the input link 12 and to the input connections 15 to the switch fabric. Cells output from the switch fabric on connections 16 are processed for the transmission on the output link 13 by an output cell processor 22 which includes a leaky bucket processing means 23 and a buffer memory 24.
  • an output cell processor 22 which includes a leaky bucket processing means 23 and a buffer memory 24. It is noted that in Figure 2, for the sake of clarity, only those components which relate to traffic shaping functions are illustrated. It will be appreciated, however, that the output cell processor 22 handles additional functions such as the writing to the cell headers of the new VPI/VCI information, and output to the output link 13.
  • the output cell processor 22 comprises a leaky bucket processing means 23 and a buffer memory 24.
  • the leaky bucket processing means 23 receives cells arriving from the switch fabric and determines for each cell, as hereinafter described with reference to Figure 4, whether the peak and sustained cell flow rates appropriate to the cell's VC have been exceeded. If the cell conforms with the peak and sustained flow rates specified, the cell is entered into a buffer memory 24 at an address corresponding to the current time. If one or the other of the peak and sustained rates has been exceeded, so that the leaky bucket overflows, the amount of the overflow, or of the greater of the overflows if both buckets overflow, is added to the current time as the address for the cell in the buffer memory 24.
  • the onward transmission of the cell is delayed by the amount of the overflow, to ensure that the cell will conform with the specified rates.
  • the cells are output from the buffer memory 24 in order of stored time slot; i.e., the cells are not transmitted onwards before the relevant time slot becomes due.
  • Figure 3 shows a first arrangement of the buffer memory 24 forming part of the traffic shaping means in the slot controller illustrated in Figure 2.
  • the buffer memory 24 comprises a multi-dimensional FIFO 31 dynamically configured in Random Access Memory (RAM) .
  • RAM Random Access Memory
  • the horizontal direction in the buffer represents different time slots arranged sequentially, the buffer being such that the current time pointer moves along the buffer until it reaches one end, and is then reset to the other end so that the buffer is effectively "circular".
  • time slot may be stored.
  • the time slot may be empty if no cells are assigned the same onward transmission time.
  • the time slot is treated as a FIFO memory, with the cells being written to the slot sequentially and read out of the time slot in the same order in which they are written to the slot.
  • An output logic means 32 is arranged to step a current time pointer along the buffer according to the actual current time, but to control output of cells according to an output time pointer which lags behind the current time by up to approximately eight time slots (the algorithm attempts to maintain a maximum of eight time slots lag, but if many cells are present a grater lag can sometimes develop) .
  • the time slots are each of 640ns duration, being thirty-two clock periods of the system clock.
  • the output pointer waits until the current clock has advanced by eight slots relative to the output time, and then during the next time interval looks at each of the eight time slots to output the cells found.
  • the time slot b has three cells awaiting transmission, and these are transmitted in turn.
  • the next slot, c might for example have no cells waiting, so the output time pointer jumps to the next slot d and causes the two cells waiting there to be transmitted in turn. If all the waiting cells in the eight slots have not been transmitted in the next time interval of 640ns, the output time pointer continues to advance at eight-times the clock speed until it "catches up" and cells are being transmitted within the appropriate time interval.
  • the set of eight slots will allow the output to keep pace with the current time, but it will be appreciated that different numbers of slots, with appropriate speeds, may be selected if desired or if necessary.
  • Figure 4 illustrates an alternative arrangement for the buffer part of the traffic shaping means, in which the cells are stored in a series of FIFOs 41 defined dynamically in RAM, each VC having its own FIFO, and a buffer memory 42 stores at appropriate time slot addresses the address of the relevant FIFO 41.
  • Leaky bucket processing logic 43 is used to process incoming cells in the manner hereinbefore described with reference to Figure 2, and as further described hereinafter with reference to Figure 5.
  • the buffer memory 42 is controlled by logic 44 to store in sequential time slots the addresses of the cells in the FIFOs 41 instead of the actual cells, and to output the addresses in sequence to cause the cells to be output from the FIFOs 41. More than one address can be stored at any time slot, and the addresses are then output in sequence on a "first in first out" basis, in the same way as the actual cells are output in the embodiment described with reference to Figure 3.
  • Figure 5 illustrates the algorithm used by the leaky bucket processor.
  • the algorithm shown uses two buckets, one for peak flow and one for sustained flow, and each cell is process by both buckets, the result of the bucket having the greatest overflow being used to determine the time slot for the cell address (for the embodiment shown in Figure 4) or (in the case of the system illustrated in Figure 3) the time slot in the FIFO for the cell itself.
  • the new cell is received at 50 to start the process.
  • the algorithm calculates the time interval between the stored onward transmission time for the last cell on the same VC and the current time at which the new cell arrives.
  • the new level of each bucket is determined at 52 by subtracting the calculated time interval from the existing bucket level, and the new level is used to calculate at 53 an overflow value by subtracting the bucket maximum from the new level. If it is determined at 54 that the overflow is negative, at 55 the overflow is set to zero. Regardless, the overflow values obtained from the two buckets (peak and average) are compared and the greatest overflow is selected at 56. At 57, the onward transmission time for the cell is set to the current time plus the amount of the overflow. Each bucket level is then incremented at 58 by the stored predetermined increment, which is equivalent to one cell, and the new bucket levels are written at 59 to the memory.
  • the stored time is then set to the onward transmission time at 60 for use in the calculation for the next cell on the particular VC, and at 61 the system is ready to read the next cell on the VC.
  • the resulting transmission time from the performance of the algorithm is used to set the time slot in the buffer memory at which the cell (in the case of the embodiment is described with reference to Figure 3) , or the cell FIFO address (in the case of the embodiment described with reference to Figure 4) is stored.
  • the cell, or the address then remains in the appropriate time slot until the output time pointer determines that its contents should be read and the cell output, either directly from the buffer, or, in the case of the Figure 4 embodiment, from the separate FIFO 41.
  • the result of this operation is that the cells are transmitted onward from the slot controller in a more controlled manner, with the effects of bunching of the cells having been removed.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Commutateur de réseau en mode de transfert asynchrone (ATM) comprenant une structure de commutation (14) et une pluralité de régisseurs d'intervalles (11) couplés à la structure de commutation. Chaque régisseur d'intervalle comporte au moins un ensemble de circuits (21) de réception de cellules provenant des liaisons externe (12, 13), recevant des cellules ATM provenant de ces liaisons, et un ensemble de circuits de transmission de cellules (22) transmettant les cellules ATM vers l'extérieur sur les liaisons. L'ensemble de circuits de transmission de cellules de chaque régisseur d'intervalles comprend des circuits d'aménagement de trafic (23) configurés de façon à fixer, pour chaque cellule présentée à l'ensemble de circuits de transmission, un moment de retransmission immédiate lorsque la retransmission au débit d'entrée correspond à un critère de débit prédéterminé, et un moment de retransmission différée lorsque la retransmission immédiate amènerait le trafic sur une connexion virtuelle à dépasser le critère de débit prédéterminé. Le circuit d'aménagement du trafic comporte un tampon (24) stockant chaque nouvelle cellule à une adresse correspondant au temps de retransmission, et une logique de sortie (32 ou 44) permettant de sortir des cellules du tampon à un moment correspondant à l'adresse de celles-ci.
PCT/US1996/005606 1995-04-22 1996-04-22 Commutateur de reseau atm a amenagement de trafic WO1996034469A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU55657/96A AU5565796A (en) 1995-04-22 1996-04-22 A traffic shaping atm network switch
EP96913033A EP0823158A4 (fr) 1995-04-22 1996-04-22 Commutateur de reseau atm a amenagement de trafic
US08/913,815 US6044060A (en) 1995-04-22 1996-04-22 Traffic shaping ATM network switch

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GBGB9508225.1A GB9508225D0 (en) 1995-04-22 1995-04-22 ATM network swith
GB9508225.1 1995-04-22
GBGB9509483.5A GB9509483D0 (en) 1995-04-22 1995-05-10 Atm network switch
GB9509483.5 1995-05-10

Publications (1)

Publication Number Publication Date
WO1996034469A1 true WO1996034469A1 (fr) 1996-10-31

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PCT/US1996/005606 WO1996034469A1 (fr) 1995-04-22 1996-04-22 Commutateur de reseau atm a amenagement de trafic

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AU (1) AU5565796A (fr)
CA (1) CA2215722A1 (fr)
WO (1) WO1996034469A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2316270A (en) * 1996-08-21 1998-02-18 Nec Corp A method for controlling the flow of cells in an ATM network
EP1293068A1 (fr) * 2000-04-27 2003-03-19 Commonwealth Scientific And Industrial Research Organisation Regulateur du trafic dans des reseaux de telecommunications
US7742506B2 (en) * 2005-05-27 2010-06-22 Agere Systems Inc. Controlling timeslot delay in a digital communication system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280475A (en) * 1990-08-17 1994-01-18 Hitachi, Ltd. Traffic shaping method and circuit
US5381407A (en) * 1992-06-04 1995-01-10 Bell Communications Research, Inc. Method and system for controlling user traffic to a fast packet switching system
US5448567A (en) * 1993-07-27 1995-09-05 Nec Research Institute, Inc. Control architecture for ATM networks

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280475A (en) * 1990-08-17 1994-01-18 Hitachi, Ltd. Traffic shaping method and circuit
US5381407A (en) * 1992-06-04 1995-01-10 Bell Communications Research, Inc. Method and system for controlling user traffic to a fast packet switching system
US5448567A (en) * 1993-07-27 1995-09-05 Nec Research Institute, Inc. Control architecture for ATM networks

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2316270A (en) * 1996-08-21 1998-02-18 Nec Corp A method for controlling the flow of cells in an ATM network
GB2316270B (en) * 1996-08-21 2000-08-30 Nec Corp ATM Network time management method
US6438103B2 (en) 1996-08-21 2002-08-20 Nec Corporation ATM network time management method
EP1293068A1 (fr) * 2000-04-27 2003-03-19 Commonwealth Scientific And Industrial Research Organisation Regulateur du trafic dans des reseaux de telecommunications
EP1293068A4 (fr) * 2000-04-27 2007-03-07 Commw Scient Ind Res Org Regulateur du trafic dans des reseaux de telecommunications
US7742506B2 (en) * 2005-05-27 2010-06-22 Agere Systems Inc. Controlling timeslot delay in a digital communication system

Also Published As

Publication number Publication date
EP0823158A1 (fr) 1998-02-11
CA2215722A1 (fr) 1996-10-31
AU5565796A (en) 1996-11-18
EP0823158A4 (fr) 2001-04-25

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