WO1996034406A1

WO1996034406A1 - Manufacture of semiconductor integrated circuit device

Info

Publication number: WO1996034406A1
Application number: PCT/JP1995/000841
Authority: WO
Inventors: Susumu Komoriya; Shunji Nagatsuka; Shinji Kuniyoshi; Hisashi Maejima; Nobuyuki Iriki; Takeshi Kato; Masayuki Hiranuma; Takashi Hiroi
Original assignee: Hitachi, Ltd.
Priority date: 1995-04-27
Filing date: 1995-04-27
Publication date: 1996-10-31

Abstract

A semiconductor wafer (21) placed on a supporting table which is movable in the vertical direction is irradiated with light (74a) transmitted through a mask pattern (74), a half mirror (73) and projecting lens, and reflected light (74b) from the wafer passes through the lens (72) and the mirror (73) to a detector (71) which is movable in the direction of the optical axis. The detector measures the intensity distribution in a three-dimensional space near the surface of the wafer (21) to determine the radius of curvature of recesses and projections, and the area and reflectivity of the reflective region. Then, a region, where recesses and projections of smaller curvature and larger area are present, is considered to have the minimum allowance of exposure and focusing. Exposure control parameters are determined in this region and are fed back to a photolithographic process.

Description

Description Method of manufacturing semiconductor integrated circuit device

The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to measures against a product defect caused by a surface shape of a semiconductor wafer in a manufacturing process of a semiconductor integrated circuit device.

Background art

Semiconductor integrated circuit devices are manufactured by forming circuit patterns on semiconductor wafers. The basic manufacturing process includes a film forming process such as thermal oxidation, CVD, and sputtering, a fine process such as resist coating, exposure, development, and etching, and an impurity doping process such as ion implantation.

For high integration of semiconductor harvesting circuit devices, microfabrication technology is particularly important. Among them, particularly high accuracy of the photosensitive process is an important technical problem.

In recent years, it is common to use a reduction projection exposure apparatus S shown in FIG. When a circuit pattern is formed on a semiconductor wafer using the reduction projection exposure apparatus shown in FIG. 17, it is very important to optimally set the exposure amount and the focal position. This is because the allowable 量 δ range of the exposure dose and the focal position at which a practical circuit pattern can be accurately printed on a semiconductor wafer is extremely small. For this reason, before printing a circuit pattern on a semiconductor wafer, it is necessary to measure the exposure dose and the allowable range of the focal position, and to determine the optimum value (control value).

In this condition setting work, the circuit pattern is printed on a semiconductor wafer by changing the exposure amount in the column direction and the focal position in the row direction as shown in FIG.

After the development processing, the dimensions and appearance of the circuit pattern on the wafer are measured using a scanning electron microscope (S Ε Μ). Fig. 19 shows the relationship between the dimensions, exposure, and focus position. Figure 20 shows the relationship between the appearance, the exposure, and the focal position S. The characteristics shown in FIGS. 19 and 20 vary depending on the shape of the pattern, the reflectivity on the semiconductor wafer, the uneven shape, and the like, and therefore differ depending on the location. For this reason, select a place where the allowable range of the exposure amount and the focus position is the smallest. It is necessary to select and set conditions.

However, the amount of work and the time required to observe and measure all circuit patterns in SEM are enormous, and in practice, the conditions are set by measuring several places. For this reason, a place where the allowable range of the exposure amount and the focal position is the smallest is often overlooked.

In mass production after completing the condition setting, the measurement is further simplified. For this reason, when the reflectance, the uneven shape, and the like on the semiconductor layer fluctuate, short-circuits, breaks (halation), and other defects occur in places where the allowable range is small. In the aluminum wiring process with high reflectivity on the semiconductor wafer and the polysilicon gate process, defects are particularly likely to occur. Generally, it is desirable that the unevenness on the semiconductor X is nearly flat. For this reason, a glass film is formed on a semiconductor wafer and flattened. For example, a method in which boron glass is formed on a semiconductor substrate by CVD and heat treatment is performed to reflow the glass film, or a method in which liquid glass is spin-coated and then heat treatment is performed to sinter the glass film. is there. However, depending on the glass film forming conditions such as impurity concentration, forming temperature, viscosity of the film forming material, and number of rotations of the film forming, the unevenness of the unevenness tends to change, and a technique for managing the change in the uneven shape is important.

In general, it is desirable that the reflectance on the semiconductor substrate be low. Aluminum, polysilicon, titanium, molybdenum, etc. for wiring are formed by sputtering or CVD, but the reflectance tends to change depending on the film formation conditions, and technology to manage this change in reflectance is important. .

As a technique for detecting a halation region or the like on a metal surface or the like, a technique disclosed in Japanese Unexamined Patent Application Publication No. Hei 6-118203 is known. This technique discloses a method of extracting a high-luminance region of a target object by an arithmetic process using virtual image data corresponding to image data of the region.

When the manufacturing technology of the conventional semiconductor integrated circuit device S as described above is integrated, in order to stably form a circuit pattern on the semiconductor

(1) It is necessary to find a place where the allowable range of the exposure amount and the focal position is the smallest in a short time.

(2) It is necessary to reduce fluctuations in the reflectivity, irregularities, and the like on the semiconductor wafer.

(3) It is necessary to prevent defects such as haration shots. And other technical issues.

If the above-mentioned problem (1) is to be solved by the technique disclosed in Japanese Patent Application Laid-Open No. 6-118023, the amount of calculation is enormous and a long time is required, and it is difficult to apply the method to a mass production process. It is.

Regarding the above (2), a technique for quickly and accurately evaluating the uneven shape is indispensable. However, when the technique of Japanese Patent Application Laid-Open No. 6-118023 is to be measured, The amount of calculation is enormous and requires a long time, making it difficult to apply to mass production processes. Further, with respect to the above-mentioned problems (2) and (3), for example, the influence of the reflection of exposure light from under the semiconductor wafer by using a multilayer resist technology in which an anti-reflection film is formed on a normal photo resist film. This can be solved by reducing the cost, but the multiple eyebrow registry makes the process unnecessarily complicated, so applying it uniformly to the manufacturing process will result in another problem that cost and throughput will decrease. Is generated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a branching technique capable of finding a place on a semiconductor wafer where an allowable range of an exposure amount and a focus position is the smallest in a short time and feeding back to control of a manufacturing process. .

Another object of the present invention is to provide a technique capable of accurately measuring fluctuations in the reflectance and unevenness of a semiconductor wafer and providing feedback to a manufacturing process.

Still another object of the present invention is to provide a technique capable of preventing defects such as halation shots and the like and improving the yield in the manufacturing process of a semiconductor integrated circuit device.

Disclosure of the invention

The present invention provides a method for irradiating inspection light onto a semiconductor X having irregularities and measuring the light intensity distribution at a spatial position distant from the pattern surface to determine the radius of curvature of the irregularities on the semiconductor wafer. Calculating the area to identify the area where the allowable range of the exposure amount and the focus position is small, and determining the management value of the exposure condition based on the area where the allowable range is small; A method of manufacturing a semiconductor integrated circuit device including the steps of:

The present invention also provides a planarizing film for planarizing a semiconductor wafer having an uneven shape. In a method for manufacturing a semiconductor integrated circuit device including a step of forming a semiconductor device, a method for irradiating inspection light onto a semiconductor substrate having an uneven shape, measuring a light intensity distribution at a spatial position distant from a pattern surface, and Determining the curvature radius and area of the irregularities on the wafer and the reflectance, and determining the correlation with the conditions for forming the flattening film; and measuring the surface of the semiconductor wafer on which the flattening film was formed during the manufacturing process. Correcting the formation condition of the flattening film based on the correspondence relationship.

The present invention also provides a method of irradiating exposure light onto a resist-coated semiconductor wafer having irregularities, measuring a light intensity distribution at a spatial position distant from the pattern surface, and measuring the curvature of the irregularities on the semiconductor wafer. A semiconductor integrated circuit including: a step of determining a radius, an area, and a surface reflectivity of exposure light, determining a correlation with an exposure S that causes an exposure defect, and a step of correcting an exposure amount during an exposure process based on the correlation. This is a method for manufacturing a circuit device.

The present invention also provides a method of irradiating inspection light on a semiconductor wafer having an uneven shape, measuring a light intensity distribution at a spatial position distant from the pattern surface, and measuring a radius of curvature and a surface of the uneven shape on the semiconductor wafer X. The step of identifying the area where the exposure amount and the focal position S are within a small allowable range by finding the ears, and determining the control value of the exposure condition based on the area where the allowable range is small, and a semiconductor wafer having unevenness Irradiate the inspection light on the top, measure the light intensity distribution at the spatial position S away from the pattern surface, and determine the half-curvature and surface roughness and reflectance of the uneven shape on the semiconductor. Determining a correlation with a flattening film formation condition for flattening on the upper surface; forming a flattening film for flattening using an optimum flattening film formation condition;ゥ X c reflectance and uneven curvature half Measuring the reflectivity of the semiconductor ゥ X and the half-S curvature and the surface roughness of the uneven shape outside the allowable range, based on the correlation. Correcting the formation conditions; performing exposure and development processing on the preceding semiconductor wafer in the lot including the semiconductor wafer using the control values; and controlling the photo resist formed by the exposure and development processing. Inspecting the photoresist pattern; if the inspection result of the photoresist pattern is normal, performing an etching using the photoresist pattern as a mask; and inspecting the etching pattern obtained by the etching. , If at least one of the inspection of the photoresist pattern and the inspection of the etching pattern is determined to be abnormal, a step of changing to a process using a multilayer photoresist is provided.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a conceptual diagram showing an example of the principle of a method for measuring the uneven shape of a semiconductor integrated circuit used in the method of manufacturing a semiconductor integrated circuit device according to the present invention. FIG. FIG. 3 is a conceptual diagram showing an example of the principle of a method of measuring the unevenness of a semiconductor wafer used in the method. FIG. 3 is a method of measuring the unevenness of a semiconductor wafer used in the method of manufacturing a semiconductor integrated circuit S of the present invention. FIG. 4 is a conceptual diagram showing an example of the principle of the present invention. FIG. 4 is a conceptual diagram showing an example of the principle of a method for measuring the uneven shape of a semiconductor wafer used in the method of manufacturing a semiconductor integrated circuit device of the present invention. FIG. 6 is a diagram showing an example of the operation of the method for measuring the uneven shape of a semiconductor wafer used in the method for manufacturing a semiconductor integrated circuit device. FIG. 6 is a diagram showing the unevenness of the semiconductor wafer used in the method for manufacturing a semiconductor integrated circuit device according to the present invention. Of measurement method FIG. 7 is a diagram showing an example of the configuration of a device S for measuring the reflectance and the unevenness on a semiconductor wafer used in a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 8 is a conceptual diagram showing an example of an ultra-low magnification objective lens in the optical system of FIG. 7, FIG. 9 is a plan view showing an example of an illumination σ switching mechanism in the optical system of FIG. 10 is a perspective view showing an example of an autofocus stripe pattern in the optical system of FIG. 7, FIG. 11 is a perspective view showing an example of a continuously variable illuminance mechanism in the optical system of FIG. 7, and FIG. FIG. 13 is a plan view showing an example of a wavelength switching mechanism in the optical system of FIG. 7. FIG. 13 is a flowchart showing an example of the operation of the method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. Is one of the relationships between the film formation conditions of the glass film and the reflectivity and unevenness of the semiconductor wafer. FIG. 15 is a diagram showing an example of the relationship between the exposure dose and the reflectance and the unevenness of the semiconductor wafer. FIG. 16 is a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 17 is a conceptual diagram showing another example of the configuration of an apparatus for measuring the reflectance and the uneven shape on the semiconductor substrate X used in the manufacturing method of the semiconductor device. FIG. 17 is used in the manufacturing process of the semiconductor integrated circuit device. FIG. 18 is a conceptual diagram showing an example of a reduced projection exposure apparatus S. FIG. 18 is a plan view showing an example of a dummy wafer used for setting exposure conditions in a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. 9 for reduced projection exposure Diagram showing an example of the relationship between the exposure dose and the focal position »and the dimensions of the lithographic pattern. Figure 20 is a concept showing an example of the relationship between the exposure dose and the focal position and the appearance of the transfer pattern in reduced projection exposure. FIGS. 21A and 21B are a cross-sectional view and a plan view showing an example of the structure of a semiconductor wafer to which a method of manufacturing a semiconductor integrated circuit device S according to an embodiment of the present invention is applied. .

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in more detail with reference to the accompanying drawings. FIG. 1 is a conceptual diagram showing an example of the principle of a method of measuring the uneven shape of a semiconductor wafer used in the method of manufacturing a semiconductor integrated circuit device of the present invention. FIG. 2 is a method of manufacturing a semiconductor integrated circuit device S of the present invention. FIG. 3 is a conceptual diagram showing an example of the principle of a method of measuring the unevenness of a semiconductor wafer used in the present invention. FIG. 3 is an example of the principle of a method of measuring the unevenness of a semiconductor wafer used in the method of manufacturing a semiconductor integrated circuit device of the present invention. FIG. 4 is a conceptual diagram showing an example of the principle of a method of measuring the uneven shape of a semiconductor wafer used in the method of manufacturing a semiconductor integrated circuit device S of the present invention, and FIG. 5 is a semiconductor integrated circuit of the present invention. FIG. 6 is a diagram showing an example of the operation of the method for measuring the unevenness of the semiconductor wafer used in the method of manufacturing the circuit device S. FIG. 6 is a diagram illustrating the unevenness of the semiconductor wafer used in the method of manufacturing the semiconductor integrated circuit device of the present invention. Of measurement method It is a diagram showing an example of.

First, an example of the principle of a method for measuring the three-dimensional intensity distribution of reflected light according to the present invention will be described with reference to FIGS.

There is a close relationship between the exposure and the location where the allowable range of the focal position S is the smallest, and the reflectivity and the concave / convex shape on the semiconductor wafer. The cross-sectional shape (profile) of the resist applied to the semiconductor wafer after development is determined by the three-dimensional light intensity distribution of the circuit pattern projected by the reduction projection optical system.

Since the three-dimensional light intensity distribution is strongly affected by the reflectance and the uneven shape on the semiconductor wafer, the allowable range of the exposure amount and the focal position can be obtained by measuring the reflectance and the uneven shape on the semiconductor wafer. But fi can also find small places.

In a semiconductor manufacturing method for forming a glass film for flattening on a semiconductor wafer having an uneven shape, the method uses the reflectance and the radius of curvature and area of the unevenness on the semiconductor wafer obtained by the above method. Impurity concentration or formation temperature or film material viscosity or By correcting and controlling glass film formation conditions such as the number of rotations of film formation, fluctuations in reflectivity and irregularities on the semiconductor wafer can be reduced.

By irradiating exposure light onto the resist-applied semiconductor ハ X c and piercing the light intensity distribution at a spatial position distant from the pattern surface, the maximum intensity and spatial position are obtained. By determining the radius of curvature and area of the uneven shape on the semiconductor wafer and the surface reflectivity with respect to the exposure light, and correcting and controlling the exposure amount of the projection exposure apparatus, defects such as harshness and short can be prevented.

The three-dimensional light intensity distribution of the circuit pattern projected by the reduction projection optical system can be calculated accurately by simulation, taking into account the reflectivity and unevenness of the semiconductor substrate. Not appropriate because it costs too much.

Figure 1 shows the principle of the means for measuring the three-dimensional light intensity distribution of a circuit pattern. In FIG. 1, the mask pattern 74 is illuminated with illumination light 74a having the same wavelength as the exposure light that exposes the resist. The mask pattern 74 is projected onto the semiconductor wafer 21 having the uneven shape via the half mirror 73 and the projection lens 72. Here, the semiconductor wafer 21 can move up and down, and is set at the best focus position of the projected image.

The reflected light 74 b reflected on the semiconductor wafer 21 having the uneven shape forms a three-dimensional light intensity distribution. In FIG. 1, a detector 71 is set at a position where a three-dimensional spatial light intensity measurement point forms an image via a projection lens 72. Here, the detector 71 can move up and down, and can focus on an arbitrary three-dimensional spatial position.

According to the above configuration, the three-dimensional light intensity distribution of the circuit pattern projected by the reduction projection optical system can be measured.

As will be described later, the mask pattern 74 is not necessarily required in order to quickly find a place where the tolerance 15 of the exposure amount and the focal position is smaller than ft in a short time. In this case, the vertical movement may be performed by either the semiconductor wafer 21 or the detector 71.

There is a close relationship between the exposure amount and the allowable position of the focal position S (the area with the smallest 5) and the reflectance and the unevenness on the semiconductor wafer 21. If possible, it is possible to predict the place where the allowable range of the exposure amount and the focus position is the smallest. In this case, all means for measuring the three-dimensional light intensity distribution of the circuit pattern of FIG. 1 are not required. FIG. 2 shows a principle diagram of the means for establishing the reflectance and the unevenness on the semiconductor wafer 21. In FIG. 2, the illumination school 80 is illuminated with illumination light 80a having the same wavelength as the exposure light that exposes the resist. The illuminating light 80a is radiated as a parallel light beam (Koehler illumination) onto the semiconductor substrate 21 having an uneven shape via a condenser lens 75, a half mirror 73, and a projection lens 72.

The light reflected on the semiconductor wafer 21 having the irregular shape forms a three-dimensional light intensity distribution. In FIG. 2, a detector 71 is set at a position where a three-dimensional spatial light intensity measurement point is imaged via a projection lens 72. Here, the semiconductor wafer 21 can move up and down, and can focus on an arbitrary three-dimensional spatial position S.

According to the above configuration, it is possible to measure the reflectance and the uneven shape on the semiconductor layer 21 _c . The reflected light 7 4 a. Figure 3 shows an example of the positional relationship. In Figure 3,

X = R s i η θ

Z = R (1-c ο s β)

F-Z = X / t a n (20)

There is a relationship. Therefore, the focus (F) is

F = R (l-cos ^ + s η η θ / t a n (20))

When the angle 0 is small enough, the focus (F) is

F = R / 2

Becomes

FIG. 4 shows the relationship between the reflection angle of the reflected light and the focal position when the semiconductor substrate 21 has a convex shape. The same relational expression as in FIG. 3 holds.

X = R s i η θ

Z = R (l-c os 0)

Ζ-F = Χ / t a n (20)

There is a relationship. Therefore, the focus (F) is

F = R (1 cos 0-si η 0 / tan (20)) If the angle 0 is small enough, the focal point (F) becomes F =-R / 2

Becomes In this case, a virtual image is formed.

FIG. 5 shows the intensity distribution of reflected light in the focal direction when the semiconductor wafer 21 is concave ₍ FIG. 6 shows the intensity distribution of reflected light in the focal direction when the semiconductor wafer 21 is convex).

In FIG. 5 when the semiconductor wafer 21 has a concave shape, the standard focus position is a position where the pattern surface of the semiconductor wafer 21 is focused, and the position with the maximum light intensity is in the plus direction. The position of the maximum light intensity—the standard focal position is the concave radius of curvature 1 Z 2, which coincides with the focal position of the concave mirror. The maximum light intensity is proportional to the surface of the concave mirror. Therefore, by measuring the position and the maximum value of the maximum light intensity, the radius of curvature of the concave shape can be obtained from the distance between the standard focal position S and the position of the maximum light intensity. Can be requested.

In FIG. 6 where the semiconductor wafer 21 has a convex shape, the position where the light intensity is maximum is in the negative direction. Similarly, by shaving the position where the light intensity is maximum and the maximum value, the curvature of the convex shape is obtained. The radius and surface ridge can be determined.

According to the above-described measurement principle of the present invention, the unevenness of the semiconductor wafer 21 can be known. This makes it possible to predict in a short time a place where the allowable range of the exposure amount and the focus position is the smallest, and it is possible to determine control values such as the exposure conditions in the manufacturing process and the conditions for forming a thin film for planarization. It can be realized quickly.

In addition, at any time during the manufacturing process, a sampling inspection is performed on the surface of the semiconductor wafer 21 for irregularities, and when the photo resist is applied, the exposure condition of the photo resist is changed. It is possible to perform fine adjustment and optimal control. Further, based on the inspection result in a state in which the photo resist is not applied, for example, the conditions for forming a thin film for flattening the unevenness of the semiconductor wafer 21 are controlled, and if necessary, a normal Process control, such as selectively switching from a photo resist to a multilayer resist process with less occurrence of exposure failure due to irregularities, becomes possible.

Next, a method for manufacturing a semiconductor integrated circuit device of the present invention using the above principle will be described more specifically.

FIG. 7 shows a semiconductor integrated circuit device manufacturing method according to an embodiment of the present invention. FIG. 3 is a perspective view showing an example of the configuration of an apparatus for measuring the reflectance and the uneven shape on a semiconductor wafer.

Compared with the principle diagram of the means for measuring the reflectivity and uneven shape on the semiconductor wafer shown in Fig. 2 above, alignment with the external shape of the semiconductor wafer orifice notch, etc., and the use of evening target patterns A mechanism necessary for the positioning and the like is added. In FIG. 7, the inspection light 7 a emitted from a light source 7 such as an Hg lamp, for example, i-line (wavelength 365 nm) and e-ray (wavelength 546 nm) 7 a is a condenser lens 8. After being converged through the camera, the shutter mechanism 4, the wavelength switching mechanism 3, the illumination intensity variable mechanism 2, the illumination sigma switching mechanism 1 (illumination center-of-gravity point adjustment mechanism), the relay lens 9, the auto focus 镇 pattern 5, and the mirror 10, the relay lens 11, the half mirror 12, the magnification switching mechanism 6, and the objective lens 20 irradiate the surface of the semiconductor substrate 21. The reflected light 7b reflected from the semiconductor substrate 21 is incident on a detector 16 such as a TV camera for detecting a pattern image via a half mirror 12, a mirror 14 and a relay lens 15.

The semiconductor wafer 21 is mounted on a 0 stage 34, which is rotatable around the optical axis of the inspection light 7a applied to the semiconductor substrate 21. The 0 stage 34 is a light source of the inspection light 7a. Z stage 33, which can move up and down and tilt in the axial direction, supported by X stage 32, Y stage 31, which can move independently in two directions perpendicular to each other in a plane perpendicular to inspection light 7a Have been.

The Y stage 31, the X stage 32, the Z stage 33, the 0 stage 34, etc. are necessary to align the position of the semiconductor ゥヱ C 21, and in this embodiment, the 0 stage 34 is more than 360 degrees. The semiconductor wafer 21 can be aligned with the outer shape of the orientation flat 22 notch or the like.

For example, as shown in FIG. 21, a semiconductor substrate 21 of the present embodiment forms a wiring pattern 21 b made of aluminum or the like on a semiconductor substrate 21 a, and The structure is such that 21b is covered with an insulating film 21c. Since the surface of the insulating film 21c is in an uneven state reflecting the unevenness of the underlying wiring pattern 21b, a glass film 21d using, for example, SOG is formed to alleviate this. It achieves flattening. And on this glass membrane 21d, for example, aluminum or A conductive thin film 21 e is formed.

The conductive thin film 21 e is turned and turned by applying a photoresist 21 f and exposing and developing, and the glass film 2 e is etched by using the photoresist 21 f as a mask. A photolithography process of forming the next wiring pattern 21 e on 1 d is performed.

In the case of the present embodiment, shaping and evaluation of the uneven shape and the reflectance in a state where the glass film 21 d and the conductive thin film 21 e are applied are performed. The optical systems provided on the optical path of the inspection light 7a from the light source 7 to the semiconductor wafer 21 and on the optical path of the reflected light 7b are i-line (wavelength 365 nm) and e-line (wavelength 54 6 nm) has been completely corrected for chromatic aberration. In positioning, it is desirable to use e-rays that do not expose the photo resist 21 f.

When positioning the semiconductor wafer 21 with respect to the outer shape of the orientation flat 22 notch, etc., the objective lens 20 needs a very low magnification lens with a magnification of about 2 times. Therefore, a special device as shown in Fig. 8 is required. In other words, since the ultra-low magnification objective lens 13 of about 2 times requires a very long distance from the chromatic aberration correcting lens 13a to the semiconductor device 21a, a plurality of mirrors 13b to 13e are required. It is necessary to lengthen the optical path length by using.

When performing position alignment using a target pattern on the semiconductor device 2I, a low-magnification lens 17 with a magnification of the objective lens 20 of about 10 is required. In addition, when shaving the reflectance or the uneven shape on a semiconductor wafer, a high-magnification lens 18 having a magnification of about 100 times the objective lens 20 is required.

For this reason, the present embodiment has a magnification switching mechanism 6 that switches the magnification in three stages by switching the ultra-low magnification objective lens 13, low magnification lens 17, and high magnification lens 18. With such a configuration, since the detection can be performed by the same detector 16, the structure of the apparatus is simplified and the cost is reduced.

When aligning the semiconductor wafer 21 with the outer shape of the orientation flat 22 notch, etc., when aligning using the target pattern on the semiconductor wafer 21, In the case of measuring the reflectance and the unevenness on the semiconductor substrate 21, the optimum illumination conditions are often different for each of the above. Generally, in alignment, an illumination value of 0.5 to 0.6 is used. In the case of measuring the reflectance and the uneven shape on a semiconductor wafer, the illumination σ value is preferably 0.4 or less. In the present embodiment, the illuminance distribution on the pupil can be detected at the same time, and the film thickness and the like can be measured. In this case, the illumination σ value needs to be 1 or more. It has a lighting sigma switching mechanism 1 to satisfy all of these requirements. As illustrated in FIG. 9, the illumination σ switching mechanism 1 is configured with a variable aperture 1a that arbitrarily adjusts the optical path cross section の of the inspection light 7a.

In addition, as shown in FIG. 10, for example, as shown in FIG. 10, the pattern 5 for automatic focusing provided in the illumination optical system for guiding the inspection light 7a onto the semiconductor substrate 21 has an optical axis of the inspection light 7a. It is composed of two sets of color patterns 5c and 5d arranged on two sets of transparent substrates 5a and 5b which are inserted so as to slightly deviate from the focal position S in the direction. . The two sets of pel patterns 5c.5d are projected onto the semiconductor wafer 21 and the patterns 5c and 5d reflected on the semiconductor wafer 21 are detected by the detector 16. The automatic focus control can be performed from the contrast of the pel pattern 5C, 5d. C The illumination intensity variable mechanism 2 is provided on the surface of the transparent substrate 2b in the circumferential direction as illustrated in FIG. In this configuration, the metal thin film 2a is applied so that the film thickness (transmittance) changes continuously, and the inspection light 7a power <, the eccentric position S of the transparent substrate 2b is transmitted. By rotating the inspection light 7a, the illuminance (transmittance) of the inspection light 7a can be continuously adjusted.

As exemplified in FIG. 12, the wavelength switching mechanism 3 has a configuration in which a plurality of filters 3 b to 3 e such as neutral density filters having different wavelengths of transmitted light are arranged on a substrate 3 a. Inspection light 7a Force The inspection light 7a is set by transmitting the substrate 3a so that it passes through the center S, and rotated to match any of the filters 3b to 3e. The wavelength of a can be changed.

According to the above configuration, the position of the orientation flat 22 of the semiconductor wafer 21 is aligned, and the position of the semiconductor wafer 21 is adjusted using the target pattern on the semiconductor wafer 21. Measurement of unevenness and the like can be performed.

That is, first, the ultra-low magnification objective lens 13 is selected by the magnification switching unit 6, and the Y stage 31 and the X stage are observed while the semiconductor wafer 21 is observed by the detector 16. The orifice 22 is positioned so as to be positioned in a predetermined direction around the optical axis of the inspection light 7a by appropriately operating the z stage 32, the Z stage 33, and the zero stage 34. Then, by switching to the low-magnification lens 17 by the magnification switching mechanism 6, the alignment mark (for example, two places) provided in the semiconductor 21 is recognized by the detector 16, and the semiconductor laser 17 is recognized. Holds each position of 1—X—Y—0.

After that, the high-magnification lens 18 is selected by the magnification switching mechanism 6 and is positioned at a target area in the semiconductor wafer 21, and the unevenness and the reflectance of the surface of the semiconductor wafer 21 are measured. The radius of curvature S indicating the surface irregularities and the area of the reflection area are determined by the reflected light at the detector 16 when the Z stage 33 is moved up and down, as in the principle illustrated in FIGS. 1 and 2 described above. The radius of curvature of the unevenness of the semiconductor wafer 21 is measured from the peak position of the change in the detected light amount of 7b and the distance of the focal position of the optical system for guiding the inspection light 7a to the semiconductor wafer 21 with respect to the semiconductor wafer 21; From the beak value of the detected light amount of the reflected light 7b, measure the area of the reflection area between the concave part and the convex part.

In a method for manufacturing a semiconductor integrated circuit device g in which a glass film 21 d for planarization is formed on a semiconductor wafer 21 having an uneven shape, the reflectance and the reflectance on the semiconductor substrate 21 obtained by the above method are determined. If the glass film 21 d forming conditions such as the impurity concentration, the forming temperature, the viscosity of the film forming material, and the number of rotations of the film forming are to be corrected and controlled using the curvature radius and the area of the uneven shape, the film must be formed in advance. It is necessary to find the relationship between the condition and the reflectance or the uneven shape. As exemplified in FIG. 14, the relationship between the reflectivity and unevenness of the surface of the semiconductor layer 21 and the film forming conditions of the glass film 21 d is, for example, a quadratic curve. The relationship shown in FIG. 14 is obtained by successively measuring the curvature radius, surface », and reflectance of the uneven shape by the above-described method while changing the 1d formation conditions. The evaluation of the unevenness is better as the radius of curvature is larger and the shape is smaller, and the reflectance is better as the reflectance is smaller. The vertical line in Fig. 14 shows the sign and value of the measured value appropriately normalized so that these evaluations are reflected comprehensively. Therefore, the optimum film forming conditions in FIG. 14 indicate the conditions for forming the glass film 21 d such that the reflectance is the smallest, the radius of curvature of the uneven shape is the largest, and the area is the smallest.

During the semiconductor manufacturing process, the reflectivity and unevenness of the semiconductor wafer 21 changed In this case, in the present embodiment, the correction amount of the film formation condition is obtained and the correction control of the film formation condition is performed based on the relationship between the film formation condition and the reflectance or the uneven shape obtained in advance as described above:

On the other hand, in a semiconductor manufacturing process in which a pattern is transferred onto a semiconductor wafer 21 having an uneven shape using a projection exposure apparatus, the photo resist 21 f was applied using the apparatus S in FIG. 7 described above. By irradiating exposure light onto the semiconductor wafer having the uneven shape, measuring the light intensity distribution at a spatial position distant from the pattern surface, and determining the maximum intensity and the space position at which the maximum intensity is obtained, the semiconductor wafer 21 is exposed. The curvature radius, surface type, and surface reflectivity of the exposure light are calculated.

From this measurement result, the exposure S margin, which causes a failure such as a halting short, is pre-shaved, and the exposure S of the projection exposure apparatus S is corrected and controlled based on the result. To prevent

FIG. 15 shows an example of the relationship between the amount of exposure and the reflectance of the semiconductor wafer 21 and the unevenness of the semiconductor wafer 21. The vertical line in FIG. 15 shows the same evaluation of the reflectance and the uneven shape as the vertical line in FIG. Therefore, FIG. 15 indicates that the lower the reflectance, the larger the radius of curvature of the concave-convex shape, and the smaller the surface of the reflection region, the larger the exposure dose margin.

In addition, the state of the uneven shape in each region in the semiconductor wafer 21 is different, and the margin of the exposure amount is different. Therefore, the area where the margin is the smallest, that is, the area where the curvature radius of the unevenness is small and the surface of the reflection area is large is specified by the device S in FIG. 7, and the optimal exposure amount and focal position S in this area are managed. The exposure operation of the semiconductor wafer 21 is performed with the value determined.

Hereinafter, an example of the operation of the method for manufacturing a semiconductor integrated circuit device according to the present embodiment will be described with reference to the flowchart in FIG.

First, the relationship between the formation conditions of the glass film 21d for flattening, as illustrated in FIG. At the same time, the relationship between the exposure conditions shown in Figure 15 and the reflectance and the irregularities, and the control values are obtained (Step 200). C Next, a glass film is formed on the semiconductor wafer 21 under the optimum film formation conditions. 2 Id is formed (step 201).

Next, the reflectance and the uneven shape of the semiconductor wafer 21 were measured by a sampling inspection. Yes (Step 202).

Next, it is determined whether or not the reflectance and the unevenness are within the allowable range (step 203). If the reflectivity and the unevenness are within the allowable range, the glass film 21 d is formed under the current optimum film forming conditions. ₍ Next, if the concavo-convex shape is not within the allowable 15 range, the current optimum film formation conditions are corrected (step 204), and the photo resist 21 1 f ( In the case of the present embodiment, the formation, exposure and development of a single-layer photo resist 21 f are used as an example (Step 205). Exposure amount and focus position S are managed using the management values set based on the area with the tightest margin, which was determined in step 2. In addition, the photo resist 21 f is attached if necessary. For the semiconductor wafer 21 in the state shown in FIG. Performs a measurement of the reflectance, may be corrected exposure conditions.

Then, it is checked whether or not the pattern of the photo-register 21f formed on the semiconductor substrate 21 is normal (step 206).

Follower The Torejisu Doo 2 1 form Fushimi of f pattern is normal埸合, follows the Photo a pattern of registry 2 1 f proceeds to etching of a mask (Step 2 0 7) _c Semiconductor etching It is checked whether or not the etching pattern formed on the surface of the wafer 21 is normal (whether or not there is a defect such as a short circuit or a disconnection) (step 208).

If the etching pattern is normal, the manufacturing process of the subsequent semiconductor wafer 21 in the lot is executed under the film formation conditions corrected in step 204 (step 209).

On the other hand, if at least one of the determination of the pattern shape of the photoresist 21 f in step 206 and the determination of the shape of the etching pattern in step 208 is determined to be defective, the process is performed. Change (step 210). Specifically, instead of the above-described single-layer photoresist 21 f, a multilayer photoresist including an anti-reflection film or the like, which is effective against failure caused by unevenness or a large reflectance. In the photolithography process after the change, the subsequent semiconductor wafer 21 in the same lot is started by the changed photolithography process (step 211). According to the manufacturing method of the example semiconductor integrated circuit device S, the semiconductor wafer 21 having a small margin of the exposure condition, a concave-convex shape, and a reflectance. In addition to determining the management value of the exposure condition by specifying the region, the exposure condition can be corrected according to the fluctuation of the uneven shape and the reflectance.

In addition, the conditions for forming the glass film 21 d for planarization can be optimized from the viewpoint of the unevenness of the surface of the semiconductor wafer 21 and the reflectance, and the formation conditions can be corrected. .

As a result, it is possible to reduce a dimensional variation error, a disconnection defect, a short defect, and the like of a circuit pattern formed on the semiconductor substrate 21 by photolithography, and to improve a manufacturing yield of the semiconductor integrated circuit device.

If the process failure is expected to occur frequently in the normal single-layer photo resist 21 f according to the reflectivity of the surface of the semiconductor substrate 21 and the state of the irregularities, for example, the process is performed as follows. Although the process becomes more complicated and the throughput is reduced, it is possible to accurately switch to a process using a multilayer resist including an antireflection film that is less likely to cause defects due to the reflectance and the uneven shape, thereby improving the yield and throughput. The optimization of the balance of the birds can be realized.

FIG. 16 shows another example of the configuration of the device S for measuring the reflectance and the unevenness on the semiconductor wafer used in the method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention. FIG.

The optical system illustrated in FIG. 16 is an optical system equivalent to a confocal microscope, and a laser, an Hg lamp, an Xe lamp, or the like is generally used as the light source 51. The illumination light 51a passes through a condenser lens 52, a half mirror 53, a movable illumination lens 54, and a projection lens 55, and is spotted on a semiconductor wafer 21 mounted on a vertically movable support base. Irradiated to the bottom. The movable lighting school 54 has, for example, a structure in which a number of through-holes 54a are formed in a disk 54b, and these through-holes 54a are illumination light 51a and reflected light. An operation of rotating the disk 54b at high speed is performed so as to cross the optical path of 51b. For this reason, the surface of the semiconductor X X 21 is illuminated with a uniform illumination over time by scanning of the spot of the illumination light 51 a having no coherence. The influence of interference or the like can be eliminated from 1b.

The reflected light 51b reflected on the semiconductor wafer 21 travels in the same path as the illumination light 51a in the opposite direction, and again passes through the movable illumination stop 54, the half mirror 53, and the projection lens 56. An image is formed on a detector 57 composed of an image sensor or the like.

When the semiconductor substrate 21 is flat, the light amount becomes maximum at the position S of the best focus, and the light S decreases even if the focus shifts above or below the semiconductor wafer 21. When the semiconductor wafer 21 has a concave surface, the light position becomes maximum when the focus position is above the semiconductor wafer 21, and the light amount decreases at other positions. When the semiconductor wafer is convex, the light amount becomes maximum when the focus position is below the semiconductor wafer, and decreases at other positions.

From the above relationship, the uneven shape on the semiconductor wafer 21 can be measured. Thereby, the same effect as in the case of the first embodiment can be obtained, and the influence of interference or the like can be eliminated from the reflected light 51b, so that the light intensity of the reflected light 51b in the three-dimensional space can be improved. Measurement can be performed with high accuracy.

Since the present invention is configured as described above, the following effects can be obtained.

(1) It is possible to find out in a short time a place on a semiconductor wafer where the allowable range of the exposure amount and the focal position is the smallest, and to feed back to the management of the manufacturing process.

(2) It is possible to accurately determine fluctuations in the reflectivity and irregularities on a semiconductor wafer and feed it back to the manufacturing process, thereby optimizing the manufacturing process and improving the yield.

(3) It is possible to prevent defects such as haration and short circuit, and to improve the yield in the manufacturing process of the semiconductor converging circuit device.

Industrial applicability

As described above, the method for manufacturing a semiconductor integrated circuit device according to the present invention is effective in countermeasures for a product defect caused by the surface roughness of the semiconductor device X in the manufacturing process of the semiconductor congestion circuit device.

Claims

The scope of the claims

1. (a) Irradiate inspection light onto a semiconductor wafer having an uneven shape, measure the light intensity distribution at a spatial position distant from the pattern surface, and determine the radius of curvature and area of the unevenness on the semiconductor wafer. Determining the exposure value and the focus position in a small allowable range, and determining the management value of the exposure condition based on the small allowable 15 range; and

(b) a step of performing an exposure process on the semiconductor wafer using the control value.

2. The method for manufacturing a semiconductor integrated circuit device according to claim 1,

Determining the radius of curvature from a difference between a focal position of the inspection light with respect to the semiconductor X and a peak position of the light intensity distribution, and determining the surface »from the light intensity at the peak position S. Semiconductor device manufacturing method.

3. The method for manufacturing a concealed semiconductor integrated circuit according to claim 1,

A method of manufacturing a semiconductor integrated circuit device S, wherein exposure light used for exposure processing of the semiconductor wafer is used as the inspection light for establishing the light intensity distribution.

4. In the method for manufacturing a semiconductor integrated circuit device according to item 1,

A method for manufacturing a semiconductor collecting circuit device, wherein the light intensity distribution is measured by illuminating with the inspection light that has passed through a mask pattern used for exposure processing of the semiconductor wafer.

5. Scope of the training In the method for manufacturing a semiconductor transplanted circuit device according to item 1,

A method for manufacturing a semiconductor integrated circuit, comprising using a Koehler illumination for irradiating the semiconductor wafer with the inspection light as a parallel light beam.

6. The method for manufacturing a semiconductor integrated circuit device according to claim 1,

A method for manufacturing a semiconductor integrated circuit device S, comprising using a confocal microscopic optical system that scans and illuminates the semiconductor wafer with a spot of the inspection light.

7. (a) A method for manufacturing a semiconductor integrated circuit device S including a step of forming a flattening film for flattening on a semiconductor wafer having an uneven shape,

(b) Irradiating inspection light on the semiconductor wafer having the uneven shape, Inserting a light intensity distribution at a spatial position distant from the semiconductor wafer to obtain a radius of curvature, surface roughness, and reflectance of the uneven shape on the semiconductor wafer, and determining a correlation with a forming condition of the flattening film. When,

(C) measuring the surface of the semiconductor wafer on which the flattening film is formed during the manufacturing process, and correcting the formation condition of the flattening film based on the correspondence relationship. Semiconductor manufacturing circuit S

8. In the method for manufacturing a semiconductor congestion circuit device according to claim 7,

A semiconductor, wherein the radius of curvature is determined from a difference between a focal position S of the inspection light with respect to the semiconductor wafer and a peak position of the light intensity distribution, and the surface is determined from the light intensity at the peak position. Manufacturing method of harvesting circuit device.

9. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein

A semiconductor integrated circuit, wherein the formation condition of the flattening film includes at least one of an impurity concentration, a formation temperature, a viscosity of a film forming material, and a rotation speed during film formation by spin coating. A method for manufacturing a circuit device.

10. The method for manufacturing a semiconductor integrated circuit device S according to claim 7, wherein

A method for manufacturing a semiconductor integrated circuit device, comprising: using exposure light used for exposure processing of the semiconductor wafer as the inspection light for measuring the light intensity distribution.

11. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein

A method of manufacturing a semiconductor integrated circuit device S, wherein the light intensity distribution is measured by illuminating the inspection light transmitted through a mask pattern used for exposure processing of the semiconductor wafer.

12. The method for manufacturing a semiconductor integrated circuit device S according to claim 7,

A method for manufacturing a semiconductor integrated circuit device S, wherein Koehler illumination for irradiating the semiconductor wafer with the inspection light as a parallel light beam is used.

13. The method for manufacturing a semiconductor integrated circuit device S according to claim 7,

A method for manufacturing a semiconductor integrated circuit device g, comprising using a confocal microscope optical system that scans and illuminates the semiconductor laser X with a spot of the inspection light.

14. (a) A semiconductor wafer having a concave and convex shape coated with a resist is irradiated with exposure light, and a light intensity distribution at a spatial position S away from the pattern surface is measured to measure the semiconductor wafer. Determining the correlation between the radius of curvature and the surface of the irregularities above and the surface reflectance of the exposure light, and determining the amount of exposure that causes exposure failure;

(b) A method for manufacturing a semiconductor integrated circuit device, comprising a step of correcting an exposure amount during the II light process based on the correlation.

15. The method for manufacturing a semiconductor integrated circuit device according to claim 14, wherein the half curvature is obtained from a difference between a focal position of the exposure light with respect to the semiconductor X and a peak position of the light intensity distribution. A method of manufacturing the semiconductor integrated circuit device S, wherein the surface ridge is determined from the light intensity at the beak position.

16. The method for manufacturing a semiconductor integrated circuit device according to claim 14, wherein the light intensity distribution is measured by illuminating with the exposure light transmitted through a mask pattern used for exposure processing of the semiconductor wafer. Semiconductor collection 9 [Circuit device manufacturing method.

17. The method for manufacturing a semiconductor integrated circuit device S according to claim 14, wherein a Koehler illumination for irradiating the semiconductor wafer with the exposure light as a parallel light beam is used. .

18. The method of manufacturing a semiconductor convergence circuit device according to claim 14, wherein a confocal microscopy system that scans and illuminates the semiconductor wafer with a spot of the exposure light is used. Semiconductors «Circuit device S manufacturing method.

19. (a) Irradiation of inspection light onto a semiconductor wafer having irregularities and measurement of the light intensity distribution at a spatial position S distant from the pattern surface, and measurement of the irregularities on the semiconductor wafer. Determining a radius of curvature and an area to specify a region where the allowable range of the exposure amount and the focal position S is small, and determining a management value of the exposure condition based on the region where the allowable range is small;

(b) irradiating inspection light onto the semiconductor wafer having the irregularities, measuring a light intensity distribution of a spatial position B away from the pattern surface, and measuring a radius of curvature of the irregularities on the semiconductor wafer and A step of obtaining a face and a reflectance, and determining a correlation with a condition for forming a flattening film for flattening on the semiconductor wafer;

(c) using the optimum conditions for forming the planarizing film to form the planarizing film for planarization. A step of forming

(d) measuring the radius of curvature and surface curvature of the reflectance and the unevenness of the semiconductor wafer;

(e) If the measured reflectance and the radius of curvature and area of the unevenness of the semiconductor wafer deviate from an allowable range, the current conditions for forming the flattening film are determined based on the correlation. Steps to correct,

(f) a step of exposing and developing the preceding semiconductor wafer in the lot containing the semiconductor X by using the control value,

(g) inspecting the photo resist pattern formed by the exposure and development processing;

(h) when the inspection result of the photo resist pattern is normal, performing etching using the photo resist pattern as a mask;

(i) a stezer for inspecting an etching pattern obtained by the etching,

(j) a step of changing to a process using a multilayer photoresist if at least one of the inspection of the photoresist pattern and the inspection of the etching pattern is determined to be abnormal;

A method for manufacturing a semiconductor integrated circuit device, comprising: