WO1996032738A1 - A METHOD FOR INTRODUCTION OF AN IMPURITY DOPANT IN SiC, A SEMICONDUCTOR DEVICE FORMED BY THE METHOD AND A USE OF A HIGHLY DOPED AMORPHOUS LAYER AS A SOURCE FOR DOPANT DIFFUSION INTO SiC - Google Patents

A METHOD FOR INTRODUCTION OF AN IMPURITY DOPANT IN SiC, A SEMICONDUCTOR DEVICE FORMED BY THE METHOD AND A USE OF A HIGHLY DOPED AMORPHOUS LAYER AS A SOURCE FOR DOPANT DIFFUSION INTO SiC Download PDF

Info

Publication number
WO1996032738A1
WO1996032738A1 PCT/SE1996/000451 SE9600451W WO9632738A1 WO 1996032738 A1 WO1996032738 A1 WO 1996032738A1 SE 9600451 W SE9600451 W SE 9600451W WO 9632738 A1 WO9632738 A1 WO 9632738A1
Authority
WO
WIPO (PCT)
Prior art keywords
dopant
layer
sic
near surface
surface layer
Prior art date
Application number
PCT/SE1996/000451
Other languages
French (fr)
Inventor
Christopher Harris
Andrei Konstantinov
Erik Janzén
Original Assignee
Abb Research Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Abb Research Limited filed Critical Abb Research Limited
Priority to JP8530948A priority Critical patent/JPH11503571A/en
Priority to EP96910271A priority patent/EP0820637A1/en
Publication of WO1996032738A1 publication Critical patent/WO1996032738A1/en

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/48—Ion implantation
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
    • C30B31/20—Doping by irradiation with electromagnetic waves or by particle radiation
    • C30B31/22—Doping by irradiation with electromagnetic waves or by particle radiation by ion-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/931—Silicon carbide semiconductor

Definitions

  • the present invention relates to a method for introduction of an impurity dopant into a semiconductor layer of SiC, comprising a step a) of ion implantation of said dopant in said semiconductor layer at a low temperature as well as a semiconductor device produced by carrying out such a method.
  • Such an ion implantation technique may be used for production of all types of semiconductor devices, such as for example different types of diodes, transistors and thyristors, and it is an attractive technique in device fabrication as it allows room temperature control of both impurity level and distribution.
  • This technique is well developed for Si- devices, but the method successfully used for ion implantation for such devices may not be utilized for SiC-devices, which are particularly used in applications in which it is possible to benefit from the superior properties of SiC in comparison with primarily Si, namely the capabilities ⁇ ity of SiC to function well under extreme conditions.
  • SiC has a high thermal stability due to a large bandgap energy, such that devices fabricated from said material are able to operate at high temperatures, namely up to 1000 K.
  • SiC has a high thermal conductivity, so that SiC devices may be arranged at a high density.
  • SiC also has a more than five times higher breakdown field than Si, so that it is well suited as a material in high power devices operating under conditions where high voltages may occur in the blocking state of a device. Accordingly, it is highly desired to find means to control this technique of device fabrication also for SiC, so that doped high quality regions with a low defect density may be created in SiC by ion implantation.
  • the US patent 3 629 011 describes a method according to the intro ⁇ duction, in which ions are implanted in SiC at room temperature, and the implanted near surface layer is then annealed at a temperature between 1200 and 1600°C for electrically activating the impurity atoms implanted. It has turned out that the crystaline quality of the near sur- face layer thus created is not as high as desired and achievable by using the ion implantation technique for fabricating devices of Si.
  • the object of the present invention is to provide a method of the type mentioned in the introduction, which makes it possible to use the ion implantation technique for producing doped layers in SiC having a very low defect density.
  • This object is in accordance with the invention obtained by carrying out the ion implantation step a) in such a way that a doped and amorphous near surface layer is formed, and by after step a) annealing said semiconductor layer at such a high temperature that said dopant diffuses into the non-implanted sub-layer of said semiconductor layer following said near surface layer.
  • the method according to this invetion makes it possible to obtain pn- junctions and doped SiC layers of very high quality, wherein the active SiC layers are formed via dopant diffusion at the annealing stage into the deeper crystal regions which are not damaged by the ion beam.
  • the re-crystallization rapidly removes the implantation-induced defects within the amorphized layer due to the difference in re-growth mechainsm, and a considerable part of the im ⁇ planted dopant is activated.
  • the remaining defects tend to be in the form of clusters or extended defects which do not diffuse.
  • said near surface layer is amorphized in said implantation step by ion implanta ⁇ tion of the dopant at such dose that said near surface layer becomes highly doped and amorphous. Due to this a high conductivity layer will be obtained after said annealing at the surface and the possibility of forming good quality ohmic contacts with low resistivity is provided. Furthermore, the highly doped near surface layer will act as a dopant reservoir or source for diffusion of dopants into said sub-layer while electrically activating them during the annealing step and it will enhance the rate of diffusion of dopant into the non-implanted sub- layer.
  • the dopant is in said implantation step implanted at a concentration below the amorphization limit of SiC and said near surface layer is then amor- phized by implanting an inert species.
  • an inert species may be for example Ar, Si or C.
  • Such a technique would be appropriated where low doping levels are required.
  • said semicon ⁇ ductor layer of SiC is low-doped and of a first conductivity type and said dopant of a second opposite conductivity type, and step b) is car- ried out so that a graded pn-junction is formed in said sub-layer outside said implanted near surface layer.
  • Boron ions are implanted in step a). It has turned out that Boron may be very useful for creating high quality layers of P-type in SiC through ion im ⁇ plantation, since it has a high diffusivity in SiC and is easily activated through annealing.
  • step a) is carried out in several sub-steps using different implantation energies so as to form a high concentration of the dopant at different depths and a volume with a considerable depth of said highly doped amor ⁇ phous near surface layer. This technique may be used to create a dopant reservoir with a high amount of dopant elements for diffusing into said sub-layer for forming a high quality doped layer there.
  • said semicon ⁇ ductor layer is annealed at a temperature above 1700°C, which will re ⁇ sult in a satisfactory diffusion of the dopant into said sub-layer.
  • the present invention also provides a semiconductor device having a semiconductor layer of SiC formed by carrying out any of the methods in the appended method claims.
  • a semiconductor device will have a doped semiconductor layer with a very high quality for the reasons set out above.
  • the implanted and annealed near surface layer of such a device may be used for forming a contact, so that the nature of this regrown damaged surface as a good contact is utilized.
  • the invention also results in the use of a new type of source for dopant diffusion into a semiconductor layer of SiC, namely a highly doped and amorphous near surface layer of said semiconductor layer.
  • Such a source for dopant diffusion will enhance the rate of diffusion of the dopant and the dopant diffusion may be accurately controlled.
  • Figs 1 and 2 illustrate schematically different steps of a method for in- troduction of an impurity dopant into a semiconductor layer of SiC and thereby creating a semiconductor power device in the form of a rectifier diode according to a preferred embodiment of the invention.
  • Figs 1 and 2 illustrate the two important major steps of a large number of steps of a method according to the invention for introduction of an impurity dopant into a semiconductor layer of SiC, which here is used for producing a power diode. All the layers of this device are made of SiC, but it is within the scope of the invention that the other semicon ⁇ ductor layers than that into which an impurity dopant is introduced by ion implantation are of another material than SiC.
  • a device created in this way and schematically shown in Fig 2 has three differently doped layers, namely a first highly doped layer 1 , preferably forming the sub ⁇ strate, of N-type conductivity for making a low resistance contact with an ohmic contact metal plate of the device not shown in Fig 2, a second low-doped N-type conductivity thicker layer 2 arranged thereon and a third thinner P-type conductivity layer 3 arranged in and on the top of the second layer 2 for forming a pn-junction at the interface therewith and which is created according to the method of the present invention.
  • the space charge region is primarily provided by said second low-doped layer 2, which will take the main part of the voltage applied on the device in the reverse operating direction thereof, and such a device may have a breakdown voltage in the kV-range.
  • the method according to the invention will now be explained while re ⁇ ferring to Figs 1 and 2.
  • the top of the SiC layer 2 is coated by a mask material 4, which has been etched so as to expose the SiC layer in a central region 5 thereof, where ions are to be implanted.
  • the mask may preferably be made of AIN, which may withstand the high tem ⁇ peratures in the annealing step of the process, but another masking material may also be used, but that may necessitate the removal thereof before annealing.
  • RIE reactive ion etching
  • ions are implanted by accel- eration thereof into this central region 5 of the SiC layer 2.
  • the ions are preferably aluminium or boron ions. Al is preferred due to its low ionisation energy, where B has the advantage of higher diffusivity and good activation behaviour.
  • the energy used for the bombardement of said central region 5 by the ions is preferably in the range of 100 KeV - 300 KeV.
  • the implantation is preferably carried out in the form of multiple implants in several sub-steps using different implantation energies so as to form a high concentration of the dopant at different depths and form a volume of a highly doped near surface layer 6 having a considerable depth.
  • the implantation is carried out at a dose making the so formed near surface layer 6 amorphous, and a threshold for achieving this is a surface concentration of the dopant of approxi ⁇ mately 10 ⁇ 5 cm -2 .
  • the implantation is preferably carried out at a dose creating a surface concentration of the dopant of substantially 10 16 cm"2 and a volume concentration in the near surface layer exceeding 10 19 cm" 3 , preferably exceeding 1 ⁇ 20 cm -3 .
  • the highly doped amor ⁇ phous near surface layer 6 created in this way may have a depth of approximately 0,25 ⁇ m.
  • the implantation of the ions at these high doses resulting in an amorphous near surface layer will give rise to ex ⁇ tended defects in the form of clusters in this layer.
  • the implantation is carried out at a low temperature, which means a temperature below 400 K, preferably at normal temperature, i.e. close to room temperature.
  • the implantation step may be followed by a step of removal of the mask material 4 by for instance RIE, or the mask may be removed after the following annealing step. Alternatively if the mask is not degraded by the anneal it may be left to form part of the surface passivation of the device.
  • the annealing step is carried out at such a temperature and for such a time that the dopant implanted in the near surface region 6 is not only well activated but also diffuses so far into the non-implanted sub-layer of the semiconductor layer 2 following said near surface layer that the region of said sub-layer receiving the diffused dopant will form a graded pn-junction with the low-doped semiconducting layer 2 well away from the damaged near surface layer 6.
  • the annealing will result in an enhanced diffusion of the dopant into said non-implanted sub-layer, since the amorphous high doped layer 6 will act as a dopant reservoir which enhances the rate of diffusion due to the high concentration of the dopant therein.
  • the defects in the near surface layer 6 in the form of clusters may not dif- fuse from the implanted layer, so that the third layer 3 so created will have a very high order with hardly any defects.
  • the third layer 3 produced in this way is indicated in Fig 2 by points. This layer may have a depth of approximately 0,5 ⁇ m.
  • the doping profile in this diffused layer may be expected to have a concentration of boron atoms of approximately 10 18 cm -3 close to the near surface layer 6 and 10 1 6 cm -3 mostly remote therefrom.
  • the annealing of the near surface layer 6 will result in a regrowth of this damaged layer, but the quality thereof will not be sufficient to work itself as a good pn-junction.
  • this damaged surface may be a good contact, so that it may be used as a contact for the device produced by carrying out the method. It would also be possible to remove said near surface layer 6 by any suitable technique after the annealing.
  • the layers 1 , 2, 3 and 6 as well as the mask 4 have been shown in proportions deviating from the reality for the sake of clearness, and the thickness of the layers 1 and 2 may typically be in the range of about 5 ⁇ m and 25-40 ⁇ m or larger, respectively.
  • the method according to the invention is applicable to all types of in- troduction of an impurity dopant into a semiconductor layer of SiC, es ⁇ pecially where a p-doped layer is required, not only to the formation of a pn-junction.
  • the formation of contact layers may be mentioned as an example of an alternative application.
  • the invention describes a technique appropriate to implantation of p-type dopants, n-type implantation, although possible to achieve by similar means, has a well established technique which does not require the method here described to achieve suitable device quality layers.
  • SiC layer includes that this SiC layer may consist of several sub-layers as shown in the Figures. Furhermore, the definition layer is to be interpreted broadly and comprises all types of volume extensions and shapes.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electromagnetism (AREA)
  • Mechanical Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for introduction of an impurity dopant into a semiconductor layer (2) of SiC comprises a step (a) of ion implantation of said dopant in said semiconductor layer at a low temperature. The ion implantation is carried out in such a way that a doped and amorphous near surface layer (6) is formed, and the implantation step is followed by a step of annealing said semiconductor layer at such a high temperature that said dopant diffuses into the non-implanted sub-layer (3) of said semiconductor layer following said near surface layer.

Description

A method for introduction of an impurity dopant in SiC, a semiconduc¬ tor device formed by the method and a use of a highly doped amor- phous layer as a source for dopant diffusion into SiC
TECHNICAL FIELD OF THE INVENTION AND PRIOR ART
The present invention relates to a method for introduction of an impurity dopant into a semiconductor layer of SiC, comprising a step a) of ion implantation of said dopant in said semiconductor layer at a low temperature as well as a semiconductor device produced by carrying out such a method.
Such an ion implantation technique may be used for production of all types of semiconductor devices, such as for example different types of diodes, transistors and thyristors, and it is an attractive technique in device fabrication as it allows room temperature control of both impurity level and distribution. This technique is well developed for Si- devices, but the method successfully used for ion implantation for such devices may not be utilized for SiC-devices, which are particularly used in applications in which it is possible to benefit from the superior properties of SiC in comparison with primarily Si, namely the capabil¬ ity of SiC to function well under extreme conditions. SiC has a high thermal stability due to a large bandgap energy, such that devices fabricated from said material are able to operate at high temperatures, namely up to 1000 K. Furthermore, it has a high thermal conductivity, so that SiC devices may be arranged at a high density. SiC also has a more than five times higher breakdown field than Si, so that it is well suited as a material in high power devices operating under conditions where high voltages may occur in the blocking state of a device. Accordingly, it is highly desired to find means to control this technique of device fabrication also for SiC, so that doped high quality regions with a low defect density may be created in SiC by ion implantation.
The US patent 3 629 011 describes a method according to the intro¬ duction, in which ions are implanted in SiC at room temperature, and the implanted near surface layer is then annealed at a temperature between 1200 and 1600°C for electrically activating the impurity atoms implanted. It has turned out that the crystaline quality of the near sur- face layer thus created is not as high as desired and achievable by using the ion implantation technique for fabricating devices of Si.
It has also been discussed to carry out the ion implantation at such a dose that an amorphous near surface layer is formed and then aπneal- ing this layer, which has been successful in the technique of device fabrication in Si, since the amorphous layer will during the annealing be subjected to a "solid phase-epitaxy" or an epitaxial re growth of the layer resulting in a high quality recrystallized layer, but it has turned out that this technique would be useless for SiC, since the annealing of this amorphous layer will result in polycrystalline forms of silicon carbide or defective single crystals of silicon carbide.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method of the type mentioned in the introduction, which makes it possible to use the ion implantation technique for producing doped layers in SiC having a very low defect density.
This object is in accordance with the invention obtained by carrying out the ion implantation step a) in such a way that a doped and amorphous near surface layer is formed, and by after step a) annealing said semiconductor layer at such a high temperature that said dopant diffuses into the non-implanted sub-layer of said semiconductor layer following said near surface layer. The method according to this invetion makes it possible to obtain pn- junctions and doped SiC layers of very high quality, wherein the active SiC layers are formed via dopant diffusion at the annealing stage into the deeper crystal regions which are not damaged by the ion beam. It is found that the creation of an amorphous near-surface layer by ion implantation in SiC is very useful for creating high quality layers and pn-junctions. The creation of an amorphous layer is actually the key to the advantages of the invention. It has appeared that ion implantation, well below a dose giving rise to an amorphous layer, results in a rather slow disorder annealing and in out-diffusion of the major part of the implanted dopant. In addition, point defects created by the implanta¬ tion diffuse into the non-implanted region creating poor material quality even beyond the implanted region. On the other hand, if the near- surface layer is amorphized, the re-crystallization rapidly removes the implantation-induced defects within the amorphized layer due to the difference in re-growth mechainsm, and a considerable part of the im¬ planted dopant is activated. The remaining defects tend to be in the form of clusters or extended defects which do not diffuse.
According to a preferred embodiment of the invention said near surface layer is amorphized in said implantation step by ion implanta¬ tion of the dopant at such dose that said near surface layer becomes highly doped and amorphous. Due to this a high conductivity layer will be obtained after said annealing at the surface and the possibility of forming good quality ohmic contacts with low resistivity is provided. Furthermore, the highly doped near surface layer will act as a dopant reservoir or source for diffusion of dopants into said sub-layer while electrically activating them during the annealing step and it will enhance the rate of diffusion of dopant into the non-implanted sub- layer.
According to another preferred embodiment of the invention the dopant is in said implantation step implanted at a concentration below the amorphization limit of SiC and said near surface layer is then amor- phized by implanting an inert species. Such an inert species may be for example Ar, Si or C. Such a technique would be appropriated where low doping levels are required. Two problems are simultaneously solved with the use of the controlled amorphization, obtaining a low device resistivity under a forward bias and a low leakage current and a high breakdown voltage under reverse bias.
The disorder with the re-crystallized layer cannot be removed alto¬ gether and if a pn-junction is formed at the interface of the amorphized region with the substrate, we obtain a poor device quality, as obtained by the applicants of US patent 3 629 011.
According to a preferred embodiment of the invention said semicon¬ ductor layer of SiC is low-doped and of a first conductivity type and said dopant of a second opposite conductivity type, and step b) is car- ried out so that a graded pn-junction is formed in said sub-layer outside said implanted near surface layer. By using this method it will be possible to form a graded pn-junction well away from the region heavily damaged by the ion implantation, so that the quality of this junction will be excellent.
It has been found that if acceptor ions are implanted a n-dopant concentration in the top layer of said semiconductor layer of SiC below ' 0' 8 cm"3 will make it possible to form said pn-junction deeper in the crystal due to the greater diffusion of the implanted dopant during the damage annealing. This radically improves the quality of the pn- junction.
According to another preferred embodiment of the invention Boron ions are implanted in step a). It has turned out that Boron may be very useful for creating high quality layers of P-type in SiC through ion im¬ plantation, since it has a high diffusivity in SiC and is easily activated through annealing.
According to a further preferred emobidmsnt Al ions are implatned. Al- though the diffusivity of Al is lower than B it is sufficient using the de¬ scribed technique to form a remote pn-junction. The lower activation energy of Al makes it a preferred dopant. According to a further preferred embodiment of the invention step a) is carried out in several sub-steps using different implantation energies so as to form a high concentration of the dopant at different depths and a volume with a considerable depth of said highly doped amor¬ phous near surface layer. This technique may be used to create a dopant reservoir with a high amount of dopant elements for diffusing into said sub-layer for forming a high quality doped layer there.
According to still a further embodiment of the invention said semicon¬ ductor layer is annealed at a temperature above 1700°C, which will re¬ sult in a satisfactory diffusion of the dopant into said sub-layer.
The present invention also provides a semiconductor device having a semiconductor layer of SiC formed by carrying out any of the methods in the appended method claims. Such a semiconductor device will have a doped semiconductor layer with a very high quality for the reasons set out above.
According to a preferred embodiment of the invention the implanted and annealed near surface layer of such a device may be used for forming a contact, so that the nature of this regrown damaged surface as a good contact is utilized.
The invention also results in the use of a new type of source for dopant diffusion into a semiconductor layer of SiC, namely a highly doped and amorphous near surface layer of said semiconductor layer.
Such a source for dopant diffusion will enhance the rate of diffusion of the dopant and the dopant diffusion may be accurately controlled.
Further preferred features and advantages of the invention will appear from the following description and the other dependent claims. BRIEF DESCRIPTION OF THE DRAWING
With reference to the appended drawing, below follows a specific description of a preferred embodiment of the invention cited as an ex- ample.
In the drawings:
Figs 1 and 2 illustrate schematically different steps of a method for in- troduction of an impurity dopant into a semiconductor layer of SiC and thereby creating a semiconductor power device in the form of a rectifier diode according to a preferred embodiment of the invention.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
Figs 1 and 2 illustrate the two important major steps of a large number of steps of a method according to the invention for introduction of an impurity dopant into a semiconductor layer of SiC, which here is used for producing a power diode. All the layers of this device are made of SiC, but it is within the scope of the invention that the other semicon¬ ductor layers than that into which an impurity dopant is introduced by ion implantation are of another material than SiC. A device created in this way and schematically shown in Fig 2 has three differently doped layers, namely a first highly doped layer 1 , preferably forming the sub¬ strate, of N-type conductivity for making a low resistance contact with an ohmic contact metal plate of the device not shown in Fig 2, a second low-doped N-type conductivity thicker layer 2 arranged thereon and a third thinner P-type conductivity layer 3 arranged in and on the top of the second layer 2 for forming a pn-junction at the interface therewith and which is created according to the method of the present invention. In a rectifier diode having these three layers the space charge region is primarily provided by said second low-doped layer 2, which will take the main part of the voltage applied on the device in the reverse operating direction thereof, and such a device may have a breakdown voltage in the kV-range. The method according to the invention will now be explained while re¬ ferring to Figs 1 and 2. The top of the SiC layer 2 is coated by a mask material 4, which has been etched so as to expose the SiC layer in a central region 5 thereof, where ions are to be implanted. The mask may preferably be made of AIN, which may withstand the high tem¬ peratures in the annealing step of the process, but another masking material may also be used, but that may necessitate the removal thereof before annealing. After the removal of said mask material, preferably by reactive ion etching (RIE), ions are implanted by accel- eration thereof into this central region 5 of the SiC layer 2. The ions are preferably aluminium or boron ions. Al is preferred due to its low ionisation energy, where B has the advantage of higher diffusivity and good activation behaviour. The energy used for the bombardement of said central region 5 by the ions is preferably in the range of 100 KeV - 300 KeV. The implantation is preferably carried out in the form of multiple implants in several sub-steps using different implantation energies so as to form a high concentration of the dopant at different depths and form a volume of a highly doped near surface layer 6 having a considerable depth. The implantation is carried out at a dose making the so formed near surface layer 6 amorphous, and a threshold for achieving this is a surface concentration of the dopant of approxi¬ mately 10^5 cm-2. The implantation is preferably carried out at a dose creating a surface concentration of the dopant of substantially 1016 cm"2 and a volume concentration in the near surface layer exceeding 1019 cm"3, preferably exceeding 1θ20 cm-3. The highly doped amor¬ phous near surface layer 6 created in this way may have a depth of approximately 0,25 μm. The implantation of the ions at these high doses resulting in an amorphous near surface layer will give rise to ex¬ tended defects in the form of clusters in this layer.
The implantation is carried out at a low temperature, which means a temperature below 400 K, preferably at normal temperature, i.e. close to room temperature.
The implantation step may be followed by a step of removal of the mask material 4 by for instance RIE, or the mask may be removed after the following annealing step. Alternatively if the mask is not degraded by the anneal it may be left to form part of the surface passivation of the device. The annealing step is carried out at such a temperature and for such a time that the dopant implanted in the near surface region 6 is not only well activated but also diffuses so far into the non-implanted sub-layer of the semiconductor layer 2 following said near surface layer that the region of said sub-layer receiving the diffused dopant will form a graded pn-junction with the low-doped semiconducting layer 2 well away from the damaged near surface layer 6. This means preferably an annealing temperature of 1700°C. The annealing will result in an enhanced diffusion of the dopant into said non-implanted sub-layer, since the amorphous high doped layer 6 will act as a dopant reservoir which enhances the rate of diffusion due to the high concentration of the dopant therein. Furthermore, the defects in the near surface layer 6 in the form of clusters may not dif- fuse from the implanted layer, so that the third layer 3 so created will have a very high order with hardly any defects. The third layer 3 produced in this way is indicated in Fig 2 by points. This layer may have a depth of approximately 0,5 μm. The doping profile in this diffused layer may be expected to have a concentration of boron atoms of approximately 1018 cm-3 close to the near surface layer 6 and 1016 cm-3 mostly remote therefrom.
Furthermore, the annealing of the near surface layer 6 will result in a regrowth of this damaged layer, but the quality thereof will not be sufficient to work itself as a good pn-junction. However, this damaged surface may be a good contact, so that it may be used as a contact for the device produced by carrying out the method. It would also be possible to remove said near surface layer 6 by any suitable technique after the annealing.
The layers 1 , 2, 3 and 6 as well as the mask 4 have been shown in proportions deviating from the reality for the sake of clearness, and the thickness of the layers 1 and 2 may typically be in the range of about 5 μm and 25-40 μm or larger, respectively.
The invention is of course not in any way restricted to the preferred embodiment described above, but several possibilities to modifications thereof would be apparent to a man with ordinary skill in the art without departing from the basic idea of the invention.
The method according to the invention is applicable to all types of in- troduction of an impurity dopant into a semiconductor layer of SiC, es¬ pecially where a p-doped layer is required, not only to the formation of a pn-junction. The formation of contact layers may be mentioned as an example of an alternative application. The invention describes a technique appropriate to implantation of p-type dopants, n-type implantation, although possible to achieve by similar means, has a well established technique which does not require the method here described to achieve suitable device quality layers.
The definition "SiC layer" includes that this SiC layer may consist of several sub-layers as shown in the Figures. Furhermore, the definition layer is to be interpreted broadly and comprises all types of volume extensions and shapes.
All definitions concerning the material of different layers of course also include inevitable impurities as well as intentional doping when SiC is concerned.

Claims

Claims
1. A method for introduction of an impurity dopant into a semiconduc¬ tor layer (2) of SiC, comprising a step a) of ion implantation of said dopant in said semiconductor layer at a low temperature, charac¬ terized in that the ion implantation step a) is carried out in such a way that a doped and amorphous near surface layer (6) is formed, and that step a) is followed by a step b) of annealing said semiconductor layer at such a high temperature that said dopant diffuses into the non- implanted sub-layer of said semiconductor layer following said near surface layer.
2. A mtthod according to claim 1 , characterized in that said near surface layer (6) is amorphized in said implantation step by ion implantation of said dopant at such a dose that said near surface layer becomes highly doped and amorphous.
3. A method according to claim 1 , characterized in that in said implantation step the dopant is implanted at a concentration below the amorphization limit of SiC and said near surface layer (6) is then amorphized by implanting an inert species.
4. A method according to claim 3, characterized in that Ar, Si or C is implanted as said inert species.
5. A method according to any of claims 1-4, characterized in that the annealing in step b) is carried out at such a high temperature and for such a time that said dopant diffuses so far into said sub-layer that the thickness of the region (3) of said sub-layer receiving the diffused dopant exceeds the thickness of said implanted near surface layer (6).
6. A method according to any of claims 1-5, characterized in that said semiconductor layer (2) of SiC is low-doped and of a first conductivity type and said dopant of a second opposite conductivity type, and that step b) is carried out so that a graded pn-junction is formed in said sub-layer outside said implanted near surface layer (6).
7. A method according to claim 6, characterized in that a dopant of P- type conductivity is implanted in step a).
8. A method according to claim 7, characterized in that Boron ions are implanted in step a).
9. A method according to claim 7, characterized in that Aluminium ions are implanted in step a).
10. A method according to any of claims 2 or 5-9, characterized in that step a) is carried out in several sub-steps using different implan¬ tation energies so as to form a high concentration of the dopant at dif¬ ferent depths and form a volume with a considerable depth of said highly doped amorphous near surface layer (6).
11. A method according to any of claims 2 or 5-10, characterized in that the implantation in step a) is carried out at a dose creating a sur¬ face concentration of the dopant above 1015 cm-2.
12. A method according to any of claims 2 or 5-10, characterized in that the implantation in step a) is carried out at a dose creating a sur¬ face concentration of the dopant of substantially 1θ1β cm-2 or above.
13. A method according to any of claims 2 or 5-12, characterized in that the implantation in step a) is carried out at a dose creating a con¬ centration of the dopant in said near surface layer (6) exceeding 1019 cm-3.
14. A method according to any of claims 2 or 5-13, characterized in that the implantation in step a) is carried out at a dose creating a con¬ centration of the dopant in said near surface layer (6) exceeding 10 ^ cm-3.
15. A method according to any of claims 1-14, characterized in that the implantation energy in step a) is selected to create a depth of said implanted near surface layer (6) above 0,1 μm.
16. A method according to any of claims 1-15, characterized in that said semiconductor layer is kept at a temperature below 400 K during said implantation.
17. A method according to any of claims 1-16, characterized in that said semiconductor layer is annealed at a temperature above 1500°C.
18. A method according to any of claims 1-17, characterized in that said semiconductor layer is annealed at a temperature above 1700°C.
19. A semiconductor device having a semiconductor layer of SiC formed by carrying out the method according to any of claims 1-18.
20. A device according to claim 19, characterized in that said implanted and annealed near surface layer form a contact thereof.
21. Use of a highly doped amorphous near surface layer (6) of a semi¬ conductor layer of SiC as a source for dopant diffusion into said SiC semiconductor layer.
PCT/SE1996/000451 1995-04-10 1996-04-09 A METHOD FOR INTRODUCTION OF AN IMPURITY DOPANT IN SiC, A SEMICONDUCTOR DEVICE FORMED BY THE METHOD AND A USE OF A HIGHLY DOPED AMORPHOUS LAYER AS A SOURCE FOR DOPANT DIFFUSION INTO SiC WO1996032738A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8530948A JPH11503571A (en) 1995-04-10 1996-04-09 Method of introducing impurity dopant into SiC, semiconductor device formed by the method, and use of highly doped amorphous layer as a source of dopant diffusion into SiC
EP96910271A EP0820637A1 (en) 1995-04-10 1996-04-09 A METHOD FOR INTRODUCTION OF AN IMPURITY DOPANT IN SiC, A SEMICONDUCTOR DEVICE FORMED BY THE METHOD AND A USE OF A HIGHLY DOPED AMORPHOUS LAYER AS A SOURCE FOR DOPANT DIFFUSION INTO SiC

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9501310A SE9501310D0 (en) 1995-04-10 1995-04-10 A method for introducing an impurity dopant into SiC, a semiconductor device formed by the method and using a highly doped amorphous layer as a source for dopant diffusion into SiC
SE9501310-8 1995-04-10

Publications (1)

Publication Number Publication Date
WO1996032738A1 true WO1996032738A1 (en) 1996-10-17

Family

ID=20397897

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1996/000451 WO1996032738A1 (en) 1995-04-10 1996-04-09 A METHOD FOR INTRODUCTION OF AN IMPURITY DOPANT IN SiC, A SEMICONDUCTOR DEVICE FORMED BY THE METHOD AND A USE OF A HIGHLY DOPED AMORPHOUS LAYER AS A SOURCE FOR DOPANT DIFFUSION INTO SiC

Country Status (5)

Country Link
US (2) US5851908A (en)
EP (1) EP0820637A1 (en)
JP (1) JPH11503571A (en)
SE (1) SE9501310D0 (en)
WO (1) WO1996032738A1 (en)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE9501310D0 (en) * 1995-04-10 1995-04-10 Abb Research Ltd A method for introducing an impurity dopant into SiC, a semiconductor device formed by the method and using a highly doped amorphous layer as a source for dopant diffusion into SiC
US6100169A (en) * 1998-06-08 2000-08-08 Cree, Inc. Methods of fabricating silicon carbide power devices by controlled annealing
US6107142A (en) * 1998-06-08 2000-08-22 Cree Research, Inc. Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion
JP4186337B2 (en) * 1998-09-30 2008-11-26 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
US6429041B1 (en) 2000-07-13 2002-08-06 Cree, Inc. Methods of fabricating silicon carbide inversion channel devices without the need to utilize P-type implantation
US6391695B1 (en) * 2000-08-07 2002-05-21 Advanced Micro Devices, Inc. Double-gate transistor formed in a thermal process
US6956238B2 (en) * 2000-10-03 2005-10-18 Cree, Inc. Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel
JP4686945B2 (en) * 2001-09-12 2011-05-25 株式会社デンソー Method for manufacturing silicon carbide semiconductor device
US7221010B2 (en) * 2002-12-20 2007-05-22 Cree, Inc. Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors
US6979863B2 (en) * 2003-04-24 2005-12-27 Cree, Inc. Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same
US7074643B2 (en) * 2003-04-24 2006-07-11 Cree, Inc. Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same
US7275357B2 (en) * 2004-03-30 2007-10-02 Cnh America Llc Cotton module program control using yield monitor signal
US7118970B2 (en) * 2004-06-22 2006-10-10 Cree, Inc. Methods of fabricating silicon carbide devices with hybrid well regions
CN1326219C (en) * 2004-06-28 2007-07-11 中国科学院半导体研究所 Method for reducing 4H-silicon carbide resistivity of oriented phosphorus ion filling (0001)
US7476594B2 (en) * 2005-03-30 2009-01-13 Cree, Inc. Methods of fabricating silicon nitride regions in silicon carbide and resulting structures
US7414268B2 (en) 2005-05-18 2008-08-19 Cree, Inc. High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities
US20060261346A1 (en) * 2005-05-18 2006-11-23 Sei-Hyung Ryu High voltage silicon carbide devices having bi-directional blocking capabilities and methods of fabricating the same
US7615801B2 (en) * 2005-05-18 2009-11-10 Cree, Inc. High voltage silicon carbide devices having bi-directional blocking capabilities
US7391057B2 (en) * 2005-05-18 2008-06-24 Cree, Inc. High voltage silicon carbide devices having bi-directional blocking capabilities
JP4919700B2 (en) * 2005-05-20 2012-04-18 トヨタ自動車株式会社 Semiconductor device and manufacturing method thereof
US7528040B2 (en) * 2005-05-24 2009-05-05 Cree, Inc. Methods of fabricating silicon carbide devices having smooth channels
US7728402B2 (en) 2006-08-01 2010-06-01 Cree, Inc. Semiconductor devices including schottky diodes with controlled breakdown
US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
KR101529331B1 (en) 2006-08-17 2015-06-16 크리 인코포레이티드 High power insulated gate bipolar transistors
US8835987B2 (en) 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
JP5339698B2 (en) * 2007-08-20 2013-11-13 新日本無線株式会社 Manufacturing method of semiconductor device
JP4935741B2 (en) * 2008-04-02 2012-05-23 三菱電機株式会社 Method for manufacturing silicon carbide semiconductor device
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
US8796809B2 (en) * 2008-09-08 2014-08-05 Cree, Inc. Varactor diode with doped voltage blocking layer
US8288220B2 (en) 2009-03-27 2012-10-16 Cree, Inc. Methods of forming semiconductor devices including epitaxial layers and related structures
US8294507B2 (en) 2009-05-08 2012-10-23 Cree, Inc. Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits
US8629509B2 (en) 2009-06-02 2014-01-14 Cree, Inc. High voltage insulated gate bipolar transistors with minority carrier diverter
US8193848B2 (en) 2009-06-02 2012-06-05 Cree, Inc. Power switching devices having controllable surge current capabilities
US8541787B2 (en) 2009-07-15 2013-09-24 Cree, Inc. High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability
US8354690B2 (en) 2009-08-31 2013-01-15 Cree, Inc. Solid-state pinch off thyristor circuits
JP5601848B2 (en) * 2010-02-09 2014-10-08 三菱電機株式会社 Method for manufacturing SiC semiconductor device
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
US9142662B2 (en) 2011-05-06 2015-09-22 Cree, Inc. Field effect transistor devices with low source resistance
US9029945B2 (en) 2011-05-06 2015-05-12 Cree, Inc. Field effect transistor devices with low source resistance
JP6042658B2 (en) * 2011-09-07 2016-12-14 トヨタ自動車株式会社 Method for manufacturing SiC semiconductor device
US9373617B2 (en) 2011-09-11 2016-06-21 Cree, Inc. High current, low switching loss SiC power module
US8664665B2 (en) 2011-09-11 2014-03-04 Cree, Inc. Schottky diode employing recesses for elements of junction barrier array
US9640617B2 (en) 2011-09-11 2017-05-02 Cree, Inc. High performance power module
WO2013036370A1 (en) 2011-09-11 2013-03-14 Cree, Inc. High current density power module comprising transistors with improved layout
US8680587B2 (en) 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
US8618582B2 (en) 2011-09-11 2013-12-31 Cree, Inc. Edge termination structure employing recesses for edge termination elements
JP6253133B2 (en) * 2012-04-27 2017-12-27 富士電機株式会社 Method for manufacturing silicon carbide semiconductor device
DE102017118864A1 (en) 2017-08-18 2019-02-21 Infineon Technologies Austria Ag power diode
CN111341651A (en) * 2020-03-11 2020-06-26 四川美阔电子科技有限公司 Method for manufacturing transistor epitaxial layer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629011A (en) * 1967-09-11 1971-12-21 Matsushita Electric Ind Co Ltd Method for diffusing an impurity substance into silicon carbide
US4789644A (en) * 1985-12-23 1988-12-06 Sgs Microelettronica Spa Process for fabrication, by means of epitaxial recrystallization, of insulated-gate field-effect transistors with junctions of minimum depth
US5270244A (en) * 1993-01-25 1993-12-14 North Carolina State University At Raleigh Method for forming an oxide-filled trench in silicon carbide
US5286660A (en) * 1992-12-24 1994-02-15 Motorola, Inc. Method for doping a semiconductor wafer having a diffusivity enhancement region
US5322802A (en) * 1993-01-25 1994-06-21 North Carolina State University At Raleigh Method of fabricating silicon carbide field effect transistor
US5364810A (en) * 1992-07-28 1994-11-15 Motorola, Inc. Methods of forming a vertical field-effect transistor and a semiconductor memory cell

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3563817A (en) * 1966-10-06 1971-02-16 Westinghouse Electric Corp Method of producing silicon carbide ultraviolet radiation detectors
US5087576A (en) * 1987-10-26 1992-02-11 North Carolina State University Implantation and electrical activation of dopants into monocrystalline silicon carbide
JPH0383332A (en) * 1989-08-28 1991-04-09 Sharp Corp Manufacture of silicon carbide semiconductor device
US5399883A (en) * 1994-05-04 1995-03-21 North Carolina State University At Raleigh High voltage silicon carbide MESFETs and methods of fabricating same
SE9501310D0 (en) * 1995-04-10 1995-04-10 Abb Research Ltd A method for introducing an impurity dopant into SiC, a semiconductor device formed by the method and using a highly doped amorphous layer as a source for dopant diffusion into SiC

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629011A (en) * 1967-09-11 1971-12-21 Matsushita Electric Ind Co Ltd Method for diffusing an impurity substance into silicon carbide
US4789644A (en) * 1985-12-23 1988-12-06 Sgs Microelettronica Spa Process for fabrication, by means of epitaxial recrystallization, of insulated-gate field-effect transistors with junctions of minimum depth
US5364810A (en) * 1992-07-28 1994-11-15 Motorola, Inc. Methods of forming a vertical field-effect transistor and a semiconductor memory cell
US5286660A (en) * 1992-12-24 1994-02-15 Motorola, Inc. Method for doping a semiconductor wafer having a diffusivity enhancement region
US5270244A (en) * 1993-01-25 1993-12-14 North Carolina State University At Raleigh Method for forming an oxide-filled trench in silicon carbide
US5322802A (en) * 1993-01-25 1994-06-21 North Carolina State University At Raleigh Method of fabricating silicon carbide field effect transistor

Also Published As

Publication number Publication date
JPH11503571A (en) 1999-03-26
US5851908A (en) 1998-12-22
US6096627A (en) 2000-08-01
SE9501310D0 (en) 1995-04-10
EP0820637A1 (en) 1998-01-28

Similar Documents

Publication Publication Date Title
US6096627A (en) Method for introduction of an impurity dopant in SiC, a semiconductor device formed by the method and a use of a highly doped amorphous layer as a source for dopant diffusion into SiC
US5710059A (en) Method for producing a semiconductor device having a semiconductor layer of SiC by implanting
US6537886B2 (en) Ultra-shallow semiconductor junction formation
US6083814A (en) Method for producing a pn-junction for a semiconductor device of SiC
US5318915A (en) Method for forming a p-n junction in silicon carbide
US5804483A (en) Method for producing a channel region layer in a sic-layer for a voltage controlled semiconductor device
US5441901A (en) Method for forming a carbon doped silicon semiconductor device having a narrowed bandgap characteristic
US8049276B2 (en) Reduced process sensitivity of electrode-semiconductor rectifiers
US5804482A (en) Method for producing a semiconductor device having a semiconductor layer of SiC
US4452645A (en) Method of making emitter regions by implantation through a non-monocrystalline layer
KR100718823B1 (en) A silicon-germanium transistor and associated methods
EP0305513A1 (en) Low leakage cmos/insulator substrate devices and method of forming the same.
US6130144A (en) Method for making very shallow junctions in silicon devices
US4058413A (en) Ion implantation method for the fabrication of gallium arsenide semiconductor devices utilizing an aluminum nitride protective capping layer
US6703294B1 (en) Method for producing a region doped with boron in a SiC-layer
EP3602609B1 (en) Method for p-type doping of silicon carbide by al/be co-implantation
US6828614B2 (en) Semiconductor constructions, and methods of forming semiconductor constructions
US20030222272A1 (en) Semiconductor devices using minority carrier controlling substances
US5674765A (en) Method for producing a semiconductor device by the use of an implanting step
EP0890184B1 (en) A METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR LAYER OF SiC
KR100498607B1 (en) Polysilicon layer formation method of semiconductor device
Fukada et al. Formation of ohmic contacts to n-GaAs by solid phase epitaxy of evaporated and ion implanted Ge films
JP4691224B2 (en) Method of manufacturing a semiconductor device using an implantation step and device manufactured by this method
KR100270073B1 (en) Method of forming shallow junction of semiconductor device with low leakage current
Biasotto et al. Low-complexity full-melt laser-anneal process for fabrication of low-leakage implanted ultrashallow junctions

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1996910271

Country of ref document: EP

ENP Entry into the national phase

Ref country code: JP

Ref document number: 1996 530948

Kind code of ref document: A

Format of ref document f/p: F

WWP Wipo information: published in national office

Ref document number: 1996910271

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1996910271

Country of ref document: EP