WO1996017380A1 - A method and system for providing an integrated circuit device that allows for a high field threshold voltage utilizing resist pullback of the field implant region - Google Patents
A method and system for providing an integrated circuit device that allows for a high field threshold voltage utilizing resist pullback of the field implant region Download PDFInfo
- Publication number
- WO1996017380A1 WO1996017380A1 PCT/US1995/014447 US9514447W WO9617380A1 WO 1996017380 A1 WO1996017380 A1 WO 1996017380A1 US 9514447 W US9514447 W US 9514447W WO 9617380 A1 WO9617380 A1 WO 9617380A1
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- WIPO (PCT)
- Prior art keywords
- region
- nitride
- field
- integrated circuit
- field implant
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
- H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
Abstract
A method and apparatus provides an integrated circuit device that allows for a high field threshold voltage by minimizing the parasitic transistors located therein. The integrated circuit includes a well region, a source/drain region, a nitride layer and a first oxide layer coupled to the well region. The system masks and etches a nitride layer and then provides a field implant region in the well area. Thereafter, it etches the nitride again where the field implant region is moved away from the source/drain region. In so doing, the field implant region is spaced away from the source/drain region of the device and therefore the breakdown voltage of the device is effectively increased.
Description
A METHOD AND SYSTEM POR PROVIDING AM INTEGRATED CIRCUIT DEVICE THAT ALLOWS FOR A HIGH FIELD THRESHOLD VOLTAGE UTILIZING RESI8T PULLBACK OF THE FIELD IMPLANT REGION
FIELD OF THE INVENTION
The present invention is directed toward an improvement in an integrated circuit device and more particularly to an integrated circuit device which provides for high field threshold voltage for programming.
BACKGROUND OF THE INVENTION
In electrical programmable devices (EPROMs) , electrical erasable PROM devices (EEPROMs) , and electrical erasable programmable array logic devices (EEPALs) , etc. high voltage is needed for programming. This high voltage, -I2v to 18v, must pass over parasitic field transistors. For example, if their individual field threshold voltage are not in excess of the programming voltage, at this operating temperatures, then leakage paths occur. As integrated circuit (IC) devices becomes smaller, this parasitic transistor breakdown voltage can be less than or equal to the programming voltage. Therefore, leakage paths are provided through these parasitic transistors that could prevent programming, disturb programmed cells, or cause parts to be non-functional because the programming voltage exceeds leakage limits. As an example, if a cell requires 14 volts at room temperature to program, it will typically require 18
volts at 125°c to program (with the Vt£ temperature coefficient of -40mv/°c) .
The way this problem has traditionally been addressed is to increase the dosage of field oxide implant of the integrated circuit. However, as the integrated circuit becomes smaller, the width of the depletion region due to the increase of the implant dosage becomes smaller. That is, in smaller devices, as more field oxide implant is provided, the field oxide implant encroaches on the source/drain junction of the IC devices. Accordingly, as the field implant region increases, the depletion region decreases. Accordingly, the gated field breakdown voltage would decrease. Therefore, known techniques for eliminating the leakage paths due to the parasitic transistors would actually decrease the gated field breakdown voltage.
Accordingly, what is needed is a method and apparatus for providing high field voltage without generating leakage paths. The system should be simple to implement and cost effective. The system should also be one that can be utilized effectively as the device sizes becomes smaller. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A method and system for providing high field threshold voltage integrated circuit device is disclosed. The method and system masks and etches a nitride layer and then provides
a field implant region in the well area. Then etches the nitride again moving the field implant region away from the source/drain region of the device.
Through this process the field implant region is spaced away from the source/drain region of the device. In so doing, the breakdown voltage of the parasitic transistors associated therewith are significantly increased.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a flow chart showing a conventional method for producing an integrated circuit.
Figure 2 is a diagram of the integrated circuit device produced in accordance with the system of Figure 1.
Figure 3 is a diagram of a portion of the integrated circuit device of Figure 1.
Figure 4 is a diagram showing the P* region and N* region of the integrated circuit device of Figure 1.
Figure 5 is a flow chart showing a method for producing an integrated circuit device in accordance with the present invention.
Figures 6A-6E are diagrams of the integrated circuit device in accordance with the present invention at various stages of its function.
DETAILED DESCRIPTION OF THE DRAWINGS
The present invention relates to an improvement in integrated circuit device with a high field threshold voltag The following description is presented to enable one ordinary skill in the art to make and use the invention provided in the context of a particular application and i requirements. Various modifications to the preferr embodiments will be readily apparent to those skilled in t art, and the generic principles defined here may be applied other embodiments. Thus, the present invention is n intended to be limited to the embodiments shown, but is to accorded the widest scope consistent with the principles a novel features disclosed herein.
Figure 1 is a flow chart for producing an integrat circuit in accordance with the prior art. Figure 2 is diagram of an integrated circuit 10 produced in accordan with the flow chart of Figure 1. Accordingly, referring Figure 2, the nitride portion 12 of IC 10 is masked and etch via steps 30 and 32 of Figure 1. Thereafter a photoresi material associated with the process is stripped, via step 3 The field implant 16 is provided via step 36. Finally, t field oxide portion 18 is provided via step 38.
In many types of integrated circuits (EPROMS, EEPROMS a EPALS) oftentimes require a high voltage (between 12 and volts) to operate. However parasitic transistors, due proximity, are created between N" source drain regions 14
the P* field implant region 16 as illustrated in Figure 3. As the IC 10 becomes smaller, the breakdown voltage of these parasitic transistors at device sizes of .0001 cm or smaller decreases. The breakdown voltage can be as low as 10 volts. If the breakdown voltage of these parasitic transistors is that low then the IC cannot be programmed because the breakdown voltage is less than the programming voltage.
The traditional approach to minimize this problem is to implant the field implant region 16 and then grow the field oxide region 18 to reduce the parasitic transistors. However, if this approach is taken, the dopant of the field implant under the field oxide will encroach on the dopant of the source/drain implant of the device causing parasitic transistors with lower breakdown voltage. Referring now to Figure 4, what is shown is a diagram showing the P* field, the field implant and N* of the source/drain field of the device. The breakdown voltage is dependent upon the amount of dopant in each field. As has been above-mentioned, the breakdown voltage utilizing conventional methods is decreased as the device becomes smaller because of the P* field of the field oxide region and N* field of the source/drain region of the device are closer together.
The present invention provides a system and method pulling the field implant away from the source drain region of the device by a photo resist ablation technique. Accordingly,
the depletion region of the field implant is effectivel pulled away thereby increasing the parasitic transistor associated with the highly doped areas. To more particularl describe the operation of the present invention, refer now t Figure 5 and Figures 6A-6E. Figure 5 shows a flow chart of method for producing a integrated circuit with a high fiel threshold voltage in accordance with the present invention Figure 6A-6E are diagrams showing the formation of a integrated circuit in accordance with the present inventio that correspond to the flow chart of Figure 5.
Accordingly, referring to Figure 5, the N* nitrid portion 101 of IC 100 is masked and etched via steps 202 an 204. In this process, the p-well source/drain mask region 10 is oversized by about 0.0005mm/side (Figure 6A) . Then, th field implant is provided via step 206 (Figure 6B) . In preferred embodiment a N* nitride photoresist 104 is left o during field implant. Next, the N* nitride photoresist 104 o the IC 100 is ablated back (for example, about 0.0005mm/side shown at 103, preferably in an oxygen atmosphere via step 208 After the N* nitride photoresist 104 has been ablated, th exposed N* nitride layer 101 is etched, via step 210 (Figur 6C) . Next, the N* nitride photoresist 104 is removed via ste 212. Then the P* nitride layer portion 101' is masked an etched via step 214 and 216, respectively (Figure 6D) . The the P* nitride photoresist 105' is removed via step 218 Thereafter the field oxide 110 is provided via step 22
(Figure 6E) .
The above process effectively pulls the doping away from the source/drain junction. In an preferred embodiment, two source/drain masks are used, an N* source/drain mask (N* junctions) and a P* source/drain mask (P* junctions) .
Through the present invention, a resist pull back technique is provided that increases the breakdown voltage characteristic of the parasitic transistors formed in the integrated circuit device by etching the field implant regions back away from the source/drain region of the integrated circuit device.
Accordingly, through the use of the present invention, as integrated circuits become smaller, higher breakdown voltages on such devices can be maintained. This present invention has been described in terms of EPALs, EPROM and EEPROM's. One of ordinary skill in the art will readily recognize that many devices can utilize the above-identified method and that user would be within the spirit and scope of the present invention. Accordingly, the key feature of such a device or family of devices is that the need to be programmed at a certain voltage level for their effective operation.
Although the present invention has been described in accordance with the embodiments shown in the figures, one of ordinary skill in the art recognizes there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many
modifications may be made by one of ordinary skill in the ar without departing from the spirit and scope of presen invention, the scope of which is defined by the appende claims.
Claims
1. A method for providing a high field threshold voltage integrated circuit device, the integrated circuit including a well region, a source/drain region and a N* nitride layer and a P* nitride layer, a first oxide layer coupled to the well region, the method comprising the steps of: a) providing a field implant region in the well area; b) moving the field implant region away from the source/drain region; c) etching one of the N* and P* nitride layers; d) masking the other of P* and N* nitride layer; e) etching the other of N* and P* nitride layers; and f) growing the first oxide layer.
2. The method of claim 1 in which the well region comprises a p-well region.
3. The method of claim 1 in which the well region comprises a n-well region.
4. The method of claim 1 in which the one of the N* and P* nitride layers comprises the N* nitride layer.
5. The method of claim 4 in which the other of the N* and P* nitride layers comprises the P* nitride layer.
6. The method of claim 5 in which field implant region moving step (b) further comprises ablating a N* nitride resist region.
7. The method of claim 6 in which the field implant region moving step (b) further comprises ablating the N+ nitride resist region in an oxygen atmosphere.
8. A system for providing a high field threshold voltag integrated circuit device, the integrated circuit including well region, a source/drain region and a N* nitride layer an a P* nitride layer, a first oxide layer coupled to the well region, the system comprising: means for providing a field implant region in the wel area; means responsive to the field implant region for movin the field implant region away from the source/drain region; first means responsive to the field implant region for etching one of the N* and P* nitride layers; means responsive to the first means for masking the other of P* and N* nitride layer; second means responsive to the masking means etching the other of N* and P* nitride layers; and means responsive to the second means for growing the first oxide layer.
9. The system of claim 8 in which the well region comprises a p-well region.
10. The system of claim 8 in which the well region comprises a n-well region.
11. The system of claim 8 in which the one of the N* and P* nitride layers comprises the N* nitride layer.
12. The system of claim 11 in which the other of the N* and P* nitride layers comprises the P* nitride layer.
13. The system of claim 8 in which field implant region moving means further comprises means for ablating a N* nitride resist region.
14. The method of claim 13 in which the field implant region moving means further comprises means for ablating the N* nitride resist region in an oxygen atmosphere.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US34508994A | 1994-11-28 | 1994-11-28 | |
| US08/345,089 | 1994-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1996017380A1 true WO1996017380A1 (en) | 1996-06-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1995/014447 WO1996017380A1 (en) | 1994-11-28 | 1995-10-18 | A method and system for providing an integrated circuit device that allows for a high field threshold voltage utilizing resist pullback of the field implant region |
Country Status (2)
| Country | Link |
|---|---|
| TW (1) | TW301027B (en) |
| WO (1) | WO1996017380A1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57202754A (en) * | 1981-06-09 | 1982-12-11 | Nec Corp | Manufacture of semiconductor device |
| US4412375A (en) * | 1982-06-10 | 1983-11-01 | Intel Corporation | Method for fabricating CMOS devices with guardband |
| US4657602A (en) * | 1980-11-06 | 1987-04-14 | Burroughs Corporation | Integrated complementary transistor circuit at an intermediate stage of manufacturing |
| EP0275508A1 (en) * | 1986-12-23 | 1988-07-27 | SGS MICROELETTRONICA S.p.A. | Method for making CMOS devices |
| US4829019A (en) * | 1987-05-12 | 1989-05-09 | Texas Instruments Incorporated | Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment |
-
1995
- 1995-07-29 TW TW84107889A patent/TW301027B/zh active
- 1995-10-18 WO PCT/US1995/014447 patent/WO1996017380A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4657602A (en) * | 1980-11-06 | 1987-04-14 | Burroughs Corporation | Integrated complementary transistor circuit at an intermediate stage of manufacturing |
| JPS57202754A (en) * | 1981-06-09 | 1982-12-11 | Nec Corp | Manufacture of semiconductor device |
| US4412375A (en) * | 1982-06-10 | 1983-11-01 | Intel Corporation | Method for fabricating CMOS devices with guardband |
| EP0275508A1 (en) * | 1986-12-23 | 1988-07-27 | SGS MICROELETTRONICA S.p.A. | Method for making CMOS devices |
| US4829019A (en) * | 1987-05-12 | 1989-05-09 | Texas Instruments Incorporated | Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment |
Non-Patent Citations (1)
| Title |
|---|
| PATENT ABSTRACTS OF JAPAN vol. 7, no. 52 (E - 162)<1197> 2 March 1983 (1983-03-02) * |
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| Publication number | Publication date |
|---|---|
| TW301027B (en) | 1997-03-21 |
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