WO1996017301A1

WO1996017301A1 - Multiple bus standards interface

Info

Publication number: WO1996017301A1
Application number: PCT/GB1995/002779
Authority: WO
Inventors: Dennis Arthur Fielder; James Henry Derbyshire; Peter Bruce Gillingham; Cormac Michael O'connell; Randall Robert Torrance
Original assignee: Accelerix Limited
Priority date: 1994-11-29
Filing date: 1995-11-29
Publication date: 1996-06-06
Also published as: GB9424104D0

Abstract

An interface and method are provided for enabling the interconnection of devices within a computer designed to communicate using different standards. A bus is provided to which the devices can be attached and which is configured such that devices according to one standard do not react to signals according to other standards appearing on the bus.

Description

MULTIPLE BUS STANDARDS INTERFACE

The present invention relates to computer architecture, that is how different devices within a computer are connected together and interact.

As is well known a typical computer comprises a number of devices having different functions, such as data processing, data storage, data input and output and graphics display. Such devices are required to communicate with each other to enable the operation of the computer, and data busses are provided for this purpose. There are a number of bus configuration standards.

Within an overall system there are typically a number of sub-systems, such as a graphics sub-system, comprising a collection of devices associated with a particular operation. A typical graphics sub-system includes a display memory, a graphics controller and a Basic Input/Output System (BIOS) EPROM. In known systems the main system bus may be a Peripheral Component Interconnect (PCI) bus (although other system bus standards include VESA Local Bus, Nubus and VME Bus) and while some components of the sub-system may be configured to use a PCI Bus, other components may use the BIOS configuration or the Industry Standard Architecture (ISA) configuration.

To enable communication between such devices in a graphics sub-system it is thus known to provide a single device, typically the graphics controller, with a number of sets of pins each configured for attachment to a different type of bus. Alternatively, or in addition, separate interface devices can be provided to enable communication between different standards.

The former of the above mentioned approaches has disadvantages in terms of the necessity of providing a considerable number of pins on a single device. This increases the cost of the device and, importantly in the context of modern computers, limits the miniturisation of the device which can be achieved because the device must be large enough to provide all of the required pins sufficiently spaced apart to be practically useful. The latter above approach increases the size and cost of the overall sub-system which would preferably be avoided.

The present invention provides an interface for connection between a computer system bus and a sub¬ system, the interface comprising means providing a secondary bus to which a plurality of devices forming the sub-system may be connected; wherein the secondary bus is configured to permit the attachment of devices designed according to a plurality of different standards and, when signals according to one of said standards are being applied to the bus, to cause devices designed to another of said standards not to operate.

The present invention also provides a method of inter-connecting devices within a computer comprising providing a bus to which devices designed according to a plurality of communications standards may be attached, and configuring said bus such that when signals according to one of said standards are being applied to the bus, devices designed to another of said standards do not operate.

Although, as discussed above, this invention has particular applicability to graphics sub-systems it is also applicable to any system in which a number of devices operating according to different bus standards are required to communicate with a central device or each other.

The sub-system can comprise a number of different devices and the device acts to present only a limited load to the system bus. The signals on the secondary or Interchip bus are managed such that devices within the sub-system can be connected to the Interchip bus and operate as normal even though these devices may be designed to work with different bus standards.

The particular bus management system which is implemented can vary depending on which bus systems the devices connected to the Interchip bus are designed to use. However in principle the Interchip bus is managed such that when signals according to one bus standard are being put on to the Interchip bus, devices which operate according to other bus standards do not try to act on the data and this can be achieved by a consideration of which lines or logical combination of lines enable or disable activity in a particular bus standard.

This invention has particular application to computer graphics display systems which systems may comprise a number of components, one of which is the graphics controller/display memory. In a graphics sub¬ system the device of the invention may be formed integrally with the graphics controller, in which case the controller only requires one set of pins, defining the secondary bus, for connection to the other graphics devices, in place of the plurality mentioned above.

The interface device provides an Interchip bus as described above to which the various components of the graphics sub-system can be connected irrespective of the bus systems for which they are designed. A particular advantage of this arrangement is that it facilitates the addition of further devices including further display memory and controllers as these can be simply added to the Interchip bus.

Preferably the invention provides a single device which comprises the host bus interface as described above, the graphics controller and the display memory. Thus when multiple ones of these units are used to improve the resolution and colour depth of a display, the performance of the display is not slowed because each addition of display memory is matched by a corresponding addition of controller capability.

In order that the present invention may be better understood, together with additional features and advantages, preferred embodiments will now be described by way of example with reference to the accompanying drawings in which:

Figure 1 illustrates a conventional approach to the provision of a graphics sub-system within a computer;

Figure 2 illustrates a preferred embodiment of this invention; and

Figure 3 illustrates a further embodiment of this invention.

The essential idea of this invention is to solve problems encountered in providing a sub-system of devices which need to be connected to a buffered bus while being designed to different bus standards. Further the invention addresses problems encountered in attaching additional memory to single chip graphics systems.

Before describing the embodiments of the invention in detail a typical graphics sub-system is described in the following to assist understanding of the invention.

Typically a computer graphics systems comprises firstly a display memory. This memory has stored in it information which reflects what is desired to be displayed on a screen. The information in the memory is repeatedly read from the memory and applied to the screen. When the computer CPU wishes to alter the display on the screen it modifies the display memory contents, which modifications are subsequently reflected in the displayed image on the screen. Thus the second part of a typical computer graphics system is the controller which interfaces with the CPU, allows the CPU to modify the display memory contents and reads the display memory repeatedly to refresh the display screen as mentioned above. The quality of the displayed image and its performance are affected by the attributes both of the display memory itself and of the controller.

Computer graphics displays have three parameters which summarise their performance, namely horizontal resolution, vertical resolution, and colour depth. The horizontal and vertical resolutions are simply defined as the number of pixels which are placed on the screen in the corresponding directions. The total number of pixels is the product of these two numbers.

The colour depth is more complex, dividing mainly into two different techniques, called the direct colour method, and the look-up table (or palette) method. The colour seen on the screen for a particular pixel is the result of displaying varying levels of red, green and blue primary colours. To obtain a good appearance for slowly varying colours and intensities it is necessary to represent each of the three primary colours by a selection from at least 256 different levels which can be represented by an 8 bit binary value.

In the direct colour method each pixel is stored in the computer display memory directly in terms of the red, green and blue values needed. This means that each pixel requires storing 3 x 8, or 24 bits of information. Each pixel on the screen can be set to a colour independent of any other pixel so giving maximum quality of the final picture.

In the palette method, a limited selection of possible colours to display is made and stored in a small look-up table in addition to the display memory. The look-up table input is the entry number for the wanted colour. The look-up table output is the red, green and blue values needed to display the wanted colour, so will typically have three 8 bit values. For each pixel on the screen it is now sufficient to store in the display memory only the entry number in the palette of the required colour. A typical computer display will have a palette of 256 different colours, so requiring a entry number in the range 0 to 255, which can be stored in 8 bits of memory. The limitation of this approach is that only 256 colours can be visible on the screen simultaneously, so limiting the quality of the final picture.

Minimising the amount of data storage used to represent the entire screen in this way has a number of advantages. The smaller memory requirements (1/3 the size) leads to lower cost. The memory need only provide data at 1/3 of the rate for a given screen refresh rate, again lowering the cost. Finally, when the display picture needs modifying only 1/3 of the amount of memory needs altering, leading to a faster acting system.

A compromise is allowed by many systems which can use the direct colour approach, but with only 16 bits stored in the display memory for each pixel. The bits are divided between the red, green and blue values in the proportions 5:5:5 (with 1 unused), 5:6:5 or 5:5:6 depending on the individual system. These systems can display pictures of a compromise quality with a corresponding compromise speed of action of the system. The capability of many present systems is to allow the user to select the type of operation they wish to have, selecting from high resolution 8 bit palette fast acting mode, medium resolution 16 bit direct colour mode, or low resolution slow acting 24 bit direct colour mode.

As mentioned above many systems have the graphic system split into two main parts, the controller and the display memory itself. While the display memory is provided as a separate entity, it is possible to vary the amount of memory easily to product systems of varying capabilities at correspondingly varying cost. The addition of extra memory permits the user to select either higher resolution of larger colour depth. Whichever parameter is improved a disadvantage is that the system acts slower since the additional memory needs modifying to change the display picture, and this is done by the controller which has not been changed.

The increasing capabilities of modern silicon integrated circuit production lead to putting larger systems into single devices, with the natural progression in the graphics system design leading to incorporating the display memory and the controller within a single device, obtaining lower system cost and improved performance as a result. The disadvantage of this approach is the loss of flexibility, since additional memory is more to difficult to attach.

The following description of various arrangements is in terms of single chip graphics devices indicated in the figures by reference numeral 1. These devices incorporate display memory in the -form of dynamic random access memory (DRAM) and a display controller. These are indicated generally by reference numeral 2. Reference numeral 3 indicates digital-to- analog converters which provide the outputs from the graphics device which outputs are applied to the display screen.

A conventional approach is shown in Figure 1, where for instance a PCI to PCI Bridge device 10 is needed to ensure that a single load is presented to the main host PCI bus 12 and a second PCI to Industry Standard Architecture (ISA) Bridge 14 is needed to interface to other devices on the same graphics system. A set of pins 16 (the BIOS port) is conventionally put onto the graphics device 1 to allow the attachment of the Basic Input/Output System (BIOS) EPROM 17, a device which is required for all graphics systems built as a plug-in adaptor board. The need for additional devices is removed if the PCI to PCI Bridge and the PCI to ISA Bridge are incorporated into the graphics controller. This would normally require an increase in the number of pins, since the graphics device would now require three ports, one for each of the BIOS EPROM device, PCI type devices and ISA type devices.

Figure 2 illustrates the present invention providing a single bus, the Interchip bus 20 which has the BIOS EPROM and other PCI and ISA bus devices attached to it. By using a single set of pins to perform these functions an advantage in package pin count is realised.

Management of the Interchip bus 20 is provided by the PCI interface and Bridge 22 which in addition provides the single link to the PCI host bus 12. The Interchip bus management is described in detail in the following.

In order to share a single set of pins for the multiple bus types, it is required that each- evice attached to the bus respond only to the bus activity intended for that type of device. This requires determining a configuration such that activity undertaken for one bus type cannot appear to be activity other than idle for another bus type.

In the case of combining a simple ISA type bus with a PCI type bus, the following technique can be used. A PCI bus has two fundamental control signals, FRAME# and IRDY#, which are driven in various combinations to indicate the start and end of the bus cycles. During the period when FRAME# and IRDY# are both high the PCI bus is idle and most other signals are ignored, in particular the Command/Byte Enables (C.BE#) and the Address/Data (AD) signals. During these idle intervals these can be used to carry other information and other bus type activity.

For ISA type busses no single signal or pair of signals indicates an idle bus, instead the four signals MEMRD, MEMWR, IORD and IOWR go active individually to indicate the type of bus cycle be performed. In addition devices intended to attach to ISA type busses usually have a chip select signal, commonly called CS, which controls whether the device responds to the other control signals. By ensuring that CS is inactive, the activity on the other control signals will not cause the ISA bus type device to respond. If the device does not have a chip select pin then the four read/write control signals need to be gated by the chip select signal.

There is no signal in the PCI bus that remains inactive during all PCI bus cycles since this signal would be redundant. The CS control signal can be derived from a combination of the others, such as FRAME# and IRDY# both being inactive, or it can be generated and provided on a separate pin from the device for simplicity of the external logic.

Table 1 shows one possible way of assigning the signals required for each bus type to the common set of pins available. Many trade-offs between, for instance, the number of pins assigned to data and to address for ISA type busses are can be made, the assignment shown is only one example. The example shows only the minimum set of signals required to enable devices to attach to the ISA type bus, it again is possible to provide a more complete set of ISA signals should higher levels of compatibility be needed.

The provision of a bus, the Interchip bus, in the present invention facilitates an improvement of the graphics capability of the system by the simple addition to the bus of further graphics chips 1 as illustrated in Figure 3. This produces equivalent benefits for this single device graphics system as those obtained by attaching additional memory to standard multi-device graphics controllers as described above. The apparent disadvantage that the control logic is repeated within the new devices, and therefore has additional cost penalty, is in fact an advantage in that the three devices can now function in parallel to achieve the modifications to the display memory contents needed to modify the screen. Conventional systems slow down by a factor of three when required to work in 24 bit per pixel mode as against 8 bit per pixel mode, since the same hardware has to modify three times as much memory. The triple device approach of this embodiment does not slow down in this way. An additional advantage is that the single device can be optimised to transfer data from the memory at the speed required to maintain the 8 bits per pixel picture on the display. When 24 bits per pixel are required again the three devices work in parallel to fetch the information from the three memory arrays, each still at the original rate.

When the host bus is used to transfer data to or from th_**- graphics system, it is the function of the combined PCI interface and Bridge to make the three devices appear as a single entity. As an example, if the host machine writes a 24 bit (3 byte) value to the graphics system representing a red, green and blue triplet of values, the two of the values will be transferred across the Interchip bus to the additional two devices without requiring further host machine activity.

Claims

_!_____ :

1. An interface for connection between a computer system bus and a sub-system, the interface comprising means providing a secondary bus to which a plurality of devices forming the sub-system may be connected; wherein the secondary bus is configured to permit the attachment of devices designed according to a plurality of different standards and, when signals according to one of said standards are being applied to the bus, to cause devices designed to another of said standards not to operate.

2. An interface device according to Claim 1 in which the secondary bus permits the attachment of devices according to the PCI, ISA and BIOS standards.

3. An interface device according to Claim 1 or 2 configured such that when activity according to one of said standards is present on said secondary bus, the secondary bus appears idle to devices designed according to the or each other of said plurality of standards.

4. A computer graphics device comprising an interface device according to Claim 1, 2 or 3 and a graphics memory device connected, internally to the computer graphics device, to the secondary bus.

5. A computer graphics system comprising a plurality of devices according to Claim 4, one of the plurality being arranged to be connected to a computer system bus and the or each other of said plurality being connected to the secondary bus of said one of the plurality.

6. A computer graphics system according to Claim 5 in which other devices are connected to the secondary bus .

7. A method of inter-connecting devices within a computer comprising providing a bus to which devices designed according to a plurality of communications standards may be attached, and configuring said bus such that when signals according to one of said standards are being applied to the bus, devices designed to another of said standards do not operate.

8. A method according to Claim 7 comprising configuring the bus such that when activity according to one of said standards is present on the bus, the bus appears idle to devices designed according to the or each other of said plurality of standards.