JPH05189550A - Image processor - Google Patents

Abstract

PURPOSE:To reduce the burden of software by allocating the same addresses to plural image processors and therefore preventing a host device from being conscious of any specific image processor to which the processor should have an access. CONSTITUTION:Each frame memory FM 5 consists of (m) pieces of planes in all. These memories FM 5 are processed in parallel by (n) pieces of image processors 4, and each processor 4 can control (k) pieces of planes at the most. In this case, (k), (m) and (n) are set at an integer respectively (m<=kXn). Then (n) pieces of processors 4 are connected to a common system bus 3 and also allocated to the same addresses. Furthermore the unique ID information is set to each processor 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic system having a frame memory (hereinafter referred to as "FM") for storing image data of a graphic screen and a processor for controlling the FM.

[0002]

2. Description of the Related Art In this type of graphic system, the number of FM planes is increased in order to increase the number of colors that can be displayed, the type of density, the type of attribute, etc. , And if the display control is processed by one image processing processor, the processing speed decreases.
Therefore, by connecting a plurality of image processors and operating them in synchronization to increase the number of pixels that can access the FM at one time, the speed has been increased.

[0003]

In the conventional graphics system, when a plurality of image processors are connected as described above, each image processor is assigned to a different address on the bus. Therefore, there is a drawback that it is necessary to create software in consideration of which image processing processor is to be accessed depending on the type of image processing, the data format, and the size.

It is an object of the present invention to allocate a plurality of image processing processors to the same address so that it is not necessary to be aware of which image processing processor is to be accessed, and the load of software is reduced.

[0005]

In order to achieve the above object, in the graphic system of the present invention, information (hereinafter referred to as "ID information") indicating which plane the FM is controlled by the image processor itself. A function of knowing and a function of determining which bit of the data on the system bus the image processing processor should control based on the ID information and a command given from another device on the system bus. An image processor having a function of inputting / outputting only a relevant bit of the data on the system bus based on the determination,
Connect to the same address on the system bus as many as the number of planes.

[0006]

As an example, consider a case where data transfer is performed from another device (referred to as a bus master here) connected to the system bus to the FM for each of the graphic systems having the 8-plane configuration and the 24-plane configuration.

First, when the bus master issues a data transfer command to the image processor and then sends image data in the packed pixel format onto the bus, each of the plurality of image processors performs FM control of which plane it is. Whether or not it is in charge is judged from the ID information and only the necessary bits of the data on the bus are read.

Here, if each image processor handles 4 planes, in the 8 plane configuration,
The data read by each image processor is shown in FIG.
It has a comb shape as shown in “packed pixel format data” of (b). On the other hand, even in the 24-plane configuration, as shown in FIG. 7, each image processing processor selects data to be read. By doing so, the bus master can access the FM at high speed without being aware of which plane's FM is accessed.

[0009]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a configuration diagram of a graphic system in which a frame memory having a plurality of planes is controlled by n FM (frame memory) control processors.

0 is a higher-level device, 1 is a central control unit (hereinafter C
PU) 2, main memory, 3 system bus, 31 system bus data section, 32 system bus address and control signal section, 4 image processor connected to system bus 3, 5 image processor A frame memory composed of n planes corresponding to 4, a parallel / serial conversion unit 6 for performing parallel / serial conversion of image data stored in the frame memory 5, and a CRT 7. F
M5 has a format in which data of one pixel is decomposed and handled for each plane. This is called plain format. here,
Each plane does not necessarily have a one-to-one physical correspondence with the FM5. An example is shown in FIG. Reference numeral 10 is one frame memory. Half of each of the two FMs 10 is assigned to plane 1 and plane 2, and
Are arranged to represent the plane 1 and the plane 2.

In the present system, the FM 5 consisting of a total of m planes is processed in parallel by n image processing processors 4 each controlling a maximum of k planes. Where k,
m and n are integers, and the relationship of m ≦ k × n is established.
The n image processors 4 share the common system bus 3
, And all image processors 4 are assigned to the same address. On the other hand, the i parallel / serial conversion units 6 process the image data in units of j planes and send them to the CRT. Here, i and j are integers, and m =
The relationship of j × i holds.

In the following, as an example, an 8-plane configuration (m =
8) and a graphic system having a 24-plane structure (m = 24) will be described. Here, if each image processor 4 handles four planes (k = 4), two image processors 4 as shown in FIG.
(N = 2) enables an 8-plane configuration, and as shown in FIG. 3, 6 image processors 4 (n = 6) enable a 24-plane configuration. 2 and 3, the parallel / serial conversion unit 6 is configured by the same unit that processes image data in units of 8 planes (j = 8). RAMDAC8 is for 8 planes in FIG.
Will be for 24 planes.

Each image processor 4 uses, as ID information, the total number of planes and the F of the planes it controls.
You can know M5. The following method is an example of a method for each image processing processor 4 to acquire this ID information.

The first method is to fix the ID number of each image processor 4 in terms of hardware and read the data from the LSI pin of the image processor 4. This method is very simple and does not impose a load on software, but the number (n) of image processing processors 4 that can be connected and the controllable plane are provided by the number of LSI pins prepared for reading ID information. Is limited in number (m).

The second method is a method in which the image processor 4 is provided with an ID information setting register, an ID setting flag, and an LSI pin for transmitting the flag to make a daisy chain connection. When the image processor 4 is reset, the ID setting flag is also reset. Then, the ID setting flag of the image processing processor 4 which is connected one level higher than the self image processing processor 4 in the daisy chain is set, and the ID setting flag of the self image processing processor 4 is reset. If the ID information setting register of the image processor 4 is accessed, the ID information can be set. With such a mechanism, at the time of initial setting, the ID information setting register is set in order from the image processor 4 connected to the upper level of the daisy chain, and the ID setting flag is set. The ID information of the image processor 4 can be uniquely set.

Regarding the representation method of ID information, for example, I
If the D information is represented by a two-digit number, the first digit indicates the plane controlled by itself, and the second digit indicates the total number of planes.
3 to FM5, and if ID = 31, the FM5 of planes 4 to 7 of 24 planes is controlled.

By setting the ID information in this way, the host device 0 can execute the same processing in parallel by an arbitrary number of image processing processors 4 by sending a command once. Each image processor 4
The same processing is performed on the data of the plane controlled by each person, and the result is output to the FM 5 controlled by each person or to an appropriate bit position on the system bus 3.

Further, by utilizing the ID information uniquely set in each image processor 4, a part of the image processors 4 can be selected to execute the processing.

Next, the internal representation of data will be considered by taking a 24-plane structure as an example. Increase the number of planes to 2
With 4 planes, the number of simultaneous colors is 16,777,21.
It is possible to expand up to 6 colors (full color). Here, the color palette (R
The function of the AMDAC8) may be used, but the color palette is originally intended to prepare the number of colors that can be developed, even if the number of simultaneous colors is small, and thus can be eliminated.
In that case, as shown in FIG. 4, a circuit configuration is conceivable in which the image processor 4 and the FM 5 are combined for every 8 planes and output independently for R / G / B. An inexpensive 8-plane DAC instead of the 24-plane compatible RAMDAC 8 of FIG.
The graphics system can be configured with 9. Since the graphic system according to the present invention does not depend on the internal representation of data, such a configuration can be realized.

[0020]

Since the graphic system according to the present invention is configured as described above, it has the following effects.

(1) Since the image processor of the present invention has a function of acquiring its own ID information and operating based on the information, a plurality of image processors can be assigned to the same address on the same bus. it can.

(2) Since a plurality of image processing processors can be assigned to the same bus, all the image processing processors can be started by sending the command once when starting the image processing processors from other devices. can do.

(3) Each image processor determines which plane's frame memory is controlled based on the ID information and processes only the required bits of packed pixel data. Therefore, the data is combined / divided on the system bus. can do. Therefore, there is no need to perform the composition / division processing by software.

As described above, the speeding up of image processing can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a graphics system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a graphic system having an 8-plane structure.

FIG. 3 is a block diagram of a graphics system having a 24-plane structure.

FIG. 4 is a block diagram of another 24-plane graphic system.

FIG. 5 is an explanatory diagram of a relationship between an FM and a plane.

FIG. 6 is an explanatory diagram of a data format having an 8-plane structure.

FIG. 7 is an explanatory diagram of a 24-plane data format.

[Explanation of symbols]

1 ... CPU, 2 ... Main memory, 3 ... System bus, 4 ... Image processor, 5 ... Frame memory composed of a plurality of planes, 6 ... Parallel / serial conversion unit, 7 ... CRT, 8
... RAMDAC, 9 ... DAC without pallet function.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Ken Ken Watanabe, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Hitachi Ltd. Microelectronics Device Development Laboratory (72) Inventor, Kazuo Sugai 292 Yoshida-cho, Totsuka-ku, Yokohama Hitachi, Ltd. (72) Inventor, Naoaki Shibata, 810 Shimoimaizumi, Ebina, Kanagawa, Ltd., Office Systems Design and Development Center, Hitachi, Ltd. (72) Satoshi Sato, 292, Yoshida-cho, Totsuka-ku, Yokohama Hitachi, Ltd. In the image information system (72) Inventor Katsumi Shimanouchi 292 Yoshida-cho, Totsuka-ku, Yokohama City Hitachi In the image information system

Claims (5)

[Claims] 1. In a graphics system having a frame memory for storing image data of a graphic screen and a processor for controlling the frame memory, m ≦ k × n is satisfied between integers k, m and n, and m A display memory configured by planes is provided, and n pieces of image data processing means, each of which controls up to k planes, and a host device for transmitting processing contents to the image data processing means are connected to a common bus. Image processing device. 2. The image processing apparatus according to claim 1, further comprising means for uniquely setting a plane controlled by each image data processing means. 3. The image processing apparatus according to claim 2, wherein the image data processing means execute the same processing in parallel by allocating each image data processing means to the same address on a common bus. .. 4. An image processing apparatus according to claim 3, wherein each of the plurality of image data processing means has a means for uniquely setting a plane to be controlled by the respective ones to select a part of the plurality of image data processing means for processing. 5. In claim 1, m = j × i holds between integers j, m and i, and image data stored in a display memory composed of m planes is parallelized in units of j planes. An image processing apparatus comprising: i parallel / serial conversion processing means for serial / serial conversion.