WO1996016434A1 - Process for producing mosfet gate electrodes - Google Patents

Process for producing mosfet gate electrodes Download PDF

Info

Publication number
WO1996016434A1
WO1996016434A1 PCT/DE1995/001597 DE9501597W WO9616434A1 WO 1996016434 A1 WO1996016434 A1 WO 1996016434A1 DE 9501597 W DE9501597 W DE 9501597W WO 9616434 A1 WO9616434 A1 WO 9616434A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
spacer
hard mask
gate electrode
electrode
Prior art date
Application number
PCT/DE1995/001597
Other languages
German (de)
French (fr)
Inventor
Martin Kerber
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1996016434A1 publication Critical patent/WO1996016434A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Definitions

  • the present invention relates to a method for producing gate electrodes of extremely short length in MOSFETs.
  • MOSFETs with extremely short gate lengths are interesting for scientific studies, but also for commercial applications (single semiconductors, key components in telecommunications).
  • the advantages of extremely short gate lengths are above all the small gate capacitance and the comparatively high saturation current.
  • At low operating voltages extremely short gate delay times and therefore very fast logic circuits are achieved.
  • Structures with dimensions below 100 nm are usually realized using X-ray or electron beam lithography.
  • Other processes use partial oxidation of lacquer bars or lateral etching back of hard masks made of TEOS.
  • the object of the present invention is to provide a simpler method for producing extremely short length gate electrodes for MOSFETs, in particular on SOI substrates. This object is achieved with the method having the features of claim 1. Further configurations result from the dependent claims.
  • any short gate electrodes are realized with conventional optical lithography.
  • This method is particularly advantageous if, due to a lower integration density of components, it is possible to move to a lithography below 100 nm.
  • the method according to the invention follows the first part of the conventional method for the production of MOSFETs up to the deposition of the electrode layer z. B. from polysilicon for the manufacture of the gate electrodes. This electrode layer must then be structured, which happens according to the invention in such a way that a hard mask z. B. is made of nitride so that it has a vertical flank immediately adjacent to a designated area for the gate electrode.
  • a hard mask in contrast to the method described in the IBM publication cited at the beginning, has the advantage that this mask withstands high process temperatures.
  • oxide layers can then be deposited by means of CVD (chemical vapor deposition), which are characterized by better coverage of the existing edges, greater homogeneity and less contamination by metal in front of plasma oxide layers.
  • CVD chemical vapor deposition
  • a plasma oxide is used at the earliest in connection with the production of metallizations if the requirements for conformity and purity of the oxide layers are significantly lower; the method according to the invention therefore modifies part of the overall process so advantageously that there is a substantial improvement in the end product.
  • a spacer covering the area provided for the gate electrode is produced on the flank of this hard mask.
  • this narrow spacer is then used as a mask for the etching of the gate electrode.
  • an area provided for a MOSFET is electrically insulated all around and provided with a basic doping and a dielectric layer as gate oxide.
  • This area can e.g. Example, as shown in FIG. 1, be a silicon mesa 3, the surface of which is covered with a dielectric layer 4 by oxidation. 1, this mesa 3 is part of a wear layer made of silicon (so-called body silicon layer) separated from a bulk silicon layer 1 of an SOI substrate by an insulator layer 2.
  • the area provided for the MOSFET is then covered over the entire area with the electrode layer 5, which is preferably z. B. is polysilicon covered. In order to be able to structure this electrode layer 5, a hard mask layer 6 z. B.
  • the thickness of the hard mask layer 6 applied should be at least about twice as large as the thickness of the spacer layer 7 so that the spacer is sufficiently high and its width can be reproduced sufficiently well.
  • Such a spacer surrounds the remaining portion of the hard mask layer 6 all around and therefore forms a closed curve under supervision, e.g. B. a closed polygon. If this is undesirable in circuit applications, e.g. B. if the If the gate electrode is to be produced as a straight web over the channel region of the MOSFET, the undesired portion of the spacer 8 may be B. by means of a paint mask 9 z. B. can be removed by wet chemical means.
  • the hard mask layer 6 z. B. removed by isotropic etching back.
  • the electrode layer 5 can then be anisotropically etched back until only the portion intended for the gate electrode 10 remains.
  • the result of this structuring of the electrode layer is shown in FIG.
  • the spacer 8 is then preferably removed by isotropic etching. Because of the all-round etching attack, the etching time therefore corresponds to half the spacer width. If TEOS is used for the deposition of the spacer layer, the gate oxide of the dielectric layer 4 at the edge of the gate electrode 10 is also attacked during this etching back. The small cutouts of this dielectric layer 4 below the gate electrode 10 shown in FIG. 4 can be filled again in a subsequent reoxidation.
  • Etching away the surface of the insulator layer 2 exposed here is also acceptable. If this etching back of the dielectric layer 4 and the insulator layer 2 is to be avoided, the etching step for structuring the gate electrode 10 can be carried out in such a way that a thin layer portion remains from the electrode layer 5 everywhere.
  • the method step in FIG. 3 not only the gate electrode 10 is left, but also a thin remaining layer portion of the electrode layer 5 completely covering the side of the measurement 3.
  • the spacer 8 is then removed and then the electrode layer 5 is further etched back until the portions present on the side of the gate electrode 10 are completely removed.
  • the electrode layer 5 can be applied somewhat thicker beforehand.
  • Electrode layer 5 Further portions of the electrode layer 5 that are not to be removed during the structuring can be covered by a further mask that follows the spacer layer 7 is applied before the electrode layer 5 is structured.
  • This mask can in particular be part of the mask 9 shown in FIG. 2.
  • the larger connection areas of the gate electrode can be structured as part of the electrode layer 5.
  • a conventional hard mask is suitable before the spacers are etched. If the mask is only applied immediately before the etching of the gate electrode, a conventional lacquer mask can be used.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A process for producing an extremely short gate electrode for MOSFETS in which a gate electrode layer (5) is first applied over the entire area, a nitride layer (6) is applied over the entire area and structured, a spacer (8) at the sides of the nitride layer (6) is produced by the anisotropic back-etching of an oxide layer covering the entire area, whereupon a mask (9) can be used to remove part of said spacer and then, after the removal of the nitride layer (6), said spacer (8) is used as a mask for the anisotrope structuring of the electrode layer (5) as a gate electrode.

Description

Beschreibung description
Herstellungsverfahren für Gate-Elektroden von MOSFETsManufacturing process for gate electrodes of MOSFETs
Die vorliegende Erfindung betrifft ein Verfahren zur Herstel¬ lung von Gate-Elektroden extrem kurzer Länge bei MOSFETs.The present invention relates to a method for producing gate electrodes of extremely short length in MOSFETs.
Die Realisierung von MOSFETs mit extrem kurzen Gate-Längen ist für wissenschaftliche Untersuchungen, aber auch für kom¬ merzielle Anwendungen (Einzelhalbleiter, Schlüsselkomponenten in der Telekommunikation) interessant. Die Vorteile extrem kurzer Gate-Längen sind vor allem die kleine Gate-Kapazität sowie der vergleichsweise hohe Sättigungsström. Bei niedrigen Betriebsspannungen erzielt man damit extrem kleine Gatter- Verzögerungszeiten und damit sehr schnelle logische Schaltkreise. Üblicherweise werden Strukturen mit Abmessungen unterhalb 100 nm mit Röntgen- oder Elektronenstrahllithogra- phie realisiert. Andere Verfahren verwenden teilweises Oxi- dieren von Lackstegen oder laterales Rückätzen von Hartmasken aus TEOS. Die Nachteile dieser Verfahren sind einerseits die aufwendige Technik und andererseits die gleich große Übertra¬ gung von Unregelmäßigkeit in der Begrenzung der ursprüngli¬ chen Masken auf die schmale Abmessung des Gate, so daß diese Unregelmäßigkeit relativ zur Größe der Abmessung zunehmend ins Gewicht fällt. Damit wird die minimal realisierbare Gate- Länge begrenzt. In IBM Technical Disclosure Bulletin 2&, 4587 - 4589 (1984) wird von C. Johnson e.a. ein Herstellungsver¬ fahren für kurze Gate-Elektroden angegeben, das Spacertechnik in Siθ2 verwendet.The implementation of MOSFETs with extremely short gate lengths is interesting for scientific studies, but also for commercial applications (single semiconductors, key components in telecommunications). The advantages of extremely short gate lengths are above all the small gate capacitance and the comparatively high saturation current. At low operating voltages, extremely short gate delay times and therefore very fast logic circuits are achieved. Structures with dimensions below 100 nm are usually realized using X-ray or electron beam lithography. Other processes use partial oxidation of lacquer bars or lateral etching back of hard masks made of TEOS. The disadvantages of these methods are, on the one hand, the complex technology and, on the other hand, the same size transfer of irregularity in the limitation of the original masks to the narrow dimension of the gate, so that this irregularity is of increasing importance relative to the size of the dimension. This limits the minimum feasible gate length. In IBM Technical Disclosure Bulletin 2 &, 4587-4589 (1984) by C. Johnson e.a. a manufacturing process for short gate electrodes specified that uses spacer technology in SiO 2.
Aufgabe der vorliegenden Erfindung ist es, ein einfacheres Verfahren zur Herstellung von Gate-Elektroden extrem kurzer Länge für MOSFETs insbesondere auf SOI-Substrat anzugeben. Diese Aufgabe wird mit dem Verfahren mit den Merkmalen des Anspruches 1 gelöst. Weitere Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.The object of the present invention is to provide a simpler method for producing extremely short length gate electrodes for MOSFETs, in particular on SOI substrates. This object is achieved with the method having the features of claim 1. Further configurations result from the dependent claims.
Bei dem erfindungsgemäßen Verfahren werden mit konventionel¬ ler optischer Lithographie nahezu beliebig kurze Gate-Elek¬ troden realisiert. Dieses Verfahren ist insbesondere von Vor¬ teil, wenn wegen einer geringeren Integrationsdichte von Bauelementen auf eine Lithographie unterhalb 100 nm ver- ziehtet werden kann. Das erfindungsgemäße Verfahren schließt an den ersten Teil des herkömmlichen Verfahrens zur Herstel¬ lung von MOSFETs bis zur Abscheidung der Elektrodenschicht z. B. aus Polysilizium für die Herstellung der Gate-Elektroden an. Diese Elektrodenschicht muß dann strukturiert werden, was erfindungsgemäß in der Weise geschieht, daß eine Hartmaske z. B. aus Nitrid so hergestellt wird, daß sie eine senkrechte Flanke unmittelbar neben einem für die Gate-Elektrode vorge¬ sehenen Bereich besitzt. Die Verwendung einer Hartmaske im Unterschied zu dem in der eingangs zitierten Veröffentlichung von IBM beschriebenen Verfahren hat den Vorteil, daß diese Maske hohen Prozeßtemperaturen standhält. In folgenden Ver¬ fahrensschritten können dann mittels CVD (chemical vapour de- position) Oxidschichten abgeschieden werden, die sich durch bessere Bedeckung der vorhandenen Kanten, größere Homogenität und geringere Verunreinigungen durch Metall vor Plasma-Oxid- Schichten auszeichnen. Ein Plasma-Oxid findet frühestens im Zusammenhang mit der Herstellung von Metallisierungen Anwen¬ dung, wenn die Anforderungen an Konformität und Reinheit der Oxidschichten wesentlich geringer sind; das erfindungsgemäße Verfahren modifiziert daher einen Teil des Gesamtprozesses so vorteilhaft, daß sich für das Endprodukt eine wesentliche Verbesserung ergibt. An die Herstellung der Hartmaske an¬ schließend wird ein den für die Gate-Elektrode vorgesehenen Bereich abdeckender Spacer an der Flanke dieser Hartmaske hergestellt. In einem weiteren Verfahrensschritt wird dann dieser schmale Spacer als Maske für das Ätzen der Gate-Elek¬ trode verwendet. Es folgt eine genauere Beschreibung des er- findungsgemäßen Verfahrens anhand der Figuren 1 bis 4, die Zwischenprodukte eines unter Einbeziehung des erfindungsgemä¬ ßen Verfahrens hergestellten MOSFET im Querschnitt zeigen.In the method according to the invention, almost any short gate electrodes are realized with conventional optical lithography. This method is particularly advantageous if, due to a lower integration density of components, it is possible to move to a lithography below 100 nm. The method according to the invention follows the first part of the conventional method for the production of MOSFETs up to the deposition of the electrode layer z. B. from polysilicon for the manufacture of the gate electrodes. This electrode layer must then be structured, which happens according to the invention in such a way that a hard mask z. B. is made of nitride so that it has a vertical flank immediately adjacent to a designated area for the gate electrode. The use of a hard mask, in contrast to the method described in the IBM publication cited at the beginning, has the advantage that this mask withstands high process temperatures. In the following process steps, oxide layers can then be deposited by means of CVD (chemical vapor deposition), which are characterized by better coverage of the existing edges, greater homogeneity and less contamination by metal in front of plasma oxide layers. A plasma oxide is used at the earliest in connection with the production of metallizations if the requirements for conformity and purity of the oxide layers are significantly lower; the method according to the invention therefore modifies part of the overall process so advantageously that there is a substantial improvement in the end product. Following the production of the hard mask, a spacer covering the area provided for the gate electrode is produced on the flank of this hard mask. In a further process step, this narrow spacer is then used as a mask for the etching of the gate electrode. There follows a more detailed description of the Process according to the invention with reference to FIGS. 1 to 4, which show cross-sections of intermediate products of a MOSFET produced using the process according to the invention.
In herkömmlicher Weise wird ein für einen MOSFET vorgesehener Bereich ringsum elektrisch isoliert und mit einer Grunddo¬ tierung sowie einer Dielektrikumschicht als Gate-Oxid verse¬ hen. Dieser Bereich kann z. B. wie in Figur 1 dargestellt ei¬ ne Mesa 3 aus Silizium sein, deren Oberfläche durch Oxidation mit einer Dielektrikumschicht 4 bedeckt ist. In der Dar¬ stellung der Figur 1 ist diese Mesa 3 Teil einer von einer Bulk-Siliziumschicht 1 eines SOI-Substrates durch eine Isola¬ torschicht 2 getrennten Nutzschicht aus Silizium (sogenannte Body-Siliziumschicht) . Der für den MOSFET vorgesehene Bereich wird dann ganzflächig mit der Elektrodenschicht 5, die vor¬ zugsweise z. B. Polysilizium ist, bedeckt. Um diese Elektro¬ denschicht 5 strukturieren zu können, wird zunächst eine Hartmaskenschicht 6 z. B. aus Nitrid aufgebracht und so strukturiert, daß der verbleibende Anteil dieser Hartmasken- schicht 6 eine senkrechte Flanke unmittelbar neben dem für die Gate-Elektrode vorgesehenen Bereich aufweist. In diesem Bereich wird dann ein Spacer, der den für die Gate-Elektrode vorgesehenen Bereich abdeckt, hergestellt. Das geschieht da¬ durch, daß eine Spacerschicht 7 zunächst ganzflächig abge- schieden wird. Dafür ist eine Siliziumoxidschicht, die herge¬ stellt wird durch Abscheiden einer Schicht aus TEOS (Tetraethyloxysilikat) , besonders geeignet. Diese Spacer¬ schicht 7 wird dann anisotrop rückgeätzt, so daß der in Figur 1 gestrichelt gezeichnete Spacer 8 der Figur 2 übrigbleibt. Die Dicke der aufgebrachten Hartmaskenschicht 6 sollte min¬ destens etwa doppelt so groß sein wie die Dicke der Spacer¬ schicht 7, damit der Spacer ausreichend hoch ist und damit dessen Breite ausreichend gut reproduzierbar ist. Ein derar¬ tiger Spacer umgibt den verbliebenen Anteil der Hartmasken- schicht 6 ringsum und bildet daher in Aufsicht eine ge¬ schlossene Kurve, z. B. einen geschlossenen Polygonzug. Wenn das bei Schaltungsanwendungen unerwünscht ist, z. B. wenn die Gate-Elektrode als gerader Steg über dem Kanalbereich des MOSFET hergestellt werden soll, kann der nicht erwünschte An¬ teil des Spacers 8 z. B. mittels einer Lackmaske 9 z. B. naßchemisch entfernt werden.In a conventional manner, an area provided for a MOSFET is electrically insulated all around and provided with a basic doping and a dielectric layer as gate oxide. This area can e.g. Example, as shown in FIG. 1, be a silicon mesa 3, the surface of which is covered with a dielectric layer 4 by oxidation. 1, this mesa 3 is part of a wear layer made of silicon (so-called body silicon layer) separated from a bulk silicon layer 1 of an SOI substrate by an insulator layer 2. The area provided for the MOSFET is then covered over the entire area with the electrode layer 5, which is preferably z. B. is polysilicon covered. In order to be able to structure this electrode layer 5, a hard mask layer 6 z. B. applied from nitride and structured so that the remaining portion of this hard mask layer 6 has a vertical flank immediately adjacent to the area provided for the gate electrode. A spacer covering the area provided for the gate electrode is then produced in this area. This is done by first depositing a spacer layer 7 over the entire surface. A silicon oxide layer which is produced by depositing a layer of TEOS (tetraethyloxysilicate) is particularly suitable for this. This spacer layer 7 is then anisotropically etched back, so that the spacer 8 shown in dashed lines in FIG. 1 remains in FIG. The thickness of the hard mask layer 6 applied should be at least about twice as large as the thickness of the spacer layer 7 so that the spacer is sufficiently high and its width can be reproduced sufficiently well. Such a spacer surrounds the remaining portion of the hard mask layer 6 all around and therefore forms a closed curve under supervision, e.g. B. a closed polygon. If this is undesirable in circuit applications, e.g. B. if the If the gate electrode is to be produced as a straight web over the channel region of the MOSFET, the undesired portion of the spacer 8 may be B. by means of a paint mask 9 z. B. can be removed by wet chemical means.
Danach wird die Hartmaskenschicht 6 z. B. durch isotropes Rückätzen entfernt. Unter Verwendung des Spacers 8 kann dann die Elektrodenschicht 5 anisotrop rückgeätzt werden, bis da¬ von nur der für die Gate-Elektrode 10 vorgesehene Anteil üb- rigbleibt. In Figur 3 ist das Ergebnis dieser Strukturierung der Elektrodenschicht dargestellt. Der Spacer 8 wird an¬ schließend vorzugsweise durch isotropes Ätzen entfernt. Wegen des allseitigen Ätzangriffes entspricht die Ätzdauer daher der halben Spacerbreite. Bei Verwendung von TEOS für die Ab- Scheidung der Spacerschicht wird bei diesem Rückätzen auch das Gate-Oxid der Dielektrikumschicht 4 an der Kante der Ga¬ te-Elektrode 10 angegriffen. Die in Figur 4 dargestellten kleinen Aussparungen dieser Dielektrikumschicht 4 unter der Gate-Elektrode 10 können bei einer nachfolgenden Reoxidation wieder gefüllt werden. Ein Abätzen der Oberfläche der hier freigelegten Isolatorschicht 2 ist ebenfalls akzeptabel. Soll dieses Rückätzen der Dielektrikumschicht 4 und der Isolator¬ schicht 2 vermieden werden, kann der Ätzschritt zum Struktu¬ rieren der Gate-Elektrode 10 so ausgeführt werden, daß von der Elektrodenschicht 5 überall ein dünner Schichtanteil stehenbleibt. In dem Verfahrensschritt der Figur 3 ist dann nicht nur die Gate-Elektrode 10, sondern seitlich ein die Me¬ sa 3 vollständig bedeckender dünner restlicher Schichtanteil der Elektrodenschicht 5 übrig. Der- Spacer 8 wird dann entfernt und anschließend die Elektrodenschicht 5 weiter rückgeätzt, bis die seitlich der Gate-Elektrode 10 vorhande¬ nen Anteile vollständig entfernt sind. Um in diesem Fall eine weitere Reduzierung der Abmessungen der Gate-Elektrode 10 zu kompensieren, kann die Elektrodenschicht 5 zuvor etwas dicker aufgebracht werden. Weitere Anteile der Elektrodenschicht 5, die bei der Strukturierung nicht entfernt werden sollen, können durch eine weitere Maske abgedeckt werden, die nach der Spacerschicht 7 aufgebracht wird, bevor die Struktu¬ rierung der Elektrodenschicht 5 erfolgt. Diese Maske kann insbesondere ein Teil der in Figur 2 eingezeichneten Maske 9 sein. Auf diese Weise können die größerflächigen Anschlußbe¬ reiche der Gate-Elektrode als Teil der Elektrodenschicht 5 strukturiert werden. Vor der Ätzung der Spacer ist eine kon¬ ventionelle Hartmaske geeignet. Falls die Maske erst unmit¬ telbar vor der Ätzung der Gate-Elektrode aufgebracht wird, kann eine konventionelle Lackmaske verwendet werden. Then the hard mask layer 6 z. B. removed by isotropic etching back. Using the spacer 8, the electrode layer 5 can then be anisotropically etched back until only the portion intended for the gate electrode 10 remains. The result of this structuring of the electrode layer is shown in FIG. The spacer 8 is then preferably removed by isotropic etching. Because of the all-round etching attack, the etching time therefore corresponds to half the spacer width. If TEOS is used for the deposition of the spacer layer, the gate oxide of the dielectric layer 4 at the edge of the gate electrode 10 is also attacked during this etching back. The small cutouts of this dielectric layer 4 below the gate electrode 10 shown in FIG. 4 can be filled again in a subsequent reoxidation. Etching away the surface of the insulator layer 2 exposed here is also acceptable. If this etching back of the dielectric layer 4 and the insulator layer 2 is to be avoided, the etching step for structuring the gate electrode 10 can be carried out in such a way that a thin layer portion remains from the electrode layer 5 everywhere. In the method step in FIG. 3, not only the gate electrode 10 is left, but also a thin remaining layer portion of the electrode layer 5 completely covering the side of the measurement 3. The spacer 8 is then removed and then the electrode layer 5 is further etched back until the portions present on the side of the gate electrode 10 are completely removed. In order to compensate for a further reduction in the dimensions of the gate electrode 10 in this case, the electrode layer 5 can be applied somewhat thicker beforehand. Further portions of the electrode layer 5 that are not to be removed during the structuring can be covered by a further mask that follows the spacer layer 7 is applied before the electrode layer 5 is structured. This mask can in particular be part of the mask 9 shown in FIG. 2. In this way, the larger connection areas of the gate electrode can be structured as part of the electrode layer 5. A conventional hard mask is suitable before the spacers are etched. If the mask is only applied immediately before the etching of the gate electrode, a conventional lacquer mask can be used.

Claims

Patentansprüche claims
1. Verfahren zum Herstellen von Gate-Elektroden bei MOSFETs, bei dem in einem ersten Schritt eine für eine Gate-Elektrode (10) vorgesehene Elektrodenschicht (5) aufgebracht wird, in einem zweiten Schritt eine Hartmaskenschicht (6) auf diese Elektrodenschicht (5) aufgebracht und so strukturiert wird, daß diese Hartmaskenschicht (6) eine senkrechte Flanke unmit- telbar neben einem für die Gate-Elektrode (10) vorgesehenen Bereich besitzt, in einem dritten Schritt eine für den nachfolgenden sechsten Schritt ausreichend dicke Spacerschicht (7) aufgebracht wird, in einem vierten Schritt diese Spacerschicht (7) soweit rück- geätzt wird, daß ein Anteil als Spacer (8) an dieser Flanke der Hartmaskenschicht (6) stehenbleibt, in einem fünften Schritt die Hartmaskenschicht (6) entfernt wird, in einem sechsten Schritt unter Verwendung dieses Spacers (8) als Maske die Elektrodenschicht (5) anisotrop rückgeätzt wird und in einem siebten Schritt der Spacer (8) entfernt wird.1. Method for producing gate electrodes in MOSFETs, in which an electrode layer (5) provided for a gate electrode (10) is applied in a first step, in a second step a hard mask layer (6) on this electrode layer (5) is applied and structured in such a way that this hard mask layer (6) has a vertical flank immediately next to an area provided for the gate electrode (10), in a third step a spacer layer (7) which is sufficiently thick for the subsequent sixth step is applied , in a fourth step this spacer layer (7) is etched back to such an extent that a portion of the spacer (8) remains on this flank of the hard mask layer (6), in a fifth step the hard mask layer (6) is removed, in a sixth step using this spacer (8) as a mask, the electrode layer (5) is anisotropically etched back and the spacer (8) is removed in a seventh step.
2. Verfahren nach Anspruch 1, bei dem der sechste Schritt so ausgeführt wird, daß von der Elektro¬ denschicht (5) ein in dem siebten Schritt als Ätzstopp ver¬ wendbarer dünner Schichtanteil stehenbleibt, und nach dem siebten Schritt die Elektrodenschicht (5) soweit rückgeätzt wird, daß sie in den Bereichen, in denen sie in dem sechsten Schritt rückgeätzt wurde, vollständig entfernt wird.2. The method according to claim 1, in which the sixth step is carried out in such a way that a thin layer portion which can be used in the seventh step as an etch stop remains of the electrode layer (5), and after the seventh step the electrode layer (5) so far is etched back to be completely removed in the areas where it was etched back in the sixth step.
3. Verfahren nach Anspruch 1 oder 2, bei dem in dem zweiten Schritt die Hartmaskenschicht (6) aus Nitrid hergestellt wird.3. The method of claim 1 or 2, wherein in the second step, the hard mask layer (6) is made of nitride.
4. Verfahren nach einem der Ansprüche 1 bis 3, bei dem in dem dritten Schritt die Spacerschicht (7) durch Abscheiden von TEOS (Tetraethylorthosilikat) hergestellt wird. 4. The method according to any one of claims 1 to 3, in which in the third step the spacer layer (7) is produced by depositing TEOS (tetraethyl orthosilicate).
PCT/DE1995/001597 1994-11-23 1995-11-16 Process for producing mosfet gate electrodes WO1996016434A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEP4441723.3 1994-11-23
DE19944441723 DE4441723A1 (en) 1994-11-23 1994-11-23 Manufacturing process for gate electrodes of MOSFETs

Publications (1)

Publication Number Publication Date
WO1996016434A1 true WO1996016434A1 (en) 1996-05-30

Family

ID=6533971

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1995/001597 WO1996016434A1 (en) 1994-11-23 1995-11-16 Process for producing mosfet gate electrodes

Country Status (2)

Country Link
DE (1) DE4441723A1 (en)
WO (1) WO1996016434A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528372B2 (en) * 2001-06-27 2003-03-04 Advanced Micro Devices, Inc. Sidewall spacer definition of gates

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0402296A1 (en) * 1989-06-09 1990-12-12 International Business Machines Corporation Field-effect-transistor with asymmetrical structure
US5061647A (en) * 1990-10-12 1991-10-29 Motorola, Inc. ITLDD transistor having variable work function and method for fabricating the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532698A (en) * 1984-06-22 1985-08-06 International Business Machines Corporation Method of making ultrashort FET using oblique angle metal deposition and ion implantation
JPH02253632A (en) * 1989-03-27 1990-10-12 Matsushita Electric Ind Co Ltd Manufacture of field effect transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0402296A1 (en) * 1989-06-09 1990-12-12 International Business Machines Corporation Field-effect-transistor with asymmetrical structure
US5061647A (en) * 1990-10-12 1991-10-29 Motorola, Inc. ITLDD transistor having variable work function and method for fabricating the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"LOW SERIES RESISTANCE SOURCE BY SPACER METHODS", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 33, no. 1A, 1 June 1990 (1990-06-01), pages 75 - 77, XP000120044 *
ANONYMOUS: "Method for Making Submicron Dimensions in Structures Using Sidewall Image Transfer Techniques", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 26, no. 9, February 1984 (1984-02-01), NEW YORK, US, pages 4587 - 4589, XP002000221 *

Also Published As

Publication number Publication date
DE4441723A1 (en) 1996-05-30

Similar Documents

Publication Publication Date Title
DE10101568B4 (en) Semiconductor device and method of making the same
DE2845460A1 (en) METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
DE3241895A1 (en) METHOD FOR PASSIVATING THE SURFACE OF A SEMICONDUCTOR COMPONENT
WO2003096399A1 (en) Method for producing a semiconductor component, and semiconductor component produced by the same
DE112010003143T5 (en) Semiconductor device, method for manufacturing a semiconductor device, and display device
DE102008060704A1 (en) Composite Passivation Process for Nitride Field Effect Transistors
DE10235793A1 (en) Semiconductor device and method of manufacturing the same
DE102007056741B4 (en) Field effect transistor and method for its production
DE1917995B2 (en) METHOD FOR FORMING AN INSULATING FILM AND AFTER-MANUFACTURED SEMICONDUCTOR ELEMENT
EP0026376A2 (en) Method of making integrated semiconductor circuits, particularly CCD circuits with self-aligned, non-overlapping polysilicon electrodes
EP1145286A2 (en) Method for structuring a metalliferous layer
DE112014003175B4 (en) Process for producing self-aligning insulation in gallium nitride components and integrated circuits
WO1996016434A1 (en) Process for producing mosfet gate electrodes
WO1999063582A2 (en) Method for producing semiconductor elements
DE10306310B4 (en) Dual gate oxide process without critical resist and without N2 implantation
DE19719909A1 (en) Dual damascene process for integrated circuits
DE3942657A1 (en) SEMICONDUCTOR DEVICE WITH A DIELECTRIC PROTECTIVE ELEMENT AGAINST PUNCH AND METHOD FOR THE PRODUCTION THEREOF
EP0823728B1 (en) Method of manufacturing a field effect transistor
DE19746901A1 (en) Vertical MOS transistor manufacture method for nano-electronics
DE19723330B4 (en) Process for the production of thin film transistors and thin film transistor
DE1957500B2 (en) SEMICONDUCTOR COMPONENT WITH SCHOTTKY BARRIER LAYER
EP1380047B1 (en) Method for producing a semiconductor component comprising a t-shaped contact electrode
EP0771028A2 (en) Semiconductor device with passivation structure
EP0250611B1 (en) Process for eliminating a patterned masking layer
DE19622415A1 (en) CMOS semiconductor structure and method of manufacturing the same

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase