WO1996013767A1

WO1996013767A1 - Multiprocessor device comprising a clock synchronization device

Info

Publication number: WO1996013767A1
Application number: PCT/IB1995/000809
Authority: WO
Inventors: Antonius Gerardus Joseph Seesing
Original assignee: Philips Electronics N.V.; Philips Norden Ab
Priority date: 1994-10-26
Filing date: 1995-09-28
Publication date: 1996-05-09
Also published as: JPH09507600A

Abstract

A multiprocessor device comprises a plurality of processors (p1, p2, p3, p4), which mutually synchronously execute the same activities. In such a device it is highly important that the processors (p1, p2, p3, p4) be supplied with mutually synchronized clock signals (clk1, clk2, clk3, clk4). For this purpose, the multiprocessor device according to the invention comprises a clock synchronization device (cir) which comprises a plurality of clock circuits (1, 2, 3, 4). The clock signals (clk1, clk2, clk3, clk4) generated by the clock circuits (1, 2, 3, 4) are fed back. The feedback clock signals (clk1, clk2, clk3, clk4) are applied in each clock circuit (1, 2, 3, 4) to a control signal generator means (CSGM1, CSGM2, CSGM3, CSGM4). This control signal generator means comprises at least two phase comparators (PHI12, PHI13,...,PHI43) for generating phase error signals (V12, V13,...,V34) in response to at least three feedback clock signals. The control signal generator means (CSGM1, CSGM2, CSGM3, CSGM4) further comprises a combining means (CMB1, CMB2, CMB3, CMB4) for combining the phase error signals (V12, V13,...,V34) to a control signal (V1, V2, V3, V4). Each clock circuit also includes a clock signal generator (VC01, VC02, VC03, VC04) which readjusts, as required, a clock signal (clk1, clk2, clk3, clk4) in dependence on the control signal (V1, V2, V3, V4). A clock synchronization device according to the invention is advantageous in that, as conditions dictate, even with a plurality of malfunctioning clock circuits (1, 2, 3, 4), mutually synchronized clock signals (clk1, clk2, clk3, clk4) can nevertheless be produced.

Description

MULTIPROCESSOR DEVICE COMPRISING A CLOCK SYNCHRONIZATION DEVICE

The invention relates to a multiprocessor device comprising a plurality of processors and a clock synchronization device which comprises a plurality of clock circuits which are arranged for applying mutually synchronized clock signals to the processors, which clock circuits comprise a clock signal generator and a control signal generator means for generating, in dependence on a plurality of feedback clock signals, a control signal for readjusting via the clock signal generator a clock signal to be generated. In such multiprocessor devices it is extremely important for processors to receive mutually well- synchronized clock signals. This means that the percentage of malfunctioning of the clock synchronization device may only be very low. Therefore, the clock synchronization device must have some degree of error redundance i.e. the clock synchronization device continues to operate even when specific errors occur in the clock circuits.

Such a multiprocessor device is known from the Dutch publication 8502768 laid open to public inspection (US Patent 4,839,855). The multiprocessor device described in that document comprises a plurality of processors and a clock synchronization device formed by clock circuits. Each respective clock circuit receives only the feedback clock signals generated by the other clock circuits that belong to the multiprocessor device. Based upon these feedback clock signals, a majority clock signal is determined by means of a majority finding decision. A control signal is generated based upon a phase comparison between this majority clock signal and the feedback clock signal coming from that respective clock circuit. The clock signal to be produced is readjusted, as required, in dependence on this control signal. The multiprocessor device has the property that if the plurality of clock circuits no longer functioning properly continues to be below a certain limit value, the remaining clock circuits continue to generate mutually synchronized clock signals based upon the majority clock signal. If the plurality of clock circuits no longer functioning properly exceed this limit value, no majority value can be determined any longer and no mutually synchronized clock signals will be available any longer.

It is an object of the invention to provide a multiprocessor device as defined in the opening paragraph in which, as conditions dictate, mutually synchronized clock signals continue to be available even if a large plurality of clock circuits malfunction, and in which the clock synchronization device is simple and cost-effective.

A multiprocessor device as defined in the opening paragraph is thereto characterized in that the control signal generator means comprises at least two phase comparators for generating phase error signals in response to at least three feedback clock signals, and a combining circuit for combining the phase error signals to the control signal. As a result, the clock synchronization device can still generate, dictated by conditions, mutually synchronous clock signals even with a considerable plurality of malfunctioning clock circuits. This is especially the case if clock circuits contain a "reverse" error which cancels this error. A known clock synchronization device as quoted in United States Patent 4,839,855 can no longer function in a similar situation, because it is no longer possible to determine a majority clock signal. Furthermore, the multiprocessor device according to the invention is advantageous in that the clock synchronization device does not need to include intricate circuits for performing majority calculations.

An embodiment for the multiprocessor device according to the invention is characterized in that the control signal generator means is arranged for generating the control signal in dependence on all the clock signals available in the clock synchronization device. As a result, all the clock circuits in the clock synchronization device have equal influence. This results in a very stable clock synchronization device being obtained which cannot easily be desynchronized. A further embodiment for the multiprocessor device according to the invention is characterized in that the phase comparators comprise a phase shifter for converting a feedback clock signal into a phase-shifted clock signal and an exclusive-OR gate for detecting a phase error signal based upon the phase-shifted clock signal and another feedback clock signal. The phase comparators are therefore formed by very cost-effective components known per se. Furthermore, the exclusive-OR gate has the property of producing a voltage when an input signal is lacking, which voltage lies between a high signal and a low signal. Subsequent to filtering, this voltage has exactly the same effect on the eventual control signal as the phase error signal which arises when two perfectly synchronized clock signals are applied to the phase comparator. As a result, the malfunctioning of either clock circuit, which results in the lacking of a feedback clock signal in one of the phase comparators in each of the other clock circuits does not affect the clock signals produced by these other clock circuits.

A further embodiment for the multiprocessor device according to the invention is characterized in that the combining means are formed by an adder circuit. This adder circuit performs the combining function in a simple and very cost-effective manner which is known per se.

A further embodiment for the multiprocessor device according to the invention is characterized in that the clock circuits comprise switching means for switching off the clock circuits if the control signals present in the clock circuits end up outside a specific interval. As a result, clock signals coming from malfunctioning clock circuits are no longer taken into account by the control signal generator means of other clock circuits.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

In the drawings:

Fig. 1 shows a multiprocessor device according to the invention comprising a clock synchronization device,

Fig. 2 shows a clock synchronization device in detail, Fig. 3 shows a phase comparator in detail,

Fig. 4 shows clock signals applied to the phase comparator and the output signal of the phase comparator, and

Fig. 5 shows an input/output relation of a voltage-controlled oscillator used in the clock circuits. Fig. 1 shows a multiprocessor device comprising a clock synchronization device. The multiprocessor device comprises four modules modl,mod2,mod3,mod4. The respective modules comprise a processor pl,p2,p3 and p4. The processors are arranged for functioning mutually in synchronism. Data words d written in the memories meml,mem2,mem3,mem4 by the processors are converted into symbols cl,c2,c3,c4 by encoders encl,enc2,enc3,enc4 according to an error redundancy code. When the processors read these symbols from the memories, the symbols are reconverted into the original data word d by decoders decl,dec2,dec3,dec4. If one of the modules no longer functions correctly, the remaining modules are still supplied with the correct data word d due to the error redundant properties of the code used. A multiprocessor device as shown in Fig. 1 is described in more detail in "The '(4.2) concept' fault tolerant computer" by Th. Krol, Philips Technical Review, Vol. 41, 1983/84, No. 1.

The modules modl,mod2,mod3,mod4 comprise each a clock circuit 1,2,3,4. The clock circuits together form the clock synchronization device cir. For a multiprocessor device it is highly important that the processors be supplied with mutually synchronized clock signals clkl,clk2,clk3,clk4. For this purpose, the clock signals clkl, clk2,clk3, clk4 are fed back to the clock circuits 1,2,3,4. Based upon the combination of all the feedback clock signals, each clock circuit readjusts its own clock signal.

Fig. 2 shows a clock synchronization device in detail. The clock circuits 1,2,3,4 are formed by phase-locked loops. The phase-locked loops comprise each a control signal generator means CSGM1,CSGM2,CSGM3,CSGM4 which generates a control signal V1,V2,V3,V4 based upon the combination of the feedback clock signals clkl,clk2,clk3,clk4. This control signal is fed to a clock signal generator arranged as a voltage-controlled oscillator VCOl,VCO2,VCO3,VCO4, which clock signal generator generates a clock signal (clkl,clk2,clk3,clk4). The control signal generator means of each phase-locked loop comprises a plurality of phase comparators:

PHI12,PHI13,PHI14,PHI21,PHI23,PHI24,PHI31,PHI32,PHI34,PHI41,PHI42,PHI43.Each of these phase comparators is supplied with both the feedback clock signal coming from its own phase-locked loop and a feedback signal coming from another phase-locked loop. In this manner each phase-locked loop comprises a plurality of phase comparators which is one less than the total plurality of clock circuits available in a clock synchronization device. In this manner the feedback clock signal coming from a particular phase comparator's own phase- locked loop is compared with the feedback clock signals coming from all the other phase- locked loops available in the clock synchronization device. Fig. 3 shows in detail a known phase comparator which is often used in phase-locked loops. The phase comparator comprises an exclusive-OR gate XOR. One of the clock signals clkx is applied directly to the exclusive-OR gate. The other clock signal clky is displaced in phase by 90° by a phase displacing circuit PHS before the clock signal is applied to the exclusive-OR gate, which operation results in the phase-shifted clock signal clky'. Fig. 4 shows the clock signals fed to the phase comparator, and the phase error signal coming from the phase comparator plotted against time in the case where the supplied clock signals clkx and clky are synchronous. In this case the phase error signal Vxy of the phase comparator is a square-wave signal which is high for half the period of time and low for the other half of the period of time. When the clock signals are no longer synchronous, the period of time the square-wave signal is high is unequal to the period of time the square- wave signal is low. The exclusive-OR gate furthermore has the property that it produces a voltage when an input signal is lacking, which voltage is halfway between a high signal and a low signal.

The phase comparators generate square-wave phase error signals V12,V13,V14,V21,V23,V24,V31,V32,V34,V41,V42,V43. All the phase error signals of the phase comparators available in the clock circuits are subsequently applied to combining means CMB1,CMB,CMB3,CMB4. The combining means may preferably be formed by adder circuits, but also by circuits which form average values of incoming signals. The signals V'1,V'2,V'3,V'4 generated by the combining means are a superposition of the square-wave phase error signals in the case where the combining means are formed by adder circuits. These phase error signals are applied to low-pass filters LPF1,LPF2,LPF3,LPF4, so that the control signals V1,V2,V3,V4 are obtained. The voltage-controlled oscillators VCOl,VCO2,VCO3,VCO4 produce clock signals clkl,clk2,clk3, clk4 based upon the fed control signals and having a certain frequency. Fig. 5 shows the relation between a supplied control signal Vx and the frequency f(clkx) of the signal generated by the voltage-controlled oscillator. This relation is linear, but also other voltage-controlled oscillators in which the frequency of the produced signal is an ever-increasing function of the control voltage may be used. In the case of a small control signal a clock signal is produced having a low frequency and in the case of a large control signal, a clock signal having a high frequency. The voltage-controlled oscillator has a certain control range. The oscillator cannot process a control signal smaller than the minimum voltage Vmin and neither can it process a control signal larger than a maximum voltage Vmax. When the clock synchronization device functions properly, the voltage-controlled oscillators are supplied with control signals having the value Veen and the clock circuits produce mutually synchronized clock signals having the centre frequency fcen.

Each clock circuit further includes a detector DET1,DET2,DET3,DET4 to which the control signal V1,V2,V3,V4 is applied. The detector produces a high signal as long the control signal is found in an interval in the middle of the control range of the voltage-controlled oscillator and a low signal if the control signal falls outside this interval. This signal together with the clock signal is applied to an AND circuit

AND1,AND2,AND3,AND4. This results in the fact that if the control signal is outside the interval, the clock signal is not fed back to other clock circuits. For that matter, it is highly probable that a clock circuit whose control signal lies outside the interval no longer functions properly. To avoid that this deteriorates the clock signals produced by odier clock circuits, the respective clock circuit is switched off in the manner shown and is thus disregarded.

The invention is not restricted to the embodiment of the clock synchronization device as shown in Fig. 2. It is alternatively possible to supply the phase error signals produced by the phase comparators first to low-pass filters and then combine them. Furthermore, the plurality of clock circuits may be chosen at random. Neither is it necessary for all the clock signals to be fed back to each clock circuit. Also a clock synchronization device in which only part of the clock signals is fed back to each clock circuit has good synchronizing properties.

In the following there will be discussed what sort of situations may occur at the output of a clock circuit due to an error in this clock circuit and what effect these situations on the output of the clock circuit have on the rest of the clock synchronization device:

Short-circuiting of the output of a clock circuit to one of the supply voltages. This error leads to the fact that the phase comparators in the other clock circuits to which the output of this clock circuit is fed back produces a voltage due to the lacking of an input signal, which voltage has a value midway between a low signal and a high signal. After filtering, this voltage has exactly the same effect on the eventual control signal as the phase error signal that arises when two perfectly synchronized clock signals are fed to the phase comparator. This means that such a short-circuit on the output of a clock circuit has no effect on other clock circuits.

A clock circuit produces the maximum or minimum frequency belonging to the control range of the voltage-controlled oscillator. Such an error will cause the phase of the clock signals produced by the other clock circuits to shift. The other clock signals continue to be mutually synchronous. Apart from this, such an error may be avoided affecting the clock signals of other clock circuits in that the clock circuit is turned off if the control signal in the clock circuit falls outside a specific interval.

A clock circuit produces a clock signal having a frequency that lies far outside the range of a properly functioning voltage-controlled oscillator. Such a clock signal results in phase error signals in the other clock circuits having frequency components which fall outside the passband of the low-pass filter. These frequency components are thus eliminated by the low-pass filters. So, such an error does not affect the clock signals coming from other clock circuits.

A clock circuit produces a clock signal having a frequency that lies within the range of the voltage-controlled oscillator, but which frequency is uncorrelated with the frequencies of the feedback clock signals fed to the clock circuit. This causes the other clock circuits to produce clock signals following the erroneous clock signal. As a result, the clock signals continue to be mutually synchronous and this situation does not lead to any problems.

A clock circuit has a so-termed "soft output", that is to say, that other clock circuits to which the output is fed back will interpret the output signal the same. The consequences of this for the clock signals coming from other clock circuits are unpredictable. Such an error hardly ever occurs.

It appears that the faults most frequently found in a clock circuit do not affect the clock signals generated by the other clock circuits.

Claims

CLAIMS:

1. Multiprocessor device comprising a plurality of processors (pl ,p2,p3,p4) and a clock synchronization device (cir) which comprises a plurality of clock circuits (1,2,3,4) which are arranged for applying mutually synchronized clock signals (c-kl,clk2,clk3,clk4) to the processors (pl,p2,p3,p4), which clock circuits (1,2,3,4) comprise a clock signal generator (VCOl,VCO2,VCO3,VCO4) and a control signal generator means (CSGM1,CSGM2,CSGM3,CSGM4) for generating, in dependence on a plurality of feedback clock signals, a control signal (V1,V2,V3,V4) for readjusting via the clock signal generator (VCOl,VCO2,VCO3,VCO4) a clock signal to be generated, characterized in that the control signal generator means (CSGM1,CSGM2,CSGM3,CSGM4) comprises at least two phase comparators (PHI12,PHI13,...,PHI43) for generating phase error signals (V12,V13,... ,V43) in response to at least three feedback clock signals, and a combining circuit (CMB1 ,CMB2,CMB3,CMB4) for combining the phase error signals (V12,V13,...,V43) to the control signal (V1,V2,V3,V4).

2. Multiprocessor device as claimed in Claim 1 , characterized in that the control signal generator means (CSGM1,CSGM2,CSGM3,CSGM4) is arranged for generating the control signal (V1,V2,V3,V4) in dependence on all the clock signals available in the clock synchronization device.

3. Multiprocessor device as claimed in Claim 1 or 2, characterized in that the phase comparators (PHI12,PHI13,...,PHI43) comprise a phase shifter (PHS) for converting a feedback clock signal into a phase-shifted clock signal and an exclusive-OR gate (XOR) for detecting a phase error signal (V12,V13,...,V43) based upon the phase-shifted clock signal and another feedback clock signal.

4. Multiprocessor device as claimed in one of the Claims 1 to 3, characterized in that the combining means (CMB1 ,CMB2,CMB3,CMB4) are formed by an adder circuit.

5. Multiprocessor device as claimed in one of the Claims 1 to 4, characterized in that the clock circuits (1,2,3,4) comprise switching means (DET1 ,DET2,DET3,DET4, AND1,AND2,AND3,AND4) for switching off the clock circuits (1,2,3,4) if the control signals (V1,V2,V3,V4) present in the clock circuits (1,2,3,4) end up outside a specific interval.

6. Clock synchronization device (cir) which comprises a plurality of clock circuits (1,2,3,4) which are arranged for generating mutually synchronized clock signals (clkl,clk2,clk3,clk4), which clock circuits (1,2,3,4) comprise a clock signal generator (VCOl,VCO2,VCO3,VCO4) and a control signal generator means

(CSGM1,CSGM2,CSGM3,CSGM4) for generating, in dependence on a plurality of feedback clock signals, a control signal (V1,V2,V3,V4) for readjusting via the clock signal generator (VCOl,VCO2,VCO3,VCO4) a clock signal to be generated, characterized in that the control signal generator means (CSGM1,CSGM2,CSGM3,CSGM4) comprises at least two phase comparators (PHI12,PHI13,...,PHI43) for generating phase error signals (V12,V13 V43) in response to at least three feedback clock signals, and a combining circuit (CMB1,CMB2,CMB3,CMB4) for combining the phase error signals (V12,V13,... ,V43) to the control signal (V1,V2,V3,V4).