WO1996012249B1 - Improvement in data collection of data processing apparatus from peripherals thereof - Google Patents
Improvement in data collection of data processing apparatus from peripherals thereofInfo
- Publication number
- WO1996012249B1 WO1996012249B1 PCT/JP1995/002072 JP9502072W WO9612249B1 WO 1996012249 B1 WO1996012249 B1 WO 1996012249B1 JP 9502072 W JP9502072 W JP 9502072W WO 9612249 B1 WO9612249 B1 WO 9612249B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- peripheral
- data
- data processing
- processing apparatus
- collection
- Prior art date
Links
- 230000002093 peripheral Effects 0.000 title claims abstract 181
- 238000000034 method Methods 0.000 claims 7
- 230000001276 controlling effect Effects 0.000 claims 2
- 238000005457 optimization Methods 0.000 claims 2
- 238000003672 processing method Methods 0.000 claims 2
- UIIMBOGNXHQVGW-UHFFFAOYSA-M buffer Substances [Na+].OC([O-])=O UIIMBOGNXHQVGW-UHFFFAOYSA-M 0.000 claims 1
- 230000000875 corresponding Effects 0.000 claims 1
Abstract
A data processing apparatus achieves high-speed image control, image control responding rapidly to the content of the operation of a peripheral, avoidance of possible wrong recognition of the peripheral. A subCPU is connected through a CPU bus to a main CPU which provides image control, etc. When the main CPU delivers command data to the subCPU through a register table, the subCPU determines peripheral data collection timing and collects pheripheral data from the peripheral at that timing. The main CPU receives through the register table the peripheral data collected by the subCPU. The subCPU receives peripheral data ID-1 (identification data) twice. If both the values of those peripheral data are different, the main CPU determines that the peripheral has not been connected to a peripheral port.
Claims
1. (Amended) A data processing apparatus comprising: main data processor; sub-data processor functionally connected with the main data processor via bus means; a peripheral port to which a peripheral device is detachably connectable;
I/O interface means connected to the peripheral port; and a switching means for switching over access to the peripheral device via the I/O interface means by the main data processor and by the sub-data processor.
2. (Amended) The data processing apparatus of claim 1, wherein the sub-data processor identifies the kind of the peripheral device based on the identification data supplied from the peripheral device and supplies data indicative of the identified kind of the peripheral device to the main data processor.
3. (Canceled)
4. (Amended) The data processing apparatus of claim 1 or 2, wherein the switching means operates the switching-over function in accordance with a control signal from the main data processor. 81
5. (Amended) The data processing apparatus of claim 1 or 2, wherein the switching means operates the switching-over function in accordance with the kind of the peripheral device.
6. (Amended) The data processing apparatus of any one of claims 1, 2, 4 and 5, wherein the switching means connects the I/O interface means with the main data processor when the peripheral device is of a kind requiring a high access speed while with the sub-data processor when the peripheral device is of a kind requiring a low access speed.
7. (Amended) The data processing apparatus of any one of claims 1, 2, 4-6, wherein the switching means operates the switching-over function in accordance with a program executed by the main data processor.
8. (Amended) A data processing apparatus to which a peripheral is connected, comprising: data collection means for collecting peripheral data from the peripheral; data processing means for executing data processing at every predetermined intervals of time using the peripheral data collected in each of the predetermined intervals of time; and data collection control means for controlling the data collection means such that collection of the peripheral data ends directly before the data processing starts on the basis 82
of information regarding the last collection of the peripheral data.
9. (Amended) The data processing apparatus of Claim 8, wherein the data collection control means determines the time of starting the collection of peripheral data such that the collection of the peripheral data ends directly before the time of starting the data processing.
10. (Amended) The data processing apparatus of Claim 9, wherein the data collection control means determines the time of starting the collection of the peripheral data by executing at least one of: a process (1) for determining the time of starting the collection of the peripheral data on the basis of the time of the last collection of peripheral data such that the collection of the peripheral data ends directly before the time of starting the data processing when the last collection of peripheral data has ended before the time of starting the last data processing; and a process (2) for advancing the time of starting the collection of the peripheral data when the last collection of peripheral data does not end before the time of starting the last data processing.
11. The data processing apparatus of Claim 10, wherein the data collection control means performs the processes (1) and
(2) repeatedly. 83
12. (Amended) The data processing apparatus of Claim 8, wherein the data collection control means controls a data collection time provided in the data collection means such that the collection of the peripheral data ends directly before the time of starting the data processing.
13. (Amended) The data processing apparatus of any one of Claim 1-7, wherein the suboperation means comprises data collection means for starting at a given time the collection of peripheral data output from the peripheral, data processing means for executing data processing at every predetermined intervals of time using the peripheral data collected in each of the predetermined intervals of time , and data collection control means for determining the time of starting the collection of the peripheral data such that the collection of the peripheral data ends directly before the time of starting the data processing.
14. (Amended) The data processing apparatus of any one of Claims 1, 2, 4-13, comprising determination means for determining whether a signal line of the peripheral is connected to a terminal of the data processing apparatus.
15. (Amended) A data processing method comprising the steps of: starting collection of peripheral data output from a peripheral at a given data collection starting time; 84
performing data processing at every predetermined intervals of time using the peripheral data collected in each of the predetermined intervals of time; and determining the data collection starting time of the peripheral data such that the collection of the peripheral data ends directly before the time of starting the data processing.
16. The data processing method of Claim 15, wherein the determining steps executes the processes of: determining the time of starting the collection of the peripheral data on the basis of the last collected peripheral data such that the collection of the peripheral data ends directly before the time of starting the data processing on the basis of the time of the last collection of peripheral data when the last collection of the peripheral data ends before the time of starting the data processing; and advancing the time of starting the collection of peripheral data when the last collection of the peripheral data does not end before the time of starting the data processing.
17. (Amended) A data processing apparatus comprising a connector terminal connectable to a peripheral, data processing means for performing data processing using data from the peripheral connected to the connector terminal, and determination means for determining whether a signal line of 85
the peripheral has been connected to the connector terminal, comprising: communication means for communicating peripheral data to the peripheral after reading identification data on identification of the kind of the peripheral through the connector terminal, wherein the determination means determining that the signal line of the peripheral has been connected to the connector terminal on condition that all the identification data read more than once at predetermined intervals of time by the communication means coincides.
18. (Amended) A data processing apparatus comprising a connector terminal connectable to a peripheral, data processing means for performing data processing using data from the peripheral connected to the connector terminal, and determination means for determining whether a signal line of the peripheral has been connected to the connector terminal, wherein the connector terminal being pulled up or down such that predetermined data indicative of an unconnected state of the peripheral is output from the peripheral when the peripheral is unconnected to the connector terminal, the data processing apparatus comprising communication means for communicating peripheral data to the peripheral through the connector terminal, the determination means determining that the peripheral is unconnected to the connector terminal when connection confirming data which includes an inverse of the predetermined data indicative of the unconnected state of the peripheral has been transmitted from the peripheral and the 86
connection confirming data received by the communication means is different from the inverse of the predetermined data indicative of the unconnected state of the peripheral.
19. (Amended) A data processing apparatus comprising a socket connector terminal connectable to a peripheral, data processing means for performing data processing using data from the peripheral connected to the socket connector terminal, and determination means for determining whether a signal line of the peripheral has been connected to the socket connector terminal, wherein the socket connector terminal being connectable to the peripheral which has plug connector terminals, one of which is connected to one of a power supply and ground (GND), the data processing apparatus comprising communication means for communicating peripheral data to the peripheral through the plug connector terminal and the socket connector terminal, the determination means determining that the peripheral is unconnected to the socket connector terminal when the signal level on the socket connector terminal corresponding to the plug connector terminal connected to one of the power supply and GND is different from a signal level on the last-mentioned plug connector terminal.
20. (Amended) A data processing apparatus comprising a connector terminal connectable to a peripheral, data processing means for performing data processing using data from the peripheral connected to the connector terminal, and determination means for determining whether a signal line of the peripheral has been connected to the connector terminal, comprising: communication means for receiving a response signal and peripheral data from the peripheral after the communication means has transmitted a data request signal to the peripheral, wherein the determination means determining that the peripheral is unconnected to the connector terminal when the communication means receives no response signal within a predetermined time after the communication means has transmitted the data request signal.
21. (Amended) A method of processing data transmitted from a peripheral to a data processing apparatus, comprising the step of determining whether a signal line of the peripheral is connected to a connector terminal of the data processing apparatus on the basis of the data transmitted from the peripheral.
22. (Amended) A peripheral for outputting data to be processed to a data processing apparatus, comprising a connector terminal connected to the data processing apparatus, the peripheral outputting data for confirming that the terminal has been connected to the processing apparatus.
23. A peripheral of Claim 22 for outputting at least one of pieces of the identification data of Claim 17, connection 88
confirming data of Claim 18, signal of Claim 19, response signal or peripheral data of Claim 20.
24. (Amended) A data processing apparatus to which a peripheral detachably is connected, comprising: a main CPU processing a peripheral data supplied from the peripheral; a first ROM connected to the main CPU; a first RAM serving as a work area for the main CPU; and a sub CPU circuit connected with the main CPU through a bus and detachably connected to the peripheral through a connector, said sub CPU circuit comprising a first interface, connected to the bus, a CPU core and a second RAM both connected to the first interface, a second ROM connected to the CPU core, and a second interface connected to both the CPU core and connector, wherein said first ROM stores a first program for sending to the sub CPU circuit an instruction to collect a peripheral data from the peripheral and a second program for fetching the peripheral data collected by the sub CPU circuit: and said second ROM stores a third program for collecting the peripheral data from the peripheral in response to the instruction and providing the main CPU with the collected peripheral data.
25. The data processing apparatus of claim 24, wherein said connector having a socket connector incorporating therein a set of nine terminal pins disposed in a row in the order of the first to the ninth pins to which a set of nine terminal 89
pins of a plug connector extending from the peripheral are detachably connected, said first pin of the socket connector being assigned for one of a power source and the ground potential, said ninth pin of the socket connector being assigned for the other of the power source and the ground potential, said second, third, seventh and eighth pins being assigned for transmitting data signals, at least said fourth and fifth pins being assigned for transmitting control signals, and said second ROM storing a program for identifying a communication mode inherently set to the peripheral on the basis of the data signals supplied through the second, third, seventh and eighth pins of the socket connector.
26. The data processing apparatus of claim 25 further comprising a multiplexer for selectively connecting the bus coupled with the main CPU and the CPU core to the second interface, wherein said first interface comprises means for controlling exchange of the multiplexer.
27. The data processing apparatus of claim 24, wherein said first interface has a register table receiving and transmitting data between the main CPU and the CPU core.
28. The data processing apparatus of claim 27, wherein said register table comprises a command register in which the main CPU writes a command to transmit the command to the CPU core, a status register data of which are read out by the main CPU 90
for examining a state of the CPU core after the CPU core executed the command, a status flag indicative of whether or not the CPU core is under execution of the command by setting the status flag before the main CPU writes the command in the command register and resetting the status flag after the CPU core executed the command, an input register in which the main CPU writes a command parameter associated with the command to transmit the command parameter to the CPU core, and an output register in which the CPU core writes data to transmit the data to the main CPU.
29. The data processing apparatus of claim 28, wherein said first program executed by the main CPU determines periodically whether or not the status flag is reset by the CPU core, then not only waits when the status flag is not reset but also sets the status flag when the status flag is reset, then writes in the input register the parameter of the command for collecting the peripheral data, and then writes in the command register the command for collecting the peripheral data; said third program executed by the CPU core reads out from the command register the command for collecting the peripheral data, then, at every specified period, not only identifies a type of the peripheral and a communication mode thereof by communicating with the peripheral but also reads out the peripheral data from the peripheral according to the communication mode, and then writes in the read-out peripheral data in the output register; and 9 1
said second program executed by the main CPU reads out the peripheral data stored in the output register at every specified period.
30. (Amended) A data processing apparatus to which a peripheral is detachably connected, comprising: a main CPU processing a peripheral data supplied from the peripheral; a first ROM connected to the main CPU; a first RAM serving as a work area for the main CPU; and a sub CPU circuit connected to the main CPU through a bus and detachably connected with the peripheral through a connector, said sub CPU circuit comprising a first interface connected to the bus, a CPU core and a second RAM both connected to the interface, a second ROM connected to the CPU core, and a second interface connected to both the CPU core and connector, wherein said second ROM stores a program which collects the peripheral data from the peripheral in response to a command given from the main CPU and then sends the collected peripheral data to the main CPU, in which a start time of collecting the peripheral data is optimized at every specified time so as to an end time of collecting the peripheral data coincides with a start time of processing the peripheral data in the main CPU.
31. The data processing apparatus of claim 30 to which a monitor is connected for displaying a processing result of the peripheral data executed by the main CPU, wherein said 92
specified time is determined by either one of a first transit and a last transit of a vertical blanking signal used by the monitor.
32. The data processing apparatus of claim 31, wherein said program includes a first step initializing a flag and a variable both concerning optimization of the start time of collecting the peripheral data; a second step, following the first process, calculating the start time at an interruption responding to a collection instruction; and a third step not only waiting for the calculated start time but also collecting the peripheral data when the calculated start time has come.
33. The data processing apparatus of claim 32, wherein said flag consists of a first flag indicative of whether or not the start time will be optimized in a next peripheral data collecting period and a second flag indicative of whether or not a time-out which the vertical blanking signal has appeared during collection of the peripheral data executed by the CPU core has occurred; and said variable shows the start time, wherein said first flag is set by the first step to a logic value "0" expressing that the optimization of the start time will not be carried out and second flag is set by the first step to a logic value "1" expressing that the time-out has occurred.
34. The data processing apparatus of claim 33, wherein said second step is a step which clears a count of a counter when 93
either one of the first and second flags is a logic value "1", replaces a value of the variable with an addition value of a current value of the variable, a count of the counter, and a time margin value when both the first and second flags are logic value "0", sets a logic value "1" into the first flag, and clears the count of the counter.
35. The data processing apparatus of claim 34, wherein said third step is a step which sets a logic value "0" into the second flag, sets a logic value "0" into the first flag only when the first flag is a logic value "1", waits until the count of the counter will reach the value of the variable, replaces the value of the variable with the current count of the counter, not only collects the peripheral data to send the collected peripheral data to the main CPU but also sets a logic value "1" into the second flag when the time-out occurs during the collection of the peripheral data, and then clears the count of the counter.
36. (Amended) A data processing apparatus to which a peripheral having a plug connector is detachably connected, comprising: a main CPU processing a peripheral data supplied from the peripheral; a first ROM connected to the main CPU; a first RAM serving as a work area for the main CPU; a sub CPU circuit connected with the main CPU through a bus; and a socket connector to which the bus is connected and the plug connector of the peripheral is detachably connected, 94
said sub CPU circuit comprising a first interface connected to the bus, a CPU core and a second RAM both connected to the first interface, a second ROM connected to the CPU core, and a second interface connected to both the CPU core and socket connector, wherein said second ROM stores a program for automatically recognizing a connection state of the plug connector of the peripheral to the socket connector when the sub CPU circuit collects the peripheral data from the peripheral responsively to a command from the main CPU.
37. The data processing apparatus of claim 36, wherein said socket connector comprises a set of nine terminal pins disposed in a row in the order of the first to ninth pins, said first pin being assigned for one of a power source and the ground potential and said ninth pin being assigned for the other of the power source and the ground potential, said second, third, seventh and eighth pins being assigned for transmitting data signals, and said fourth to sixth pins being assigned for transmitting control signals; and said plug connector comprises another set of nine terminal pins disposed in a row in the order of the first to ninth pins each detachably connected to each of the first to ninth pins of the socket connector.
38. The data processing apparatus of claim 37, wherein each of signal lines connected to said second to eighth pins of the 95
socket connector is connected to the power source indicative of a logic value "1" through a register.
39. The data processing apparatus of claim 38, wherein said program stored by the second ROM includes a process which, when "1" and "0" represent the power source and the ground potential respectively, at each of a state that control signals "1" and "1" are supplied through the fourth and fifth pins respectively and a state that control signals "0" and "1" are supplied through the fourth and fifth pins respectively, calculates an identification data using the data signals from the peripheral through the seventh, eighth, second and third pins at every specified time; and determines a completion of connection of the peripheral to the data processing apparatus when calculation values of the identification data are indicative of a connected status of the plug connector to the socket connector over a plurality of the specified times.
40. The data processing apparatus of claim 39, wherein said program stored by the second ROM includes another process which determines a non-connected status of the peripheral to the data processing apparatus when the identification data at the current specified time is different in the calculation value from the last specified time.
41. (Amended) A data processor for use with a data processing apparatus including a main CPU, the data processor comprising: 96
I/O interface means through which the data processor communicates with a peripheral device which is detachably connectable to a peripheral port of the apparatus;
CPU bus means through which the data processor communicates with the main CPU; a CPU core functionally connected to the CPU bus means so as to execute a command provided from the main CPU; a ROM storing a program required for processing the command; and a switching means which functionally connects the I/O interface selectively with one of the CPU bus means and the CPU core in compliance with an access speed required by the peripheral device.
42. (Amended) The data processor of claim 41, wherein said switching means comprises a multiplexer which is connected to the I/O interface means, and register means which functionally connects the multiplexer with the CPU core and with the CPU bus means.
43. (Amended) The data processor of claim 42, wherein said register means comprises a first register group which functionally connects the multiplexer with the CPU core, a second register group which functionally connects the multiplexer with the CPU means, and an I/O selection register which controls the switching function of the multiplexer so as to allow one of the main CPU and the CPU core to access the
AMENDEDSHEET(ARΗCLE19) 96 / 1
peripheral device responsively to the data set in the I/O selection register.
44. (Amended) The data processor of claim 43, wherein each of the first and second register group comprises a data direction register which sets signal line directions of input/output data at the peripheral port and a port data register which stores data at the peripheral port.
45. (Amended) The data processor of claim 42, wherein said multiplexer comprises a plurality of three-state buffers which perform switching functions responsive to control data set into the I/O selection register.
46. (Amended) The data processor of claim 41, wherein the program stored in the ROM is a program collecting peripheral data from the peripheral device to send the peripheral data to the main CPU when the CPU core receives from the main CPU a command notifying a start of collection of the peripheral data.
47. (Amended) The data processor of claim 46, further comprising an interface means provided between the CPU core and the CPU bus means and having a register table through which data communication between the main CPU and the CPU core is carried out.
AMENDED SHEET(ARΗCLE19) 96/2
48. (Amended) The data processor of claim 47, wherein said register table comprises a command register in which the main CPU writes a command to transmit the command to the CPU core, a status register data of which are read out by the main CPU for examining a state of the CPU core after the CPU core executed the command, a status flag indicative of whether or not the CPU core is under execution of the command by setting the status flag before the main CPU writes the command in the command register and resetting the status flag after the CPU core executed the command, an input register in which the main CPU writes a command parameter associated with the command to transmit the command parameter to the CPU core, and an output register in which the CPU core writes data to transmit the data to the main CPU.
49. (New) A peripheral for supplying peripheral data to a data processing apparatus having a main data processor processing the peripheral data, a sub-data processor functionally connected to the main data processor, a peripheral port to which the peripheral is detachably connectable, an I/O interface means connected to the peripheral port, and a switching means for switching over access to the peripheral via the I/O interface means by the main data processor and by the sub-data processor responsively to designation of either one of a first control mode allowing the main data processor to directly gain access to the peripheral through the I/O interface means to collect the peripheral data and a second control mode allowing the sub-data processor to gain access to 96/ 3
the peripheral through the I/O interface means to collect the peripheral data and provide the main data processor the collected peripheral data, wherein the peripheral is constructed in a manner that the peripheral supplies the peripheral data to the I/O interface means responsively to the access of either one of the main data processor and the sub-data processor, the peripheral data including data manually-inputted by a user.
50. (New) The peripheral of claim 49, wherein the peripheral data includes an identification data indicative of a kind of the peripheral, thereby the sub-data processor identifies the kind of the peripheral.
51. (New) The peripheral of claim 49, wherein the peripheral data includes data for confirming the peripheral has been connected to the peripheral port of the data processing apparatus.
52. (New) The peripheral of claim 49, wherein the peripheral is detachably connectable with the data processing apparatus in which the switching means connects the I/O interface means with the main data processor when the peripheral device is of a kind requiring a high access speed while with the sub-data processor when the peripheral device is of a kind requiring a low access speed.
AMENDEDSHEET(ARΗCLE19) 97 STATEMENT UNDER ARTICLE19
Claims 1 and 41 each describe a switching means. The cited references 1 and 2 do not describe such switching means.
Claims 17-22 each describe a determination means. The cited references 1 and 2 do not indicate such determination means.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/656,226 US5892974A (en) | 1994-10-12 | 1995-10-11 | System for sub-data processor identifies the peripheral from supplied identification data and supplies data indicative of the kind of peripheral to main data processor |
| EP95934268A EP0733242A1 (en) | 1994-10-12 | 1995-10-11 | Improvement in data collection of data processing apparatus from peripherals thereof |
| AU36724/95A AU3672495A (en) | 1994-10-12 | 1995-10-11 | Improvement in data collection of data processing apparatus from peripherals thereof |
| CA002176940A CA2176940C (en) | 1994-10-12 | 1995-10-11 | Improvement in communication between data processing apparatus and peripheral device thereof |
| JP8513088A JPH09512369A (en) | 1994-10-12 | 1995-10-11 | Improving data collection from its peripherals by a data processor |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6/246580 | 1994-10-12 | ||
| JP24657994 | 1994-10-12 | ||
| JP24658094 | 1994-10-12 | ||
| JP6/246579 | 1994-10-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1996012249A1 WO1996012249A1 (en) | 1996-04-25 |
| WO1996012249B1 true WO1996012249B1 (en) | 1996-05-30 |
Family
ID=26537800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP1995/002072 WO1996012249A1 (en) | 1994-10-12 | 1995-10-11 | Improvement in data collection of data processing apparatus from peripherals thereof |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5892974A (en) |
| EP (1) | EP0733242A1 (en) |
| JP (1) | JPH09512369A (en) |
| CN (1) | CN1136849A (en) |
| AU (1) | AU3672495A (en) |
| TW (1) | TW357913U (en) |
| WO (1) | WO1996012249A1 (en) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7993194B1 (en) | 1998-06-18 | 2011-08-09 | Aristocrat Technologies Australia Pty Limited | Method of linking devices to gaming machines |
| WO2000057290A1 (en) * | 1999-03-19 | 2000-09-28 | Hitachi, Ltd. | Information processor |
| JP3449313B2 (en) | 1999-09-28 | 2003-09-22 | 日本電気株式会社 | Device information collection method, device control device, and bridge |
| US6618048B1 (en) | 1999-10-28 | 2003-09-09 | Nintendo Co., Ltd. | 3D graphics rendering system for performing Z value clamping in near-Z range to maximize scene resolution of visually important Z components |
| US6717577B1 (en) | 1999-10-28 | 2004-04-06 | Nintendo Co., Ltd. | Vertex cache for 3D computer graphics |
| US7047338B1 (en) * | 2000-07-18 | 2006-05-16 | Igt | Configurable hot-swap communication |
| US6811489B1 (en) | 2000-08-23 | 2004-11-02 | Nintendo Co., Ltd. | Controller interface for a graphics system |
| US7576748B2 (en) | 2000-11-28 | 2009-08-18 | Nintendo Co. Ltd. | Graphics system with embedded frame butter having reconfigurable pixel formats |
| US6700586B1 (en) | 2000-08-23 | 2004-03-02 | Nintendo Co., Ltd. | Low cost graphics with stitching processing hardware support for skeletal animation |
| US6636214B1 (en) | 2000-08-23 | 2003-10-21 | Nintendo Co., Ltd. | Method and apparatus for dynamically reconfiguring the order of hidden surface processing based on rendering mode |
| US7538772B1 (en) | 2000-08-23 | 2009-05-26 | Nintendo Co., Ltd. | Graphics processing system with enhanced memory controller |
| US6609977B1 (en) | 2000-08-23 | 2003-08-26 | Nintendo Co., Ltd. | External interfaces for a 3D graphics system |
| US7196710B1 (en) | 2000-08-23 | 2007-03-27 | Nintendo Co., Ltd. | Method and apparatus for buffering graphics data in a graphics system |
| US7134960B1 (en) | 2000-08-23 | 2006-11-14 | Nintendo Co., Ltd. | External interfaces for a 3D graphics system |
| US6707458B1 (en) | 2000-08-23 | 2004-03-16 | Nintendo Co., Ltd. | Method and apparatus for texture tiling in a graphics system |
| US7003588B1 (en) | 2001-08-22 | 2006-02-21 | Nintendo Co., Ltd. | Peripheral devices for a video game system |
| US6810439B2 (en) * | 2003-02-18 | 2004-10-26 | Hewlett-Packard Development Company, L.P. | System and method to monitor connections to a device |
| JP5340803B2 (en) * | 2009-05-18 | 2013-11-13 | 株式会社ソニー・コンピュータエンタテインメント | Information processing device |
| JP5966270B2 (en) * | 2010-09-16 | 2016-08-10 | 株式会社リコー | System and device management program |
| JP5929431B2 (en) | 2012-03-30 | 2016-06-08 | ブラザー工業株式会社 | Image recording apparatus, control method for image recording apparatus, and control program |
| JP5477456B2 (en) * | 2012-12-04 | 2014-04-23 | 株式会社バッファロー | Peripheral device and method for connecting host device and peripheral device |
| CN103744324B (en) * | 2013-12-23 | 2017-01-11 | 广西科技大学 | Indoor environment quality monitoring-based data acquisition method |
| TW201601407A (en) * | 2014-06-24 | 2016-01-01 | 萬國商業機器公司 | Power distribution unit and alarming method applied in the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4534011A (en) * | 1982-02-02 | 1985-08-06 | International Business Machines Corporation | Peripheral attachment interface for I/O controller having cycle steal and off-line modes |
| US4862156A (en) * | 1984-05-21 | 1989-08-29 | Atari Corporation | Video computer system including multiple graphics controllers and associated method |
| US4912672A (en) * | 1988-01-15 | 1990-03-27 | Giorgio Paul J | Computer peripheral rate aided sensing system |
| US5157519A (en) * | 1989-08-24 | 1992-10-20 | Fujitsu America, Inc. | Serial computer peripheral for facsimile image and ascii text communication |
| JP2784811B2 (en) * | 1989-08-25 | 1998-08-06 | ソニー株式会社 | Image creation device |
| JP3468786B2 (en) * | 1992-11-27 | 2003-11-17 | 任天堂株式会社 | Information processing apparatus and information processing method using optical storage medium |
| WO1994016774A1 (en) * | 1993-01-27 | 1994-08-04 | Life Fitness | Physical exercise video system |
-
1994
- 1994-10-13 TW TW084210124U patent/TW357913U/en unknown
-
1995
- 1995-10-11 JP JP8513088A patent/JPH09512369A/en active Pending
- 1995-10-11 CN CN95191026A patent/CN1136849A/en active Pending
- 1995-10-11 WO PCT/JP1995/002072 patent/WO1996012249A1/en not_active Application Discontinuation
- 1995-10-11 AU AU36724/95A patent/AU3672495A/en not_active Abandoned
- 1995-10-11 US US08/656,226 patent/US5892974A/en not_active Expired - Fee Related
- 1995-10-11 EP EP95934268A patent/EP0733242A1/en not_active Withdrawn
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