WO1996012229A1 - Indexing and multiplexing of interleaved cache memory arrays - Google Patents

Indexing and multiplexing of interleaved cache memory arrays Download PDF

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Publication number
WO1996012229A1
WO1996012229A1 PCT/US1995/013241 US9513241W WO9612229A1 WO 1996012229 A1 WO1996012229 A1 WO 1996012229A1 US 9513241 W US9513241 W US 9513241W WO 9612229 A1 WO9612229 A1 WO 9612229A1
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WO
WIPO (PCT)
Prior art keywords
cache
data
array
tag
address
Prior art date
Application number
PCT/US1995/013241
Other languages
English (en)
French (fr)
Inventor
Kenneth C. Yeager
Original Assignee
Silicon Graphics, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Graphics, Inc. filed Critical Silicon Graphics, Inc.
Priority to EP95938247A priority Critical patent/EP0803095A1/en
Priority to JP8513403A priority patent/JPH10509819A/ja
Publication of WO1996012229A1 publication Critical patent/WO1996012229A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array

Definitions

  • Processor 100 fetches and decodes instructions in their original program order but may execute and complete these instructions out of order. Once completed, instructions are "graduated" in their original program order.
  • LoadDone signal is generated in two circuit stages 851 and 852.
  • Circuit stage 851 generates a LoadMiss in response to IgnoreHitB, IgnoreHitA,
  • LoadDoneHit & ⁇ LoadMiss Load is "done” only if the cache "hits”.
  • Circuit stages 851 and 852 may be implemented with a 4x3 dynamic "and-or” gate.
  • the circuit's critical path inputs are the "miss” pulses from the tag comparators. These are complements of the "hit” signals, so this equation is complemented.
  • a fifth term IgnoreHitA&IgnoreHitB has been omitted. It is redundant because the cache cannot properly generate a hit on both ways simultaneously).
  • Fig. 13 shows tag row decoder 900 which is a 6-bit to 64-bit row decoder which selects which word line will be asserted.
  • the decoder's input is selected from the addresses provided by the Address Calculation unit, address stack, or extemal interface.
  • the address is latched at the end of phase 2, so that it will be stable while the wold line is driven during the following phase 1.
  • Decoding is split into predecode and drivers.
  • the predecoder 901 the high 3 bits (13:11) and low 3 bits (10:8) are separately decoded by 3-to-8 decoders 902 and 903, respectively.
  • Each predecoder has one output high.
  • Low decoder 903 can force all its outputs low to disable the tag array, thereby eliminating most power dissipation in the tag array.
  • These decoders are next to the array at the center.
  • the outputs drive signals across the array to the row decoders. Each output drives 8 loads, which may be distributed across the tag array.
  • One driver is selected by logically and-ing one input from predecoder 901.
  • the output ofthe "and” gate should be stable by the end of each cycle. It is gated with ⁇ , to generate a pulse during the first half of the next cycle.
  • the Extemal Interface sends this command, a new state code, state modifier, an index address, a tag address, two cycles before the actual cache operation.
  • the cache and the address queue each pipeline these fields for use during the next two cycle.
  • the extemal interface sends the processor a "busy" signal which indicates when it can accept new operations. Bits 1 indicates if the Miss Handling Table is busy. If it is set the Extemal Interface cannot accept any new command. Bits 0 indicates if the Write-Back Buffer is busy. If it is set, the Extemal Interface cannot accept any refill request for an "inconsistent" block and data is written back to secondary cache. During cycle "CO", the Extemal Interface sends the address queue a

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
PCT/US1995/013241 1994-10-14 1995-10-13 Indexing and multiplexing of interleaved cache memory arrays WO1996012229A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP95938247A EP0803095A1 (en) 1994-10-14 1995-10-13 Indexing and multiplexing of interleaved cache memory arrays
JP8513403A JPH10509819A (ja) 1994-10-14 1995-10-13 インターリーブされるキャッシュメモリアレイのインデッキシングとマルチプレキシング

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US32412494A 1994-10-14 1994-10-14
US08/324,124 1994-10-14

Publications (1)

Publication Number Publication Date
WO1996012229A1 true WO1996012229A1 (en) 1996-04-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1995/013241 WO1996012229A1 (en) 1994-10-14 1995-10-13 Indexing and multiplexing of interleaved cache memory arrays

Country Status (4)

Country Link
US (1) US6594728B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (2) EP0803095A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH10509819A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
WO (1) WO1996012229A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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Also Published As

Publication number Publication date
EP0803095A1 (en) 1997-10-29
EP1278125A2 (en) 2003-01-22
JPH10509819A (ja) 1998-09-22
US6594728B1 (en) 2003-07-15
EP0803095A4 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1997-10-29

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