WO1996009709A2

WO1996009709A2 - Method and arrangement for eliminating the influence of high-capacitance nodes

Info

Publication number: WO1996009709A2
Application number: PCT/SE1995/001054
Authority: WO
Inventors: Nianxiong Tan
Original assignee: Forskarpatent I Linköping Ab
Priority date: 1994-09-21
Filing date: 1995-09-19
Publication date: 1996-03-28
Also published as: WO1996009709A3; SE9403172D0; SE9403172L; AU3581495A

Abstract

The invention relates to a method and an arrangement for avoiding the influence of a high-capacitance node on digital signal transfer in relation to a VLSI-circuit chip, for instance a CMOS-chip. A digital signal having voltage swing is converted to a digital signal having current swing and stabilized potential at the input of said node. The current swing signal is converted back to a voltage swing signal at the output of the node.

Description

Method and arrangement for eliminating the influence of hiσh- capacitance nodes

This invention relates to a method for avoiding the influence of high-capacitance nodes on digital signal transfer in VLSI- circuit chips, for instance CMOS-chips, and an arrangement for executing the method.

A lot of power is consumed by driving high-capacitance nodes (e.g. padbuses) in digital VLSI-circuit chips, for instance CMOS-chips, and a large voltage swing of the digital pulses transferred through the nodes is the reason especially when clocked at very high frequency. Today, the sub-micron CMOS technology provides the possibility of integrating millions of transistors on a single chip. Power consumption then naturally arises to be a very important issue because of the heat generated inside the chip which can burn it.

Low power consumption is also required for battery-powered systems, such as laptop computers, personal communication services, and medical applications.

Another important issue is the switching noise generated by the CMOS digital circuits, since more and more CMOS digital chips contain a portion of analog interfacing circuits and the switching noise, obtained particularly from high-capacity nodes, poses a severe limitation on the performance of the onchip analog circuits.

Power consumption of CMOS digital circuits is mainly the dynamic power consumption, approximated by

P » ∑C_i*ώV_i*V_dd*f_i (1) where C_L is the capacitive load, AV_L is the voltage swing, V_dd is the power supply voltage, and f_L is the actual operation frequency for the circuit block i.

The delay time for transfer through a high-capacitance node can be approximated by ^tdi^sCi*^ΔVi/Iavi (2) where I_av^ is the average charging current for circuit block i. The delay time limits the operation speed.

The switching current noise i . when transmitting pulses through a node can be expressed as ini^=ci*^dvi/ ^{t (3)}

The voltage swing is usually equal to power supply voltage V_dd. From the Equations (1) to (3) it is seen that this large voltage swing results in large power consumption, long delay, and large switching noise when the capacitance is very large, especially for high frequencies.

Different techiques have earlier been proposed to increase the speed and reduce the dynamic power consumption. The main ideas were then to reduce the capacitance load and voltage swing, usually at the cost of some static power consumption. However, most of the prior art techniques focused on the on- chip digital circuits. Examples of these techniques are described in for instance the following articles: "Low Power CMOS digital design" by A. P. Chandrakassan, S. Sheng and R. . Brothersen, IEEE J. Solid-State Circuits, vol 27, pp. 473-484, April 1992; "Trading speed for low power by choice of supply and threshold voltages", by D. Liu and C. Svensson, IEEE J. Solid-State Circuits, vol 28, pp. 10-17, Jan. 1993.

In reality, die pads which are inevitable for chip-to-chip communication limit the performance, because they have indeed a very large parasitic capacitance.

A main object of the invention is to provide digital signal transfer in VLSI-circuit chips and/or in chip-to-chip communication through a high-capacitance node with low dynamic power consumption.

Another object of the invention is to provide digital signal transfer in VLSI-circuit chips and/or in chip-to-chip communication through a high-capacitance node with short delay.

Still another object of the invention is to provide digital signal transfer in VLSI-circuit chips and/or in chip-to-chip communication through a high-capacitanse node with low or eliminated switching noise.

The aforesaid objects are achieved with a method of the kind set forth in the introduction and have the characteristic features set forth in Claim 1. Further characteristics and developments and an arrangement for achieving the method are disclosed in the rest of the Claims.

According to the invention the voltage swing at high- capacitance nodes is practically eliminated by using a current-mode technique, in which the digital pulse signal, having for instance a high voltage for the transfer of a "1" and a low voltage for the transfer of a "0", is converted to a current signal through each node having a high capacitance. Preferably, the converted current signal is such that it is the current direction that is essential and thus current going in one direction represents a "1" and in the opposite direction a "0". Thus, the current direction is preferably used to represent the logic values. The digital signal is then converted back to a voltage pulse train having the voltage level to represent the logic values after the high- capacitance node. The potential of the high-capacitance nodes should also be stabilized.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and for further objects and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which: Fig . 1 shows a block schedual of the main principle according to the invention,

Fig . 2 shows a block schedual of an advantageous embodiment according to the invention,

Fig . 3 shows a circuit schedual of an embodiment according to the invention, and

Fig . 4 shows a diagram of measurement results provided with the circuitry shown in Fig. 3.

With reference to FIG 1, a driver 1 including a voltage-to- current converter 2, below called v/i-converter, is connected to the input 3 of a high-capacitance node. The voltage pulse train v_in having different voltage levels for the transfer of "1" and "0", respectively, connected to the input of the v/i- converter is then converted to a current pulse train i having different current levels, preferably alternating current directions, for the transfer of "1" and "0". A receiver 4 including a current-to-voltage converter 5, below called i/v- converter, connected to an output 6 of the high-capacitance node converts the current pulse train i back to the voltage pulse train v_out.

If the potential of the high-capacitance node is stabilized, then practically no power is consumed when transmitting a data across the node except the power consumed by the v/i and i/v converters 2 and 5. These converters consume little power if they are properly designed. It is to be noted that the driver 1 and the receiver 4 are only to be inserted at nodes which pose problems because of their high capacitance. Examples of such nodes are die pads, which are inevitable for chip-to-chip communication, long wires inside a chip etc.

Stabilization of the potential of the node can be provided at one of the converters, if properly designed, but can instead advantageously be accomplished by using a current conveyor. In FIG 2 a current conveyor 7 is connected between the node output 6 and the i/v converter 5 in the receiver 4'. The current conveyor 7 is a three-port device having a first input X connected to the node output 6 and a second input Y connected to a reference voltage V_ref. The conveyor is such that the potential of the input X follows the potential of the input Y, independent of the current into or out of the input X, while the current at the output Z is dependent on, for instance a replica of, the input current at the input X.

The voltage signal v_in at the input of the v/i converter 2 has a large voltage swing. Therefore, its capacitance should be small to save power and have a high speed. The output of the converter 2 is the alternating current i and its potential essentially constant, which means that a large capacitance is of no concern.

The current conveyor 7 is used to stabilize the potential of the high-capacitance node. Then, ideally, the input conductance seen at the input X of the conveyor should be infinite. This is impossible to realize so therefore a small voltage variation of the potential of the input X can not be completely avoided because of finite input conductance but it should be minimized.

In the embodiment of the circuitry shown in FIG 3, the v/i converter 2 includes two p-type CMOS transistors T_p0 and T_pl having their source/drain paths series connected between a source voltage V_dd and an output I_out and two n-type CMOS transistors T_n0 and T_nl having their source/drain paths connected between earth and the output I_out. The interconnected drains of the transistors T_pl and T_nl are connected to their gates, which thus also are interconnected. The transistors thus acting as diodes. The gates o the transistors T_p0 and T_n0 are interconnected and conn ted to the circuit input V_in.

When the varying input voltage v_in is high, T_n0 conducts and T_p0 does not. A current flowing from the high-capacitance node through T_nl to ground is generated. The value is determinated by T_nl. When the input voltage V_in is low, T_p0 conducts but T_n0 does not. A current flowing from V_dd through T_pl to the high-capacitance node is generated. The value is determinated by T_pl.

The parasitic capacitance at the input of the v/i converter 2 is small, equal to that of a minimum-sized CMOS inverter, and it is independent of the value of the output current i. The output current value i is determined by T_nl and T_pl. It is possible to have biasing voltages for transistors T_nl and T_pl, but since the potential of output node is fixed (as described below) , the gates and drains of T_nl and T_pl can simply be short-circuited. The power consumption to drive the v/i converter 2 is usually very small, for instance less than 30μW even with a frequence around 100 MHz (V_dd = 5V) , and the delay time can be estimated to be equal to the delay time of driving a minimum-sized inverter. Typical value is less than 20 ps.

The shown embodiment of the current conveyor 7 is divided into two parts 7a and 7b, where 7a is a first circuit 7a indicating the current direction of its input current from said node and regulating the voltage level of said node to a reference voltage V_ref, and a second circuit 7b controlled by said first circuit to provide an output current having the same current direction as the input current. The circuit 7a comprises a p-type CMOS transistor T_p3 connected as a diode having its gate and drain interconnected and series connected with the drain/source path of a n-type CMOS transistor T_n5 between the voltage source V_dd and the input X. A n-type CMOS transistor T_n3 is connected as a diode having its gate and drain interconnected and is series connected with the drain/source path of a p-type CMOS transistor T_p5 between earth and the input X.

The source/drain path of a p-type CMOS transistor T_p4 is series connected with the drain/source path of a n-type CMOS transistor T_n6, connected as a diode having its gate and drain interconnected, between the voltage source V_dd and the input Y. A n-type CMOS transistor T_n4 is series connected with the drain/source path of a p-type CMOS transistor T_p6, connected as a diode having its gate and drain interconnected, between the earth and the input Y having the reference voltage V_ref which for instance can be chosen to V_dd/2. The gates of the n-type transistors T_n5 and T_n6 are interconnected and so are also the gates of the p-type transistors T_p5 and T_p6.

The circuit 7b includes a p-type CMOS transistor T ₇ having its source/drain path connected in series with the drain/source path of an n-type CMOS transistor T_n7 between the source voltage V_dd and earth. The transistors T_p7 and T_n7 have their interconnected drains connected to the output Z. The gates of the transistors T_p3, T_p ,T_p7 are interconnected, and so are the gates of the transistors T_n3, T_n4,T_n7.

A quite crucial part of the ciruitry according to the invention is the conveyor 7 which stabilizes the potential of high-capacitance nodes. In order to save power, class AB is a good choice, as is provided in the embodiment shown in Fig. 3.

When there is a positive or negative going current i being forced into the input X, it splits into the upper and lower branches. To the first order, the currents flowing through transistors T_p3, T_p4 are equal, because the transistors have the same dimension ratios and the same gate/source voltage. The currents flowing through T_n3, T_n4 are equal too. The transistors T_p7 and T_n7 are controlled by the voltages at the drains of the transistors T_p3 and T_n3, respectively, in the circuit 7b. The currents in the two branches combine at the output Z resulting in an output current i_out having the same current value and reverse direction as the input current I_in. Since the current flowing through T_p3,T_n5 is equal to that flowing through T_p4 and T_n6, T_n5 and T_n6 must have the same gate/source voltage. This forces the potential of the input X equal to that of input Y. The same statement holds with the lower branch as well.

When we consider the power consumption, consideration must be taken to the v/i converter 2. Suppose the conveyor 7 has a quiescent current I_. Due to the match of transistors, the drain current of T_p3 is I_q/3. If a current I_in flows from the v/i converter 2 into the input X of the conveyor 7, the drain current of T_p3 decreases to I_q/3 - I _n/ assuming the input current equally splits into the upper and lower branches. Therefore the conveyor 7 draws a current 3 (I_q/3 - I_in/2) from the power supply and the v/i converter 2 draws a current I_in from the power supply. If there is a current I_in flowing from the input X of the conveyor 7 to the v/i converter, the drain current of T_p3 increases to I_q/3 + I_in/2. Therefore the conveyor draws a current (I_q/3 + I_in /2) from the power supply and the v/i converter does not draw current from power supply. As an average, the power consumption by the v/i converter 2 and the current conveyor 7 can be estimated by

where I_ is the quiescent current of the current conveyor 7 and I_in is the value of the current generated by the v/i converter 2.

It is seen from equation (4) that the power consumption is independent of the operation frequency and high capacitances.

The delay time can be estimated as the time taken to change the gate voltages of T_p7 and T_n7 in order to accommodate the input current with minimum-sized transistors, the delay time is usually less than 1 ns. However, finite input conductance of the current conveyor may limit the speed due to the small voltage "ariation. The input conductance can be increased by proper design. Also, the speed can be increased.

Since only the direction of the current needs be sensed, a simple inverter can be used as the i/v converter 5. It functions as a 1-bit current quantizer.

The series connection of the source/drain path of p-type CMOS transistor T_p8 and the drain/source path of a n/type CMOS transistor T_n8 is connected between the voltage source V_dd and earth. The current i_out from the conveyor 7 is connected to the interconnected gates of the transistors T_p8 and T_n8. The varying voltage output v_out is provided at the interconnected drains of the transistors T_p8 and T_n8.

When the output current i_c from the conveyor 7 flows into the i/v converter 5, it charges the parasitic capacitor at the input node making the potential ramp up till V_dd. An output voltage equal to OV is thus generated. When the input current i_c flows from the i/v converter 5, it discharges the parasitic capacitor at the input node making the potential ramp down till 0. An output voltage equal to V_dd is thus generated. Thus the output signal v_out is a voltage signal varying between V_dd and O volt.

Suppose that the load to the i/v converter 5 is a minimum- sized inverter. According to Eq. (1) , the typical value of the power consumption of the i/v converter is less than 30 W even with a frequency around 100 MHz.

The power consumption of the inventive circuitry is determined by the power consumption of the v/i, the converter, the current conveyor and the i/v converter. Since the power consumed by driving the v/i converter and by driving the load of the i/v converter is very small, the power consumption of the approach is approximately equal to P₁ of Eq. (4) . Therefore, the high capacitance of communicating nodes has no influence on the power consumption and the power consumption of the approach is almost independent of the operation frequency.

In Fig. 4, measurement results, curve A, of the power consumption provided at experiment with the invention are compared with the power consumption, curve B, provided for ordinary voltage-mode transfer through a high-capacitance node. The power consumption when using the inventive idea is practically independent of operation frequency. At a frequency around 5MHz, the proposed method can save power by 40 times.

While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the invention. In addition, modifications may be made without departing from the essential teachings of the invention as expressed in the accompanying claims.

Claims

We claim:

1. A method for avoiding the influence of a high-capacitance node on digital signal transfer in relation to a VLSI-circuit chip, for instance a CMOS-chip, characterized in that a digital signal having voltage swing is converted to a digital signal having current swing and stabilized potential at the input of said node and that said current swing signal is converted back to a voltage swing signal at the output of said node.

2. A method according to Claim 1, characterized in that said current swing is between currents having different directions.

3. A method according to Claim 1 or 2, characterized in that said stabilized potential is provided as a current conveyance at the output of said node before said current swing signal is converted back to said voltage swing signal.

4. An arrangement for avoiding the influence of a high- capacitance node on digital signal transfer in relation to a VLSI-circuit chip, for instance a CMOS-chip, characterized in a voltage/current converter (2) converting a digital signal having voltage swing to a digital signal having current swing connected to an input of said node, a current/voltage converter (5) converting said current swing signal is converted back to a voltage swing signal connected at the output of said node, means for stabilizing the potential at said node.

5. An arrangement according to Claim 4, characterized in that said voltage/current converter (2) converts said voltage swing digital signal into a current swing signal, the swing going between mutually opposed current directions.

6. An arrangement according to claim 5, characterized in that said potential stabilizing means is a current conveyor (7) having a high input conductance.

7. An arrangement according to claim 5 or 6, characterized in that said potential stabilizing means is a current conveyor (7) having a first circuit (7a) indicating the current direction of its input current from said node and regulating the voltage level of said node to a reference voltage V_ref, and a second circuit (7b) controlled by said first circuit to provide an output current having a current swing in close relation to the input current.

8. An arrangement according to claim 7, characterized in that said output current from said second circuit (7b) is adapted to have the samve current value and reversed direction as the input current to said current conveyor (7) .

9. Method according to any of the claims 1 - 3, characterized in that the current swing is between different current directions.

10. Method according to claim 9, characterized in different current directions corresponding to the transfer of the binary bit "l" and "0" respectively.

11. An arrangement according to any of the claims 4 - 7, characterized in that the current swing is between different current directions.

12. An arrangement according to claim 11, characterized in the binary bits "1" and "0" corresponding to different current directions.