WO1996001496A1 - Method of manufacturing a semiconductor device with a moisture impermeable barrier layer - Google Patents

Method of manufacturing a semiconductor device with a moisture impermeable barrier layer Download PDF

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Publication number
WO1996001496A1
WO1996001496A1 PCT/GB1995/001571 GB9501571W WO9601496A1 WO 1996001496 A1 WO1996001496 A1 WO 1996001496A1 GB 9501571 W GB9501571 W GB 9501571W WO 9601496 A1 WO9601496 A1 WO 9601496A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
aluminium
track
barrier
tracks
Prior art date
Application number
PCT/GB1995/001571
Other languages
French (fr)
Inventor
Adrian Kiermasz
Christopher David Dobson
Original Assignee
Electrotech Equipments Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Electrotech Equipments Limited filed Critical Electrotech Equipments Limited
Publication of WO1996001496A1 publication Critical patent/WO1996001496A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to the manufacture of semiconductor devices and in particular, but not exclusively, to such devices which include aluminium tracks deposited on a dielectric layer.
  • aluminium is to be understood to include aluminium alloys.
  • Most semiconductor devices are made up of a multilayer sandwich of dielectric layers. * At least some of these have electrically conducting aluminium tracks deposited on their upper surface and interconnections between tracks at different levels may be made by vias, through the dielectric between the tracks. It is common, as the sandwich is built up, for the dielectric materials to be heated up during processing, which may cause the material to give off various forms of moisture H 2 0, OH and/or hydrogen, if it has not been adequately removed in a previous step. The resultant change in bonding within the material causes stress changes in the material and typically degradation of the aluminium track occurs. Thus, the track may suffer voids or may notch (for example in the manner sometimes known as "mouse bites”) .
  • the invention includes a method of manufacturing a semiconductor device, including the step of forming an impermeable barrier to moisture between an aluminium track and any adjacent moisture containing layer.
  • the barrier will usually only need to be formed over the upper surface of the track and adjacent portions of the upper surface of the layer on which the track sits (hereinafter referred to as the under layer) . Indeed once the immediately adjacent upper layer has been deposited and had its moisture removed the barrier may be broken, for example to allow for connections to be formed with overlying tracks.
  • the invention consists in a method of forming a semiconductor device having an aluminium track, the method including forming a water impermeable layer over the aluminium track and the under layer prior to deposition of a further dielectric layer.
  • the invention includes a method of manufacturing a semiconductor device which may include depositing an under layer of dielectric material, heating the layer, if necessary, to remove excess moisture, depositing an aluminium or aluminium alloy track on the upper surface of the under layer, depositing a thin water impermeable layer over the track and under layer surface and depositing a further layer of dielectric material over the thin impermeable layer.
  • the barrier is kept thin so that it does not introduce any stress/moisture problem itself. Preferably it is 500A or below thick.
  • the barrier or water impermeable layer may be silicon nitride, a silicon oxynitride or silicon carbide or a combination of these.
  • the further layer may be heated to remove moisture from it and may later be etched to form connections with subsequent overlying aluminium tracks.
  • a semiconductor device is schematically illustrated at 10 and includes an under layer 11 of dielectric material, aluminium tracks 12 and further deposited dielectric layers 13 to 17.
  • Layers 13 and 15 are planarisation layers for evening out the hills and valleys created by the aluminium tracks;
  • layers 14 and 16 are capping layers and
  • layer 17 is a passivation layer.
  • the under layer 11 is duly formed, for example by spin-on glass techniques or high temperature reflow of boron and phosphorous doped silicon oxide (BPSG) , and then etched to provide connection vias 19, 20.
  • the under layer 11 might be further heated to remove any excess moisture.
  • the aluminium tracks 12 are then deposited on the upper surface 21 of the under layer 11 and this is followed by the deposition of an extremely thin layer or barrier 22 of silicon nitride (for example by plasma chemical vapour deposition) which extends over the upper surface 21 of the base layer 11 and over the exposed surface of the aluminium tracks 12.
  • the silicon nitride layer 22 is water impermeable and so effectively seals the tracks at that stage.
  • dielectric layers 13, 14 are then deposited and are subsequently heated so that their excess moisture is removed as mentioned above. Although this removal of moisture will cause stress within the layer 13, this in itself does not appear to be sufficient to create degradation, such as voiding or mouse bites in the aluminium. It is believed this is because the moisture coming out of the layers 13, 14 cannot reach the aluminium or possibly the interface between the aluminium and the upper surface 21 of the under layer 11.
  • the layers 13, 14 can then be etched to provide a further connection via 23 and subsequently aluminium track 24 is deposited and once again is given a silicon nitride coating.
  • the barrier layer 22 may subsequently be deposited onto further metal structures. Barrier 25 and metal layers 24 for example can be provided, and so on throughout the device as many as is necessary. The layers 13 and 14 then become the under layer.
  • any water impermeable substance which can be readily deposited in the normal conditions applying during the manufacture of a semiconductor device, may be used.
  • silicon oxynitrides and silicon carbide may be used.
  • the layer should be very thin so that, in itself, it does not induce stress within the aluminium nor carry significant quantities of excess moisture.
  • the layer or barrier 22, 25 will be 500A or less.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

This invention relates to the manufacture of semiconductor devices and in particular to such devices which include aluminium tracks deposited on a dielectric layer. A semiconductor device is schematically illustrated at (10) and includes an under layer (11) or dielectric material, aluminium tracks (12) and further deposited dielectric layers (13-17). Layers (13 and 15) are planarisation layers; layers (14 and 16) are capping layers and layer (17) is a passivation layer. The under layer (11) is typically heated, after formation, to remove any excess moisture and the aluminium tracks (12) are then deposited. A barrier layer (22) is then deposited prior to the deposition of the subsequent dielectric layer (13).

Description

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A MOISTURE
IMPERMEABLE BARRIER LAYER.
This invention relates to the manufacture of semiconductor devices and in particular, but not exclusively, to such devices which include aluminium tracks deposited on a dielectric layer. .For the purposes of this specification the term aluminium is to be understood to include aluminium alloys.
Most semiconductor devices are made up of a multilayer sandwich of dielectric layers. *At least some of these have electrically conducting aluminium tracks deposited on their upper surface and interconnections between tracks at different levels may be made by vias, through the dielectric between the tracks. It is common, as the sandwich is built up, for the dielectric materials to be heated up during processing, which may cause the material to give off various forms of moisture H20, OH and/or hydrogen, if it has not been adequately removed in a previous step. The resultant change in bonding within the material causes stress changes in the material and typically degradation of the aluminium track occurs. Thus, the track may suffer voids or may notch (for example in the manner sometimes known as "mouse bites") .
The Applicant has discovered that in addition to stress, moisture surprisingly also plays a significant role in the degradation and indeed its presence may form an essential component of the degradation process.
Accordingly the invention includes a method of manufacturing a semiconductor device, including the step of forming an impermeable barrier to moisture between an aluminium track and any adjacent moisture containing layer. Usually it will only be the layers deposited after the aluminium tracks are formed which will contain damaging, releasable moisture and so the barrier will usually only need to be formed over the upper surface of the track and adjacent portions of the upper surface of the layer on which the track sits (hereinafter referred to as the under layer) . Indeed once the immediately adjacent upper layer has been deposited and had its moisture removed the barrier may be broken, for example to allow for connections to be formed with overlying tracks.
It is possible that the effect of the moisture is particularly significant at the interface between the aluminium track and the under layer and so it may be that a barrier covering this interface alone would suffice, but in general it will be easier, and more certain, simply to deposit a layer over the tracks and the upper surface of the under layer.
Thus, more specifically, the invention consists in a method of forming a semiconductor device having an aluminium track, the method including forming a water impermeable layer over the aluminium track and the under layer prior to deposition of a further dielectric layer. From another aspect, the invention includes a method of manufacturing a semiconductor device which may include depositing an under layer of dielectric material, heating the layer, if necessary, to remove excess moisture, depositing an aluminium or aluminium alloy track on the upper surface of the under layer, depositing a thin water impermeable layer over the track and under layer surface and depositing a further layer of dielectric material over the thin impermeable layer. The barrier is kept thin so that it does not introduce any stress/moisture problem itself. Preferably it is 500A or below thick. The barrier or water impermeable layer may be silicon nitride, a silicon oxynitride or silicon carbide or a combination of these. The further layer may be heated to remove moisture from it and may later be etched to form connections with subsequent overlying aluminium tracks.
Although the invention has been defined above it is to be understood that it includes any inventive combination of the features set out above of in the following description.
The invention may be performed in various ways and specific embodiments will now be described with reference to the following drawing, which is a schematic vertical section through a semiconductor device illustrating features of the invention.
A semiconductor device is schematically illustrated at 10 and includes an under layer 11 of dielectric material, aluminium tracks 12 and further deposited dielectric layers 13 to 17. Layers 13 and 15 are planarisation layers for evening out the hills and valleys created by the aluminium tracks; layers 14 and 16 are capping layers and layer 17 is a passivation layer.
In the method of the invention the under layer 11 is duly formed, for example by spin-on glass techniques or high temperature reflow of boron and phosphorous doped silicon oxide (BPSG) , and then etched to provide connection vias 19, 20. The under layer 11 might be further heated to remove any excess moisture. The aluminium tracks 12 are then deposited on the upper surface 21 of the under layer 11 and this is followed by the deposition of an extremely thin layer or barrier 22 of silicon nitride (for example by plasma chemical vapour deposition) which extends over the upper surface 21 of the base layer 11 and over the exposed surface of the aluminium tracks 12. The silicon nitride layer 22 is water impermeable and so effectively seals the tracks at that stage.
Further dielectric layers 13, 14 are then deposited and are subsequently heated so that their excess moisture is removed as mentioned above. Although this removal of moisture will cause stress within the layer 13, this in itself does not appear to be sufficient to create degradation, such as voiding or mouse bites in the aluminium. It is believed this is because the moisture coming out of the layers 13, 14 cannot reach the aluminium or possibly the interface between the aluminium and the upper surface 21 of the under layer 11. The layers 13, 14 can then be etched to provide a further connection via 23 and subsequently aluminium track 24 is deposited and once again is given a silicon nitride coating. The barrier layer 22 may subsequently be deposited onto further metal structures. Barrier 25 and metal layers 24 for example can be provided, and so on throughout the device as many as is necessary. The layers 13 and 14 then become the under layer.
It is believed that any water impermeable substance, which can be readily deposited in the normal conditions applying during the manufacture of a semiconductor device, may be used. For example silicon oxynitrides and silicon carbide. In general the layer should be very thin so that, in itself, it does not induce stress within the aluminium nor carry significant quantities of excess moisture. Typically the layer or barrier 22, 25 will be 500A or less.

Claims

Claims
1. A method of manufacturing a semi-conductor device, including the step of forming an impermeable barrier between an aluminium track and any adjacent moisture containing layer.
2. A method as claimed in Claim 1 wherein the barrier is formed over the upper surface of the track and adjacent portions of the upper surface of the layer (under layer) on which the tracks sits.
3. A method as claimed in Claim 2 wherein a single layer is deposited over a track or tracks and the upper surface of the under layer.
4. A method as claimed in Claim 1 wherein the barrier is formed at the interface between the aluminium track and the upper surface of the layer (under layer) on which the tracks sits.
5. A method of forming a semi-conductor device having an aluminium track, the method including forming a water impermeable layer over the aluminium track and the layer (under layer) on which it sits prior to deposition of a further dielectic layer.
6. A method of manufacturing a semi-conductor device which includes depositing an under layer of dielectic material, heating the under layer or otherwise removing excess moisture, depositing an aluminium track on the upper surface of the under layer, depositing a thin water impermeable layer on the track and on the under layer surface and depositing a further layer of dielectic material over the thin impermeable layer.
7. A method as claimed in any one of the preceding claims wherein the barrier layer is 50θA or below thick.
8. A method as claimed in any one of the preceding claims wherein the barrier or water impermeable layer is made of silicon nitride, a silicon oxynitride or silicon carbide or a combination of these.
9. A method as claimed in any one of the preceding claims wherein the further layer is heated to remove moisture from it and subsequently etched to form connections with subsequent overlying aluminium tracks.
PCT/GB1995/001571 1994-07-06 1995-07-04 Method of manufacturing a semiconductor device with a moisture impermeable barrier layer WO1996001496A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9413568A GB9413568D0 (en) 1994-07-06 1994-07-06 Semiconductor devices
GB9413568.8 1994-07-06

Publications (1)

Publication Number Publication Date
WO1996001496A1 true WO1996001496A1 (en) 1996-01-18

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PCT/GB1995/001571 WO1996001496A1 (en) 1994-07-06 1995-07-04 Method of manufacturing a semiconductor device with a moisture impermeable barrier layer

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GB (1) GB9413568D0 (en)
WO (1) WO1996001496A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1099245A1 (en) * 1999-05-06 2001-05-16 Koninklijke Philips Electronics N.V. Moisture repellant integrated circuit dielectric material combination
US11808725B2 (en) * 2018-07-18 2023-11-07 B-Horizon GmbH Apparatus for measuring pressure and/or humidity

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5284801A (en) * 1992-07-22 1994-02-08 Vlsi Technology, Inc. Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric
US5306936A (en) * 1992-08-05 1994-04-26 Nec Corporation Non-volatile semiconductor memory device having oxynitride film for preventing charge in floating gate from loss

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5284801A (en) * 1992-07-22 1994-02-08 Vlsi Technology, Inc. Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric
US5306936A (en) * 1992-08-05 1994-04-26 Nec Corporation Non-volatile semiconductor memory device having oxynitride film for preventing charge in floating gate from loss

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
STOLLER A I ET AL: "A novel technique for forming glass-to-metal seals using a silicon nitride interface layer", RCA REVIEW, JUNE 1970, USA, vol. 31, no. 2, ISSN 0033-6831, pages 443 - 449 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1099245A1 (en) * 1999-05-06 2001-05-16 Koninklijke Philips Electronics N.V. Moisture repellant integrated circuit dielectric material combination
EP1099245A4 (en) * 1999-05-06 2006-06-21 Koninkl Philips Electronics Nv Moisture repellant integrated circuit dielectric material combination
US11808725B2 (en) * 2018-07-18 2023-11-07 B-Horizon GmbH Apparatus for measuring pressure and/or humidity

Also Published As

Publication number Publication date
GB9413568D0 (en) 1994-08-24

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