WO1995022791A3 - Method and apparatus for single cycle cache access on double word boundary cross - Google Patents

Method and apparatus for single cycle cache access on double word boundary cross Download PDF

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Publication number
WO1995022791A3
WO1995022791A3 PCT/US1995/001779 US9501779W WO9522791A3 WO 1995022791 A3 WO1995022791 A3 WO 1995022791A3 US 9501779 W US9501779 W US 9501779W WO 9522791 A3 WO9522791 A3 WO 9522791A3
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WO
WIPO (PCT)
Prior art keywords
data
cache
single cycle
cache memory
word boundary
Prior art date
Application number
PCT/US1995/001779
Other languages
French (fr)
Other versions
WO1995022791A2 (en
Inventor
Graham B Whitted Iii
James A Kane
Hsiao-Shih Chang
Original Assignee
Meridian Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meridian Semiconductor Inc filed Critical Meridian Semiconductor Inc
Publication of WO1995022791A2 publication Critical patent/WO1995022791A2/en
Publication of WO1995022791A3 publication Critical patent/WO1995022791A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A cache memory system and method control a random access read/write cache memory (122) that stores a plurality of cache data lines (148). The bytes in each cache data line (148) correspond to bytes stored in sequential addresses in a main memory (104). The cache memory (122) is organized to provide storage of a plurality of double words in each cache data line (148). To retain main memory consistency, input circuitry receives and aligns data before storage in the cache memory (122). A separate instruction output path (114) provides access to a plurality of double words in a single cycle. A separate data output path (112) provides access to data that crosses a double word boundary in a single cycle and provides the data as aligned data.
PCT/US1995/001779 1994-02-08 1995-02-08 Method and apparatus for single cycle cache access on double word boundary cross WO1995022791A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US19338394A 1994-02-08 1994-02-08
US08/193,383 1994-02-08

Publications (2)

Publication Number Publication Date
WO1995022791A2 WO1995022791A2 (en) 1995-08-24
WO1995022791A3 true WO1995022791A3 (en) 1995-09-21

Family

ID=22713424

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1995/001779 WO1995022791A2 (en) 1994-02-08 1995-02-08 Method and apparatus for single cycle cache access on double word boundary cross

Country Status (2)

Country Link
TW (1) TW255024B (en)
WO (1) WO1995022791A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010023581A (en) * 1998-07-03 2001-03-26 인피니언 테크놀로지스 아게 Data storage device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4314332A (en) * 1978-03-15 1982-02-02 Tokyo Shibaura Denki Kabushiki Kaisha Memory control system
US4652991A (en) * 1978-08-22 1987-03-24 Nippon Electric Co., Ltd. Data transfer apparatus
US4814976A (en) * 1986-12-23 1989-03-21 Mips Computer Systems, Inc. RISC computer with unaligned reference handling and method for the same
US5386531A (en) * 1991-05-15 1995-01-31 International Business Machines Corporation Computer system accelerator for multi-word cross-boundary storage access

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4314332A (en) * 1978-03-15 1982-02-02 Tokyo Shibaura Denki Kabushiki Kaisha Memory control system
US4652991A (en) * 1978-08-22 1987-03-24 Nippon Electric Co., Ltd. Data transfer apparatus
US4814976A (en) * 1986-12-23 1989-03-21 Mips Computer Systems, Inc. RISC computer with unaligned reference handling and method for the same
US4814976C1 (en) * 1986-12-23 2002-06-04 Mips Tech Inc Risc computer with unaligned reference handling and method for the same
US5386531A (en) * 1991-05-15 1995-01-31 International Business Machines Corporation Computer system accelerator for multi-word cross-boundary storage access

Also Published As

Publication number Publication date
TW255024B (en) 1995-08-21
WO1995022791A2 (en) 1995-08-24

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