WO1995018357A1

WO1995018357A1 - Embedded programmable sensor calibration apparatus

Info

Publication number: WO1995018357A1
Application number: PCT/US1994/014957
Authority: WO
Inventors: Robert D. Juntunen
Original assignee: Honeywell Inc.
Priority date: 1993-12-30
Filing date: 1994-12-28
Publication date: 1995-07-06
Also published as: AU1446695A; JPH09507295A; KR970700312A; KR100327809B1; EP0737301A1; CA2178936A1; AU697904B2

Abstract

An apparatus for quick and low cost calibration of a sensor. The device includes an amplifier, a switch, a gain circuit, an offset circuit and a memory. The memory, which may be serial written memory including static RAM and a shift register, stores gain and offset coefficients for use by the gain and offset circuits and the amplifier. The gain and offset circuits may include digital to analog converters for converting the stored gain and offset digital values into analog equivalents. The gain and offset values are calculated by first measuring an uncorrected sensor output at no input and at full scale output. These values are then used in an equation to calculate offset and gain values.

Description

EMBEDDED PROGRAMMABLE SENSOR CALIBRATION APPARATUS
BACKGROUND OF THE INVENTION
The present invention relates to the field of sensors and is more particularly directed to the area of calibration of sensors. This application is related to United States
Patent Application Serial Number 08/175,908 entitled EMBEDDED
PROGRAMMABLE SENSOR CALIBRATION METHOD, filed 30 December 1993 and assigned to Honeywell Inc.

Since the inception of electronic sensors, calibration of sensors have imposed a substantial cost on sensor cost to the end user of the sensor. Generally, three calibrations were required depending upon the end use of the sensor.

An initial calibration was usually performed by the sensor manufacturer to make sure that broad desired tolerances are met. This calibration process in current times involved laser tailoring of a bias resistor network to a desired resistance. This process typically would require multiple passes and total elapsed times in excess of 20 seconds when using median grade performance equipment.

Next, an original equipment manufacturer (OEM) would perform a calibration to ensure that the sensor met its needs. This was usually done by including at least one multi-turn potentiometer with the sensor and adjusting the potentiometer in a well known way until the desired performance characteristics were achieved. Finally, an epoxy could be placed on the potentiometer to freeze the setting. This was an expensive process.

Lastly, performance characteristics of sensors were affected by the conditions in which they were used in the field. Accordingly, field calibration was necessary to ensure that sensor performance was acceptable once the sensor was installed in its intended application. Usually, this calibration involved further adjustments to mult- turn potentiometers.

One particular sensor of interest here was a flow sensor. Flow sensors were often used in Heating, Ventilating and Air Conditioning applications for, as an example, measuring air flow through ducts. This information could be used to control the temperature of a controlled room. Typically, such sensors were located within a HVAC controller. The controller typically operated on instructions stored by a memory and executed by a clocked arithmetic logic unit (ALU). The controller itself could be located within the overhead space of the room. This could make manual adjustment of potentiometers difficult once the controller was installed.

Accordingly, it is an object of the present invention to substantially eliminate the need for factory laser trimming of resistors during the calibration of sensors. It is a further object of the present invention to substantially reduce the need for using potentiometers to calibrate the sensor. It is yet another object of the present invention to reduce the cost of calibrating the sensor. It is still another object of the present invention to reduce the manual labor required to calibrate the sensor.

SUMMARY OF THE INVENTION
The present invention is an apparatus for calibrating a sensor which is used in connection with a clocked ALU and memory. The invention includes an amplifier means for amplifying signals received from the sensor, a reference voltage supply for connection to the sensor and connected to the amplifier means, an offset circuit connected to the amplifier and for connection to the ALU and memory for adjusting the gain of the amplifier to correct for a known offset, a gain circuit connected to the amplifier means and for connection to the ALU and memory for adjusting the gain of the amplifier means based upon a desired full scale output and a switching means connected to the amplifier means, the gain circuit and the ALU for multi-plexing a preamplifier output and a programmable amplifier output.

At manufacture, an uncalibrated output, at a zero input level of the sensor, is generated and the output voltage of the sensor is recorded. The sensor is then stimulated at its top input level and the output voltage is again recorded. These are commonly known as the null and full scale output specifications of the sensor. Coefficients are then calculated for use in the programmable amplifier to bring the null and full scale amplified outputs within a usable range for a desired analog to digital converter.

BRIEF DESCRIPTION OF THE DRAWING
Figure 1 is a block diagram of a controller which incorporates the inventive system.

Figure 2 is a block diagram of the inventive circuit.

Figure 3 is a schematic diagram of one embodiment of the inventive circuit connected to a representative sensor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to Figure 1, there shown is a controller 10 which incorporates the inventive apparatus. The controller 10 includes a sensor 15 connected to a calibration circuit 20. The calibration circuit 20 is connected to analog to digital converter 22, arithmetic logic unit (ALU) 35, memory 25 and input/output port 40. The ALU is connected to a clock 30.

In operation, sensor 15 produces a sensor signal representative of a condition to be sensed. The sensor is connected to a calibration circuit 20 which uses an algorithm for correcting the sensor signal at null input and full scale output (FSO) variations. A digitized version of the corrected circuit is then sent to the ALU through analog to digital converter 22. Coefficients used in the algorithm are stored in memory 25.

Memory 25, which may include both read only memory and random access memory, also stores instructions upon which ALU 35 operates. ALU 35, which may be a microprocessor, micro controller, microcomputer or the like, receives the corrected signal and instructions from the memory and produces a control signal which is sent out to a controlled device (not shown) through input output port 40. To. ensure orderly operation and communications, clock 30 provides a timing signal which is used by all of the components of the controller.

Referring now to Figure 2, there shown is a block diagram of the inventive calibration circuit 20. It includes amplifier means 205, reference voltage generator 210, offset means 215, gain means 220 switch means 225 and memory 230. Amplifier 205 receives the sensor signal and amplifies the sensor signal to levels which can be used by the ALU. Amplifier 205 also amplifies the signal according to signals received from offset means 215 and gain means 220 to adjust the output signal to achieve desired span and offset characteristics. Reference voltage means 210 produces a reference voltage which is used by the sensor 15, the amplifier 205 and the offset means 215. By biasing these devices using a common reference voltage, the circuits will be subject to common variations in reference voltage which may be induce by temperature changes.

Therefore, temperature effects on these circuits are ratiometrically canceled.

The switch means 225, gain means 220 and offset means 215 are controlled by information stored in memory 230. This information is supplied to the memory each time the sensor is started up from memory 25. Memory 230 may have components of
Static RAM (SRAM), Non-Volatile Ram (NOVRAM) and Electrically Erasable
Programmable ROM (EEPROM). The switch means 225 controls whether a corrected or amplified but uncorrected sensor signal is output from the Amplifier means 205 based on input received from the memory 230. Offset means 215 receives stored coefficients from memory 230 to correct the sensor signal for offset error. Gain means 220 receives coefficients from the memory 230 to correct the sensor signal for errors in the full scale output signal. More detail on this will be provided with reference to Figure 3.

Referring now to Figure 3, there shown is a schematic diagram of a sensor 15 and the calibration circuit 20. The calibration circuit is further broken down and depicts a preferred embodiment of the invention. The amplifier means 205 includes preamplifier 305 and amplifier 308. The pre-amplifier is used to scale the sensor output signal to levels which are usable by the ALU. Amplifier 308 may be programmable to a desired gain level and is affected by the output of the offset means 215 and the gain means 220.

Offset means 215 includes a digital to analog converter. Gain means 220 includes resistor R1 and gain section 221.

Memory 230 includes digital to analog converter memory section 316, gain memory section 321 and latch memory section 322. These memory sections take the form of serial written memory.

Switch means 225 includes switches 325 and 326 and not gate 327. Analog to digital converter 350 is used to convert the output signal to a fonn which can be stored and used by the ALU.

Gain section 221 in a preferred embodiment is a ladder type digital to analog converter having a desired transfer function. The same is true for digital to analog converter 215. The selection of the transfer function and structure of these converters is a matter of design choice for the specific application and is well known to those of ordinary skill in the art. In the present invention, these converters are constructed of seven resistors which can be selectively chosen to create a desired resistance.

Sensor 15 may be any sensor designed to produce a differential output signal.

Here, the flow sensor is configured as a Wheatstone Bridge with resistors Rb l, Rb2,
Rfsl and Rfs2 as the legs of the bridge. Resistor Rb3 provides level shifting of the differential voltage developed at the positive and negative inputs of pre-amplifier 305.

The sensor may be a flow sensor such as the Honeywell AWM series of flow sensors. It is important to note that the sensor described herein is exemplary and while the sensor may be connected to the present invention, it in no way is a part of the present invention.

At time for calibration, the invention operates as follows. First, switch 325 is enabled and switch 326 is disabled by writing a 1 to the first bit of the serial written memory. All other bits are don't cares at this point.

Next, the sensor is placed in a condition where zero stimulus is applied to the sensor (0 input level) and the sensor output value is stored in memory (Vlo). The sensor is then stimulated at a level in which it is to produce a full scale output and the sensor output value is stored in memory (Vhi).

These two values are then plugged into the equation:
Vr=(Vlo*Vhi-Vlo*Vo 1 -Vhi*Vlo+Vhi*Vo2)/(Vhi-Vo 1 -Vlo+Vo2);
Where, Vo2 is the desired voltage output at 0 sensor input (in a preferred embodiment, 0.50Vdc);
Vol is the desired voltage output at full scale output( in a preferred embodiment, 4.50 Vdc); and
Vr is the required offset voltage.

Next, the gain can be calculated using the Or just calculated:
Rf=((Vhi-Vo l )*Rl )/(Vr-Vhi); and
Gain'= Rf/Rp.

The value of R1 is chosen such that the desired output of the programmable amplifier and the gain section are achieved. The method of picking such a resistor is well known to those of ordinary skill in the art: here, the applicant has chosen R1=4990 Ohms.

Note that the term "Gain"' refers only to the ratio of Rf to R1, the true output voltage of amplifier 308 is defined as Vo = (Gain'+l) * Vin+Vr * (Gain'). Vin is the output of the pre-amplifier.

It should be noted that the switch means 225 and latch memory section are not necessary in the basic embodiment of the present invention. These'functions may be implemented by a circuit connected to the sensor output only during calibration. Once calibration is completed, these functions are no longer necessary and the external circuit could be disconnected. The Vr and Gain' values could then still be loaded as described herein.

Once the gain and Vr values are determined, decimal equivalent values of Gain' and Vr can be calculated. These values are dependent upon the transfer function and resolution of the gain section, and the analog to digital converter. In the present case:
Dec(Offset)= Int ((Vref * 12.8/Vr)-44.8)).

Dec(gain) = Int((336/Gain')-32+ 0.1)
(Vref is, in a preferred embodiment, = 5 .45V)
Next, the decimal codes just calculated are arranged with the offset code first, the gain code second, and a 0 as the last bit in order to shut off the switch 325 and turn on switch 326. The codes are then put into the memory sections and the corrected sensor output signal is checked against the desired null and full scale output levels by again stimulating the sensor at these levels. If the output levels at these input levels meet the predefined criteria, the offset and gain decimal codes are stored in memory 25 and are used during the operation of the sensor.

At startup of the sensor, the digital values of Vr and Gain' are loaded from memory 25 to the appropriate memory sections in memory 230 (Vr in digital to analog converter memory section 316, Gain' in gain section memory 321 and a digital one in latch memory section 322. Thereafter, the corrected output signal sent to analog to digital converter 350 is corrected by the Gain' and Vr values through the circuit shown in Figure 3.

The foregoing has been a description of a novel and non-obvious apparatus for correcting a sensor signal for offset and null errors. Many minor variations which fall within the spirit of the invention will be obvious to those of ordinary skill in the art.

The applicant does not intend for the description to be limiting but instead define the limits of their invention through the claims appended hereto.

Claims

1. Apparatus for correcting offset and span errors in a sensor, comprising: memory for receiving and storing an offset correction value for correcting a sensor output signal for offset errors and a span correction value for correcting the sensor output signal for span errors; offset means, connected to said memory, for converting said offset value to an analog signal; gain means, connected to said memory, for converting said gain value to an analog signal of a desired level; and amplifier means connected to the sensor, said gain means, said offset means and said memory, said amplifier means amplifying the sensor output signal to a first desired level and further amplifying the sensor output signal by analog equivalent signals which are substantial equivalents of said gain and offset values.

2. The apparatus of claim 1, wherein said memory comprises serial written memory.

3. The apparatus of claim 2, wherein said serial written memory is comprised of: a static random access memory (SRAM) connected to a shift register, said SRAM continually providing a constant value to said shift register after start-up of the apparatus.

4. The apparatus of claim 3, wherein: there are first and second SRAMs and shift registers, said first SRAM and shift register storing and shifting said offset value respectively and said second SRAM and shift register storing and shifting said gain value respectively.

5. The apparatus of claim 1, further comprising: a switch connected to said memory and said amplifier said memory sending a value to said switch which causes the amplifier to output the sensor output signal at said first desired level during calibration of the sensor.

6. The apparatus of claim 5, wherein said memory comprises serial written memory.

7. The apparatus of claim 6, wherein said serial written memory is comprised of: a static random access memory (SRAM) connected to a shift register, said SRAM continually providing a constant value to said shift register after start-up of the apparatus.

8. The apparatus of claim 7, wherein: there are first, second and third SRAMs and shift registers, said first SRAM and shift register storing and shifting said offset value respectively, said second SRAM and shift register storing and shifting said gain value respectively and said third SRAM and shift register storing and shifting a desired switch value for causing a desired amplifier output.

9. The apparatus of claim 1, wherein said gain means and said offset means comprise ladder type digital to analog converters.

10. The apparatus of claim 9, wherein said memory comprises serial written memory.

11. The apparatus of claim 10, wherein said serial written memory is comprised of: a static random access memory (SRAM) connected to a shift register, said SRAM continually providing a constant value to said shift register after start-up of the apparatus.

12. The apparatus of claim 11, wherein: there are first and second SRAMs and shift registers, said first SRAM and shift register storing and shifting said offset value respectively and said second SRAM and shift register storing and shifting said gain value respectively.

13. The apparatus of claim 9, further comprising: a switch connected to said memory and said amplifier, said memory sending a value to said switch which causes the amplifier to output the sensor output signal at said first desired level during calibration of the sensor.

14. The apparatus of claim 13, wherein said memory comprises serial written memory.

15. The apparatus of claim 14, wherein said serial written memory is comprised of: a static random access memory (SRAM) connected to a shift register, said SRAM continually providing a constant value to said shift register after start-up of the apparatus.

16. The apparatus of claim 15, wherein: there are first, second and third SRAMs and shift registers, said first SRAM and shift register storing and shifting said offset value respectively, said second SRAM and shift register storing and shifting said gain value respectively and said third SRAM and shift register storing and shifting a desired switch value for causing a desired amplifier output.

17. The apparatus of claim 1, wherein said amplifier means comprises: a preamplifier having input terminals connected to sensor output terminals and an output terminal, said preamplifier having a fixed gain; and a programmable amplifier having a first input terminal connected to said output terminal of said preamplifier and a second input terminal connected to said offset means and said gain means for receiving said analog equivalent signals, said programmable amplifier having an output terminal at which a corrected sensor signal, which is a function of said analog equivalent values, is produced.

18. The apparatus of claim 17, wherein said memory comprises serial written memory.

19. The apparatus of claim 2, wherein said serial written memory is comprised of: a static random access memory (SRAM) connected to a shift register, said SRAM continually providing a constant value to said shift register after start-up of the apparatus.

20. The apparatus of claim 19, wherein: there are first and second SRAMs and shift registers, said first SRAM and shift register storing and shifting said offset value respectively and said second SRAM and shift register storing and shifting said gain value respectively.

21. The apparatus of claim 17, further comprising: switch means connected to said memory and said output terminal of said preamplifier, said memory sending a value to said switch means which causes the signal appearing at the output terminal of said preamplifier to be an output signal for the apparatus during calibration of the sensor.

22. The apparatus of claim 21, wherein said memory comprises serial written memory.

23. The apparatus of claim 22, wherein said serial written memory is comprised of: a static random access memory (SRAM) connected to a shift register said SRAM continually providing a constant value to said shift register after start-up of the apparatus.

24. The apparatus of claim 23, wherein: there are first, second and third SRAMs and shift registers, said first SRAM and shift register storing and shifting said offset value respectively, said second SRAM and shift register storing and shifting said gain value respectively and said third SRAM and shift register storing and shifting a desired switch value for causing a desired amplifier output.

25. The apparatus of claim 17, wherein said gain means and said offset means comprise ladder type digital to analog converters.

26. The apparatus of claim 25, wherein said memory comprises serial written memory.

27. The apparatus of claim 26, wherein said serial written memory is comprised of: a static random access memory (SRAM) connected to a shift register, said SRAM continually providing a constant value to said shift register after start-up of the apparatus.

28. The apparatus of claim 27, wherein: there are first and second SRAMs and shift registers, said first SRAM and shift register storing and shifting said offset value respectively and said second SRAM and shift register storing and shifting said gain value respectively.

29. The apparatus of claim 25, further comprising: switch means connected to said memory and said output terminal of said preamplifier, said memory sending a value to said switch means which causes the signal appearing at the output terminal of said preamplifier to be an output signal for the apparatus during calibration of the sensor.

30. The apparatus of claim 29, wherein said memory comprises serial written memory.

31. The apparatus of claim 30, wherein said serial written memory is comprised of: a static random access memory (SRAM) connected to a shift register, said SRAM continually providing a constant value to said shift register after start-up of the apparatus.

32. The apparatus of claim 31, wherein: there are first, second and third SRAMs and shift registers, said first SRAM and shift register storing and shifting said offset value respectively, said second SRAM and shift register storing and shifting said gain value respectively and said third SRAM and

shift register storing and shifting a desired switch value for causing a desired amplifier output.