WO1995008862A1

WO1995008862A1 - Method and switching arrangement for starting a power supply

Info

Publication number: WO1995008862A1
Application number: PCT/FI1994/000422
Authority: WO
Inventors: Matti Havukainen
Original assignee: Nokia Telecommunications Oy
Priority date: 1993-09-22
Filing date: 1994-09-21
Publication date: 1995-03-30
Also published as: GB2297874A; DE4497069T1; FI94195B; FI934158A0; GB2297874B; GB9606136D0; AU7699394A; FI94195C

Abstract

The invention relates to a method and a circuit arrangement for switching on an electric load, in particular a power supply. The load is fed from a voltage source supplying an input voltage (Uac), and an input capacitor (Cin) is connected to the input terminals of the load (107). According to the method, (a) when the input voltage (Uac) is switched on, the operation is in the inrush mode, where the input capacitor (Cin) begins to be charged by means of a charging current (Ic) supplied by a constant-current generator circuit (108), when the input voltage (Uac) has exceeded its minimum value, and (b) after the input capacitor (Cin) is charged, a transition to the continuous mode following the start-up occurs. To switch on the load safely by means of equipment as simple as possible, information about the charging of the input capacitor (Cin) is derived from a change caused in the constant-current generator circuit by a drop in the charging current.

Description

Method and switching arrangement for starting a power supply

The invention relates to a method according to the preamble of the appended claim 1 and a circuit arrangement according to the preamble of the appended claim 4, for switching on an electric load, in particular a power supply. The purpose of the method and the device according to the invention is to limit the starting current supplied to the load at the start-up. The method and the circuit arrangement according to the invention are intended for use in particular in power supplies for telecommunication devices, which convert a direct voltage supplied by a battery or some other corresponding direct voltage source to a stabilized form by means of, for example, a switched-mode power supply. To eliminate short-term disturbances in the supply voltage, the input terminals of the power supply comprise one or more input capacitors.

At the start-up, when the input voltage is switched on from a battery or some other corresponding voltage source, the aforesaid capacitors represent a short circuit. Therefore, a limiting circuit is needed to limit the input current to a safe range at the moment of switching. The short-duration mode of operation which immediately follows the switching on of the input voltage and where current spikes exceeding the current of a normal mode are formed is often called an inrush mode. (In this connection, normal mode refers to the continuous operating mode after the inrush mode. )

Known current-limiting circuits are often based on the use of either NTC or PTC resistors. The drawback with limit circuits based on the use of NTC resistors is that there remains in the circuit a component (NTC resistor) causing dissipation even after the start-up, unless a separate shunting is used, which in turn complicates the circuit. When PTC resistors are used, a separate circuit is needed to detect when the capacitors are charged and the PTC resistors can be shunted. Such a circuit contains a large number of components and adds to the manufacturing costs.

US Patent 4,678,984 discloses a circuit arrangement limiting a power supply current, the arrangement having three operating modes: inrush mode, normal mode and overcurrent mode. When voltages are switched on, the circuit first starts operating in the inrush mode, where the voltage controlling the gate of a FET on the current path between the input voltage supply and the power supply is gradually increased. When the control voltage has exceeded its threshold value, a current begins to flow between the voltage supply and the power supply, and when the control voltage reaches its normal-mode value, a transition from the inrush mode to the normal mode occurs. However, it is not possible in this circuit to detect when the input capacitors are charged, but the start-up operation goes on, and if overcurrent situations occur, the device is driven via the overcurrent mode back to the inrush mode. The purpose of the present invention is to eliminate the above disadvantages and to provide a solution which makes it possible to start a power supply in a controlled and safe manner by means of simple equipment. This is achieved by means of a method according to the invention, which is characterized by what is described in the characterizing portion of the appended claim 1. A circuit arrangement according to the invention, in turn, is characterized by what is described in the characterizing portion of the appended claim 4. The idea of the invention is to derive information about the charging of input capacitor(s) from a change caused in the constant-current generator circuit by a drop in the charging current, and to utilize this change to effect the actual switching on of the load, i.e. the transition to normal mode.

By means of the solution according to the invention, reliable information about the charging of the input capacitor is obtained immediately and at the same time information about whether the voltages are within a range where the starting operation can be permitted to continue, in which case the power supply can be started safely and a transition to the normal mode can occur. A further advantage of the solution according to the invention is that the constant-current generator circuit also works in the normal mode as a current limiter, and it is also easy to provide it with a voltage limiting function. In the following, the invention and its preferred embodiments will be described in greater detail with reference to the examples according to the accompanying drawings, in which

Figure 1 is a block diagram of a circuit arrangement according to the invention,

Figure 2 represents one possible implementation of the constant-current generator circuit shown in Figure 1,

Figures 3a to 3f illustrate voltages/currents occurring in the circuit arrangement shown in Figure 1,

Figure 4 is a more detailed representation of the time-constant circuit shown in Figure 1, and

Figure 5 shows a voltage limit circuit added to the constant-current generator circuit. Figure 1 shows a functional block diagram of a circuit arrangement according to the invention, which operates as a current limit circuit when a power supply 107 is being started, the power supply being typically a switched-mode power supply, used widely at present due to their advantages, which include for example a high efficiency, a wide input voltage range and a possibility to implement compact and light power supplies. At present switched-mode power supplies utilize flyback topology more and more often (topology refers to the circuit configuration which determines how power is transferred in a power supply). The greatest advantage of a flyback-type power supply is its simple and inexpensive structure, which is also applicable in multiple-output power supplies.

The operating voltages required by the circuit are formed in an operating voltage unit 101 from a direct voltage Uac (supplied e.g. from a battery) used as the input voltage. An over/undervoltage unit 102, which is also connected between the battery voltage terminals, checks by means of a comparator whether the input voltage Uac is within an allowable range. The over/undervoltage unit 102 controls a time-constant circuit 105 through its outputs Uu and Uo, and a time- delay circuit 103 through its output Uo. A control signal is obtained at the output Uo if the input voltage is too high and at the output Uu if the input voltage is higher than the minimum input voltage. The output Uu is connected to a starting input S in the time-constant circuit, and the output Uo is connected to the first resetting input R in the time-constant circuit and to a starting input S in the time-delay circuit. A starting signal is generated from the outputs Uu and Uo to the time-constant circuit 105, when the input voltage is within its allowable range. The output Uo controls the power supply by means of the time-delay circuit 103 so that it will be switched off in overvoltage situations.

The first control output Uk of the time- constant circuit 105 is connected to the first input II in a constant-current generator circuit 108 via a parallel connection formed by a resistor Rl and a capacitor Cl. The second control output Up of the time- constant circuit 105, in turn, is connected to the second input 12 of the constant-current generator circuit 108 via a resistor R2. The time-constant circuit supplies the control voltage Uk of the inrush mode, through its first output, to the constant-current generator circuit 108, and correspondingly it supplies the control voltage Up of the normal mode (continuous mode), through its second control output, to said constant-current generator circuit (in this connection, the outputs and their signals are denoted by the same reference symbols). During the inrush mode, the control voltage Up of the normal mode is zero, so the constant- current generator circuit is controlled during the inrush mode solely by means of the control voltage Uk. Correspondingly, during the normal mode the control voltage Uk is zero, so that the constant-current generator circuit is controlled solely by means of the control voltage Up.

The output Uv of the constant-current generator circuit is connected to the first input of the voltage comparator 106, and the input of the constant-current generator circuit, the voltage of which is denoted by Ukk, is connected to the second input of the comparator. The output of the comparator is connected to the second resetting input R of the .time-constant circuit to reset the time-constant circuit as soon as information about the charging of the input capacitor Cin, connected across the input terminals of the power supply 107, is obtained from the constant-current generator circuit.

The output of the time-delay circuit 103 is connected to the resetting input R of a separate starting block 104. The actual start-up of the power supply 107, i.e. the transition from the inrush mode to the normal mode, is achieved by means of the starting block 104. For this purpose, the output Up of the time- constant circuit 105 is connected to the starting input S of the starting block 104.

Figure 2 shows in greater detail one way known per se for implementing the constant-current generator circuit 108. Both inputs II and 12 are connected to the non-inverted input of a differential amplifier 201. The output of the differential amplifier is connected to the gate of a power transistor SW. The transistor can be, for example, a power MOSFET (as shown in the figure) or any other corresponding switching element where the resistance can be adjusted by means of voltage control. The drain electrode of the FET SW is connected to one terminal of the input capacitor Cin, and its source electrode is correspondingly connected through a resistor Rm to the negative pole of the input voltage Uac. The other terminal of the input capacitor Cin is connected to the positive pole of the input voltage. A voltage proportional to the charging current Ic is obtained from the resistor Rm to the inverted input of the differential amplifier 201.

The operation of a circuit arrangement according to the invention will be described in the following in greater detail with reference to Figures 3a to 3f, which show the voltages Uac, Uu, Uk, Uv and Ukk and the charging current Ic of the input capacitor shown in Figure 1. When the input voltage Uac has exceeded its minimum value (cf. Figure 3a), the over/undervoltage unit 102 supplies a signal (voltage Uu, Figure 3b) to the starting input S of the time- constant circuit 105, thus starting the time-constant circuit (the length of the time constant is e.g. 1,000 ms), which supplies a control pulse Uk (Figure 3c) to the constant-current generator circuit 108 immediately after having started.

After the start-up, the charging current Ic increases to a certain constant value (Figure 3d), and the input capacitor Cin begins to be charged (the value of the "constant current" is determined by the resistor Rl and the capacitor Cl) . The effect of the capacitor Cl is described in Figures 3d to 3f by a broken line. At the end of the charging phase, the charging current Ic begins to decrease and then the voltage difference in the inputs of the differential amplifier 201 and also the output voltage Uv of the differential amplifier increase (Figure 3e). The differential amplifier thus aims at maintaining the constant current by controlling the resistance between the drain and source electrodes of the FET so that the resistance decreases. When the input capacitor Cin is fully charged, the control voltage Uv of the FET has become so high (higher than the set reference voltage Ukk) that the state of the output signal of the comparator 106 changes, whereupon the comparator resets the time-constant circuit 105. (This moment is denoted in Figures 3c to 3f by the reference symbol Tl and by a broken line connecting the figures). As a result of the resetting, the time- constant circuit 105 supplies a control signal Up of the normal mode to the constant-current generator circuit 108, whereupon the voltage Ukk also increases to its normal-mode value (Figure 3f). The values of the voltage Up and the resistor R2 determine the highest input current of the power supply in the normal mode. In a short-circuit situation, the control voltage Uv remains lower than the control voltage Ukk, whereupon the operation is interrupted after a period (e.g. 1,000 ms) determined by the time-constant circuit. When the control voltage Up has reached its normal-mode value, the starting block 104 receives a starting pulse, whereupon it starts the power supply. This can take place by means of for example a relay or the like provided in the starting block, which provides information about the starting to the power supply.

If overvoltage situations occur in connection with the starting operation, the time-constant circuit 105 will not start up until the input voltage Uac is within its allowable range. If overvoltages occur in the normal mode, the power supply is switched off after a period (e.g. 10 ms) determined by the time-delay circuit 103, by resetting the starting block 104. The operation again returns to normal after the overvoltage has disappeared. If the input voltage Uac decreases below its lowest allowable value, the power supply is switched off. The operation again begins with the above described charging phase after the input voltage Uac has exceeded its lowest allowable value (min, Figure 3a).

Figure 4 shows more closely a more detailed implementation of the time-constant circuit 105. The circuit comprises in its input an AND gate 401, to which the over and undervoltage information Uo and Uu, respectively, from the over/undervoltage unit 102 is connected; and a resetting circuit 402, to the inputs of which the undervoltage information Uu and the operating voltage information DV (the DV is the voltage pulse occurring at the moment of switching on the operating voltage Uac) is connected. When the input voltage Uac is within its allowable range, both input signals (Uo and Uu) of the AND gate have the logic value "true" (logical one), whereupon the output of the AND gate also has the value "true". This value is stored in a memory 403. The output of the memory starts a pulse circuit 404, which supplies a pulse (control voltage Uk) the length of which determines the duration of the inrush mode. When the comparator 106 applies a control pulse to the resetting input R of the pulse circuit 404, the control voltage drops to the logical zero level, but the output of the AND gate 405 has time enough to rise to a logical one. This value is stored in the memory 406, the output of which supplies the control signal Up of the continuous mode. A transition in the circuit from the charging phase mode to the normal mode occurs thus, after the comparator 106 has detected that the input capacitor Cin is charged. The memories are needed in the circuit, so that random disturbance peaks would not influence the operation of the circuit, but the control would remain at the desired value for a desired period of time. The output of the memory 406 can be connected in the starting block for example to one input of an AND gate (not shown here) . When the overvoltage information Uo is connected to the other input of the AND gate through the time-delay circuit 103, a signal starting the power supply is obtained from the output of the AND gate.

The memories and the pulse circuit are reset, by means of the resetting circuit 402, whenever (a) the input voltage is switched on (signal DV) or (b) the input voltage is too low (signal Uu). The constant-current generator circuit 108 can also be utilized as a current limiter after the inrush mode during the normal mode, and it is also possible to add a voltage limit circuit to the constant-current generator circuit in a simple manner. Figure 5 shows one alternative way of implementing the voltage limit function. In this case another differential amplifier 501 is added to the circuit, the output of the amplifier controlling the gate of the FET through a diode Dl in the same way as the differential amplifier 201 controls the gate of the FET through the resistor R6. In this case, the diode Dl prevents the current control provided by means of the differential amplifier 201 and the voltage control provided by the differential amplifier 501 from interfering with each other. A zener diode Zl and a resistor R3 are connected in series between the terminals of the input voltage Uac. A reference voltage Vref is supplied from their common terminal to the inverted input of the differential amplifier 501. The voltage Ul acting across the input terminals (and the input capacitor) of the power supply is sampled to the non-inverted input of the differential amplifier by means of the voltage divider resistors R4 and R5. If the voltage Ul acting across the power supply exceeds its allowable value, the differential amplifier 501 reduces the control voltage of the FET by increasing the resistance of the current path between the drain and source electrodes of the FET.

It is also possible to place the constant- current generator circuit 108 between the input capacitor Cin and the other input terminal of the power supply, but in that case the filter effect of the input capacitor is weakened.

In the above described manner, the constant- current generator circuit provides, by means of the comparator 106, information indicating when the input capacitor is fully charged and a transition to the normal mode is possible. Thus, it is essential to monitor that electrical quantity of the constant-current generator circuit, in this case the control voltage Uv, which is affected by a drop in the charging current. The constant-current generator circuit used here is known per se, but it is utilized according to the invention in a new manner.

Even though the invention is described above with reference to the examples according to the accompanying drawings, it is clear that the invention is not limited thereto, but it can be modified within the inventive idea disclosed above and in the appended claims. Although only a power supply is described above, the solution according to the invention is also applicable in principle in the switching on of other similar loads. There can also be more than one input capacitors.

Claims

Claims:

1. A method for switching on an electric load, in particular a power supply, said load being fed from a voltage source supplying an input voltage (Uac) , and an input capacitor (Cin) being connected to the input terminals of said load (107) , according to which method

- when the input voltage (Uac) is switched on, the operation is in the inrush mode, where the input capacitor (Cin) begins to be charged by means of a charging current (Ic) supplied by a constant-current generator circuit (108), after the input voltage (Uac) has exceeded its minimum value, and

- after the input capacitor (Cin) is charged, a transition to the continuous mode following the start¬ up occurs, c h a r a c t e r i z e d in that information about the charging of the input capacitor (Cin) is derived from a change caused in the constant- current generator circuit by a drop in the charging current.

2. A method according to claim 1, where the constant-current generator circuit (108) comprises a semiconductor switch (SW), the resistance of the current path passing through the input capacitor (Cin) being controlled by means of a control voltage (Uv) fed to the control electrode of said semiconductor switch, c h a r a c t e r i z e d in that information about the charging of the input capacitor (Cin) is derived by comparing said control voltage (Uv) to a reference value (Ukk), and when the control voltage exceeds the reference value, the load is switched on.

3. A method according to claim 1 or 2, c h a r a c t e r i z e d in that during the inrush mode a signal (Uk) controlling the constant-current generator circuit is supplied from a time-constant circuit (105) , which maintains said control signal during a period not exceeding a predetermined limit, and transition to the normal mode can only occur during this predetermined period of time.

4. A circuit arrangement for switching on an electric load, in particular a power supply, said load being fed from a voltage source supplying an input voltage (Uac), said circuit comprising

- at least one input capacitor (Cin), which is connected across the input terminals of the load (107), and

- a constant-current generator circuit (108), which comprises a semiconductor switch (SW), the resistance of the current path passing through the input capacitor (Cin) being controlled by means of a control signal (Uv) fed to the control electrode of said semiconductor switch, c h a r a c t e r i z e d in that it also comprises comparing means (106) for comparing the value of said control signal (Uv) to a predetermined reference value (Ukk), and starting means (104, 105) responsive to the comparing means, for switching on the load in response to the result of the comparison.

5. A circuit arrangement according to claim 4, c h a r a c t e r i z e d in that said starting means comprise a time-constant circuit (105), which maintains a control signal (Uk) supplied in the inrush mode to said constant-current generator circuit for a period not exceeding a predetermined limit, and that the output of said comparing means (106) is operationally connected to said time-constant circuit (105) to disconnect said control signal (Uk) and to supply a new control signal (Up) of the continuous mode to the constant-current generator circuit.

6. A circuit arrangement according to claim 5, c h a r a c t e r i z e d in that said starting means also comprise a separate starting block (104), which is operationally connected to the output (Up) of the time- constant circuit (105) supplying the control signal of the continuous mode, to switch on the load (107) in response to said control signal of the continuous mode.

7. A circuit arrangement according to claim 6, c h a r a c t e r i z e d in that it comprises means (102) for detecting overvoltage, the means being operationally connected to said starting block (104) to prevent the power supply from operating in an overvoltage situation.

8. A circuit arrangement according to claim 4, where said constant-current generator circuit comprises a first differential amplifier (201), the output signal of which forms the control signal (Uv) to be fed to the control electrode of the semiconductor switch (SW), c h a r a c t e r i z e d in that it also comprises a second differential amplifier (501) to the first input of which a voltage proportional to the voltage (Ul) acting across the load is connected, and to the second input of which a reference voltage (Vref) is connected, and the output of which is operationally connected to the control electrode of the semiconductor switch (SW).