WO1994028582A1

WO1994028582A1 - Integrated circuit including complementary field effect transistors and photodetector, and method of fabricating same

Info

Publication number: WO1994028582A1
Application number: PCT/US1994/005854
Authority: WO
Inventors: John E. Childers, Jr.; Michael R. Feldman; James E. Morris
Original assignee: The University Of North Carolina
Priority date: 1993-06-01
Filing date: 1994-05-25
Publication date: 1994-12-08

Abstract

An ingrated circuit includes a relatively lightly doped epitaxial layer of first conductivity type on a semiconductor substrate of the first conductivity type. A plurality of relatively heavily doped regions of the first conductivity type and a plurality of relatively heavily doped regions of a second conductivity type are included in the relatively lightly doped epitaxial layer. A pluraity of complementary field effect transistors, such as CMOS transistors, are formed in the first and second relatively heavily doped regions. At least one photodiode is formed in the relatively lightly doped epitaxial layer, outside the relatively heavily doped regions of the first and second conductivity type. Accordingly, complementary field effect transistors are formed in N-wells and P-wells and photodiodes are formed in intrinsic wells. The photodiodes form P-I-N photodetectors of relatively high quantum efficiency, short rise time, short fall time and short transit time.

Description

INTEGRATED CIRCUIT INCLUDING COMPLEMENTARY

FIELD EFFECT TRANSISTORS AND PHOTODETECTOR,

AND METHOD OF FABRICATING SAME

Field of the Invention

This invention relates to microelectronic devices and more particularly to integrated circuits including complementary field effect transistors, such as complementary metal oxide semiconductor (CMOS) field effect transistors.

Background of the Invention

Integrated circuits which include complementary field effect transistors, such as CMOS transistors, have become dominant in logic and memory devices, microprocessors and other applications. Presently, there is much investigation concerning integration of optoelectronic devices into these integrated circuits. Optoelectronic devices include photodetectors for detecting optical signals impinging thereon and photoemitters for emitting optical signals. Optoelectronic devices may be used to transmit and receive digital signals at high speeds. See, for example, Application Serial No. 07/787,938, entitled Microelectronic Module Having optical and Electrical Interconnects, to coinventor Feldman et al. , now U.S. Patent 5,237,434, the disclosure of which is hereby incorporated herein by reference. As shown, optical signal beams are used with holograms to form signal interconnections between very large integration (VLSI) chips.

In order for a photodetector to operate efficiently, it is preferable for the photodetector to have a high quantum efficiency, such as a quantum efficiency of more than 40%, to maximize the optical radiation which is detected. Moreover, low power consumption, on the order of a few milliwatts or less, is preferred for high circuit packing densities.

Finally, the photodetector should have rise and fall times which are at least as fast as the CMOS logic gates on the integrated circuit. The integral photodetector should also preferably be compatible with a CMOS fabrication process, and should not degrade the performance of the CMOS circuits themselves.

The simplest photodetector is a P-N diode. Schottky diode photodetectors can also be provided. As is well known to those having skill in the art, a depletion layer forms between the anode and cathode of a diode. In the depletion layer, there is a strong electric field due to a reverse bias voltage and the distribution of space charge at the P-N junction. As a result, photocarriers generated in this region move as a drift current. In the anode and cathode regions, the electric field is typically weak, causing the photocarriers to move as a slower diffusion current. In a typical CMOS integrated circuit, the source/drain contacts are typically too thin to contribute significantly to a photodiode's quantum efficiency. Also in a typical CMOS integrated circuit, the substrate is moderately doped, resulting in small depletion widths. Accordingly, previously reported photodiodes manufactured using a standard CMOS process have had low quantum efficiency, and much slower rise and fall times than the CMOS logic circuits themselves. It is known to provide high performance photodiodes in the form of a P-I-N photodiode. The P- I-N photodiode uses an intrinsic (I) region between the P and N regions. As is well known to those having skill in the art, the intrinsic region need not be, and is typically not, truly intrinsic (undoped) , but can be relatively lightly doped compared to the P- and N- region. The P-I-N diode provides high performance by providing a relatively wide depletion region. However, P-I-N diodes have not been regarded as compatible with CMOS technology, where the epitaxial layer in which the CMOS devices are formed is relatively heavily doped.

Summary of the Invention

It is therefore an object of the invention to provide an improved integrated circuit including complementary field effect transistors and a photodiode.

It is yet another object of the present invention to provide an integrated circuit including logic gates and a photodiode, in which the photodiode is capable of relatively high quantum efficiency, relatively low power consumption and rise and fall times which are comparable to the logic gates in the integrated circuit. It is yet another object of the present invention to provide a method of manufacturing an integrated circuit which includes complementary field effect transistors and a photodetector, and which is compatible with CMOS fabrication processes. These and other objects are provided, according to the present invention, by an integrated circuit which includes a relatively lightly doped (for example, less than about 10¹⁵ carriers cm^"3) epitaxial layer of first conductivity type on a semiconductor substrate of first conductivity type. A plurality of relatively heavily doped, (for example, more than about 10¹⁵ carriers cm^"3) regions of the first conductivity type and a plurality of relatively heavily doped regions of a second conductivity type are included in the relatively lightly doped layer. A plurality of complementary field effect transistors are formed in the first and second relatively heavily doped regions. At least one photodiode is formed in the relatively lightly doped epitaxial layer of first conductivity type, outside the relatively heavily doped regions of the first and second conductivity types.

Accordingly, the complementary field effect transistors are formed in relatively heavily doped complementary regions in a relatively lightly doped epitaxial layer. The photodiodes are formed in the relatively lightly doped epitaxial layer, outside the relatively heavily doped complementary regions. The relatively lightly doped layer may be considered an intrinsic region so that P-I-N photodetectors are formed. The relatively lightly doped layer is preferably doped at a doping concentration of less than about 10¹⁵ carriers cm^"3, for example 2.8xl0¹⁴ carriers cm^"3. Since the intrinsic epitaxial layer is relatively lightly doped, a large depletion region is formed in the P-I-N photodetector. As a result of the depletion region's contribution to the photodetectors quantum efficiency, a large increase in quantum efficiency of the fast-responding depletion region is provided compared to photodetectors which are formed in a relatively heavily doped epitaxial layer. Additionally, the transit time is greatly decreased and the rise time is dramatically decreased.

The present invention may be regarded as an integrated circuit having three wells. As used herein, a "well" is a region of predetermined conductivity type, in which semiconductor devices such as transistors or diodes are formed. At least one intrinsic well is provided in a semiconductor substrate, by the relatively lightly doped (intrinsic) epitaxial layer. A plurality of first and second wells of first and second conductivity type are provided by the relatively heavily doped regions of first and second conductivity type in the semiconductor substrate. CMOS or other complementary field effect transistors are formed in the first and second wells and at least one photodiode is formed in the intrinsic well. Accordingly, the semiconductor substrate includes three types of wells which are optimized for CMOS devices and photodiodes. This contrasts sharply from standard N-well CMOS technology, which includes only two types of wells for the complementary CMOS transistors. The P-well is typically formed by a P- type epitaxial layer, and N-wells are formed in the epitaxial layer.

The photodiode itself includes an intrinsic or relatively lighted doped layer of first conductivity type on a relatively heavily doped semiconductor substrate of the first conductivity type. A relatively heavily doped cathode of second conductivity type is formed in the relatively lightly doped layer, opposite the semiconductor substrate. A relatively heavily doped anode contact of the first conductivity type is formed in the relatively lightly doped layer, opposite the semiconductor substrate, and at least partially surrounding the relatively heavily doped cathode. Accordingly, light is primarily detected in the relatively lightly doped (intrinsic) layer of first conductivity type. The relatively lightly doped (intrinsic) layer forms a large depletion region between the anode and cathode. It will be understood by those having skill in the art that the substrate can also form an additional anode contact.

The three well integrated circuit of the present invention may be fabricated using techniques which are compatible with CMOS processing. In particular, a relatively lightly doped (intrinsic) layer of first conductivity type is epitaxially formed on a relatively heavily doped semiconductor substrate of the first conductivity type. A plurality of relatively heavily doped regions of the first conductivity type and a plurality of regions of the second conductivity type are formed in the relatively lightly doped layer opposite the semiconductor substrate, for example using two masking and ion implantation steps. Complementary field effect transistors are then formed in the first and second regions, for example by using standard CMOS processing. At least one photodiode is formed in the relatively lightly doped epitaxial layer, outside the relatively heavily doped regions. Accordingly, high efficiency photodetectors may be provided in a CMOS-integrated circuit.

Brief Description of the Drawings Figure 1 illustrates a side cross-sectional view of an integrated circuit according to the present invention.

Figure 2 illustrates an enlarged cross- sectional view of a photodiode of Figure 1. Figures 3A-3C illustrate the integrated circuit of Figure 1 during intermediate fabrication steps.

Figure 4 is a circuit schematic diagram of an integrated circuit according to the present invention.

Detailed Description of Preferred Embodiments

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

Referring now to Figure 1, a side cross- sectional view of an integrated circuit according to the present invention is shown. As shown in Figure 1, integrated circuit 10 includes a relatively heavily doped semiconductor substrate 11, for example, doped P+ with a doping concentration of 10¹⁹ carriers cm^"3. A relatively lighted doped epitaxial layer 12 is formed on substrate 11. Epitaxial layer 12 is preferably doped at a doping density of less than approximately 10¹⁵ carriers cm"³ so that it may be considered an "intrinsic" layer relative to the other heavily doped layers in the device. However, it will be understood by those having skill in the art that epitaxial layers are typically not truly intrinsic, i.e. undoped. Rather, they include a doping level of first or second conductivity type which is substantially lower than that of the other device regions. Accordingly, epitaxial layer 12 is referred to herein as a

"relatively lightly doped epitaxial layer" or an "intrinsic layer", and is denoted P-- in Figure 1.

Still referring to Figure 1, a plurality of relatively highly doped regions 13 of first conductivity type are formed in epitaxial layer 12 opposite substrate 11. As shown in Figure 1, these regions 13 form "P-wells". A plurality of relatively highly doped regions 14 of second conductivity type are also formed in epitaxial layer 12, opposite substrate 11. Regions 14 will also be referred to herein as "N- wells" . The N-wells 14 and P-wells 13 are preferably doped at a carrier concentration greater than 10¹⁵ carriers cm^"3, and more preferably at a concentration which optimizes the performance of the CMOS transistors, such as a concentration greater than 10¹⁶- 10¹⁷ carriers cm^"3 for a typical CMOS process. As illustrated in Figure 1, plurality of complementary field effect transistors 16 and 17 are formed in N-wells 14 and P-wells 13, respectively. PMOS transistors 16 are formed in N-wells 14 and NMOS transistors 17 are formed in P-wells 13. Thus, CMOS transistors are formed. As will be understood by those having skill in the art, each transistor 16, 17 includes a source 22, a drain 23, a gate insulating layer 24 such as silicon dioxide and a gate electrode 25 typically formed of polycrystalline silicon (polysilicon) . Sources 22 and drains 23 are typically degeneratively doped at more than 10¹⁸-10¹⁹ carriers cm^"3. Source, drain and gate contacts and other interconnecting metallizations are also typically provided, but are not illustrated in Figure 1. As also shown in Figure 1, at least one photodiode 15 is also formed in epitaxial layer 12. The photodiode includes a relatively highly doped cathode region 18 of the second conductivity type, and a relatively highly doped anode contact 21 of the first conductivity type. The anode contact 21 at least partially surrounds cathode 18. Cathode 19 and anode contact 21 are typically degeneratively doped at more than 10^1B-10¹⁹ carriers cm^"3. The anode 19 of photodiode 15 is provided by the relatively lightly doped epitaxial layer 12 adjacent the cathode 18 and the anode contact 21. A cathode electrode 26 and an anode electrode 27 are also provided.

The integrated circuit of Figure 1 may be regarded as a relatively lightly doped or intrinsic epitaxial layer having P-wells and N-wells therein. Alternatively, the structure of Figure 1 may be regarded as having a plurality of P-wells 13, N-wells 14 and intrinsic wells 12a therein, where the intrinsic wells are formed by a portion of the epitaxial layer 12. The photodiodes 15 are formed in the intrinsic wells 12a. Figure 2 illustrates an enlarged cross- sectional view of a photodiode 15 of Figure 1. As shown, the relatively lightly doped intrinsic well 12a forms an enlarged depletion region 20 in anode region 19, between cathode 18 and anode contact 21. The low anode doping approximates a P-I-N diode and provides improved performance characteristics as will be described below.

The photodetector 15 of Figure 2 contrasts with known photodetectors, such as described in U.S. Patent 4,275,362 to Harford. For example, the cathode 18 is opposite conductivity type from that of substrate 11, while in Harford, the same conductivity type is used. The opposite conductivity type cathode 18 produces a vertical photodetector, in which most of the light contributing to the photocurrent is absorbed beneath cathode 18, and most of the photocurrent flows between cathode 18 and substrate 11 in a vertical direction (i.e. orthogonal to the faces of substrate 11. The present invention also contrasts with the integrated circuit described in Harford because all of Harford' s transistors and photodetectors are formed in the same conductivity region.

Referring^{^} now to Figures 3A-3C, a process for forming the integrated circuit 10 of Figure 1 will now be described. As shown in Figure 3A, a relatively lightly doped layer 12 is epitaxially formed on a relatively heavily doped substrate 11. As shown in Figure 3B, the integrated circuit is masked with first mask 31, using well known masking and patterning techniques. As is well known to those having skill in the art, mask 31 may be silicon dioxide, silicon nitride,^' polyimide or other well known materials. First ions 32, such as Boron ions, are implanted into epitaxial layer 12 to form P-wells 13. Mask 31 is then removed.

Referring now to Figure 3C, a second mask 33 is formed on epitaxial layer 12 and patterned using standard techniques. Second ions 34, such as Arsenic ions, are then directed to the mask to form N-wells 14, and the second mask 33 is removed. Source,^' drain and gate regions are formed in the N-wells and P-wells using standard CMOS or other processes. At least one photodiode 15 is formed in the epitaxial layer outside the N- and P-wells to form the structure of Figure 1. It will be understood by those having skill in the art that the sources, drains, anodes and cathodes may be formed by masked ion implantation or other well known steps.

An explanation of the superiority of the photodetector 15 of Figure 1 compared to standard P-N photodetectors will now be provided. The simplest CMOS photodetector is a P-N diode. When a photodetector is formed in a standard N-well CMOS process, the cathode is formed by an N-contact and the anode is formed from the substrate and a P-substrate contact. A depletion layer forms between the anode and cathode with a width given by :

where e_s is the dielectric constant of silicon, V is the reverse bias voltage applied to the photodetector, V_bi is the photodetector' s built-in potential, q is the electronic charge, and N_a is the substrate doping. See S. M. Sze, Semiconductor Devices, Physics and

Technology, 1986, pp. 78-79 and 283. The contribution to the photodetector' s quantum efficiency from each of -li¬ the principle regions (anode, cathode and, depletion layer) is given by:

where a is the absorption coefficient (about 10⁵/m for silicon) , the index i refers to the particular region (i=l for the cathode, i=2 for the depletion layer and, i=3 for the anode) , d__ is the depth at which light enters region i and d_2/1 is the depth at which light exits region i. See K. A. Jones, Introduction to Optical Electronics, 1987, pp. 190-194. Light enters from above the photodetector and travels vertically through the cathode, depletion layer and anode. For the cathode d_{x l} and d_2ιl are at the top of the detector and at the interface of the cathode with the depletion layer respectively. The cathode's d_2ιl is also the depletion layer's d_1#2. For the depletion layer, d_2/2 is at the interface of the depletion layer with the anode, which is also d₁₃ for the anode. The anode's d_2/3 is the depth beyond which photocarriers are no longer collected. In the depletion layer there is a strong electric field due to a reverse bias voltage and the distribution of space charge at the P-N junction. As a result, photocarriers generated in this region move as a drift current with a velocity near V_sat (about 10⁷ cm/sec for silicon) . In the anode and cathode regions the electric field is weak, causing the photocarriers to move as a slower diffusion current. A typical average velocity for the diffusion carriers is about 10⁴ cm/sec. Thus, the drift carriers in the depletion layer will respond much faster than the diffusion carriers in the anode and cathode. The transit time for carriers to cross the depletion layer is given by:

where W is the width of the depletion layer. The transit time for the diffusion carriers in the anode and cathode is given by:

r²

where D_n is the electron diffusivity (35 cm²/sec for silicon) and L is the distance the carriers diffuse. See W. H. Wu et al. , CMOS Detector Cells for Holographic Optical Interconnects in Microcircui ts, Proceedings of the SPIE, Vol. 752, 1987, pp. 192-199. For optimum speed, the photodetector design should maximize the generation of carriers in the depletion layer and minimize the generation of carriers in the anode and cathode. In a typical CMOS process the N-source/drain contacts are typically too thin (about 0.2μm) to contribute significantly to the photodetector's quantum efficiency. Also in a typical CMOS process the substrate is moderately doped (10¹⁵ to 10¹⁶cm^"3) resulting in small depletion widths, from Equation (1), of approximately l.Oμm at a reverse bias of 5 volts. Moderate doping is required because if the carrier concentration is too high, it is difficult to invert the channel of a transistor, and capacitance values are high due to shallow depletion regions. If the doping is too low, there can be relatively large voltage drops between different regions of the substrate, and there can be latchup problems. Epitaxial layers are used to provide a very high concentration substrate to avoid latchup problems, while allowing the use of moderately doped regions in which the transistor channels can be formed.

Although the transit time for such a depletion layer, from Equation (3) , is in the tens of picoseconds, previously reported photodetectors manufactured in a standard CMOS process have had much slower rise and fall times, in the tens of nanoseconds range. This is explained by Equation (2) . In silicon, a 1.0 μm depletion layer will absorb less than 10 percent of the incoming optical signal while the much thicker, and slower responding, anode region can absorb 50 to 90 percent of the incoming signal. By absorbing more of the optical signal, the anode region will produce a much larger photocurrent than the depletion layer. Since the majority of the photodetector' s current is being produced in the slower responding anode region, the overall photodetector response will be slow. Improved performance can be achieved by fabricating photodetectors 15 in intrinsic wells 12a according to the present invention. An intrinsic well is a lightly doped substrate region used to form the anode of a photodetector. With the use of the lightly doped anode 19, the depletion width and the depletion layer 20 quantum efficiency are increased allowing the photodetector to approximate a P-I-N diode.

An intrinsic well photodetector 15 was designed with an epitaxial layer 12 doping of 2.8 x 10¹ cm^"3 and a substrate doping of 10¹⁹. N-well and P- well doping was about 10¹⁶. Source and drain doping and anode and cathode doping was 10¹⁸. The depth of anode contact 21 and cathode 18 was about 0.2μm. The depth of depletion region 20 was about 5μm and the thickness of epitaxial layer 12 was about 8μm. Substrate 11 was about 300μm thick. Cathode 18 was about 21μm wide and anode contact 21 was about 2.8μm wide. A spacing of about 8.4μm was maintained between adjacent edges of cathode 18 and anode contact 21. This increased the depletion layer 20 width, from Equation (1), to 5.1μm at a reverse bias of 5 volts. In the above design, the depletion layer's contribution to the photodetector's quantum efficiency, from Equation (2) , was increased to about 40%, while the anode region's contribution to the quantum efficiency dropped to about 15%. Additionally the transit time for the depletion layer, from Equation

(3) , increased by only a few picoseconds while the anode transit time, from Equation (4) , decreased to under 3 nanoseconds. As already discussed, such an intrinsic well detector can be fabricated in a CMOS compatible process that is modified to include intrinsic wells.

The photodetector was integrated with the simple output circuit shown in Figure 4. The output circuit consists of PMOS transistor 16 and a CMOS inverter 35. The gate of the PMOS transistor is connected to ground so that it will operate in it's linear region and therefore act as a resistor to reverse bias the photodetector. The CMOS inverter 35 including an NMOS transistor 17 and a PMOS transistor 16, provides an output stage. See Huang et al. Low Impedance Compl emen tary Me tal- Oxi de- Semi conductor Optical Receivers for Optical Interconnects, Applied Optics, Vol. 31, p. 4623, 1992. The active area of the detector was 21μm x 21μm. For experimental measurements, the photodetector was connected by microprobes to a power supply and a sampling oscilloscope. A 5mW 790nm laser was imaged onto the photodetector through the microscope via a camera port on the microscope. The spot size of the incident beam was- less than 15μm and the maximum optical power measured at the photodiode was 274μW. The DC response of the discrete detectors was directly measured at 0.32 A/W. To measure the discrete detector response time, a detector was connected to a 5V supply through a 10KΩ resistor and to a sampling oscilloscope through an active FET probe with several picofarads of capacitance. The RC time constant for this setup was measured as 113ns. To obtain the detector response time with this setup, the delay between laser turn on and the detector turn on was measured and the effects of the RC delay were subtracted. The turn on delay for the detector was found to be 2.5ns, and 7.6ns for the turn off delay.

To measure the combined detector and circuit response times, the complete photodetector was connected to a variable DC power supply and to a sampling oscilloscope through an FET probe, and the turn on and turn off delay times were measured. The photodetector' s response times were found to be power dependent, with the turn on time decreasing as the optical power increased. While not wishing to be bound by any theory of operation, it is believed that the reason for the decrease in turn on time was that the high optical power produced large photocurrents that discharged the detector and inverter gate capacitances faster. It is also believed that the reason for the increase in the turn off time was that the higher optical power produced a photocurrent in the slower responding diffusion region that was greater than the circuit's switching threshold. The shortest turn on time measured was 4.5ns and the shortest turn off time measured was 2.0ns, measured at approximately 250μW and 50μW respectively. At an intermediate power, a symmetric response of approximately 10ns for turn on and turn off time was obtained. The maximum modulation rate at which the photodiode could detect a signal was also measured. Due to the MOS transistor load the photodiode's response was supply voltage dependent . When the supply voltage was increased the transistor's resistance decreased, thus lowering the photodetector' s RC time constant. The fastest rate measured was 112 MHz (224 Megabits/sec) with a supply voltage of 10V. The data rate was 180 Megabits/sec at 6.5V. These results were compared to the turn on time measurement and computer simulations. From this, the detector capacitance was calculated to be 15fF. The Table below compares the photodiode of the present invention with results of previous work in the above cited Wu et al. and Huang et al. publications. As shown, the detector and detector circuit response times have been significantly improved. The modulation rate has also been dramatically improved.

Table

Previous Present Invention

Detector Rise Time 34ns 2.6ns

Detector Fall Time 36ns 7.9ns

Circuit Rise Time 27ns 4.5ns

Circuit Fall Time 108ns 2.0ns

Modulation Rate 5 Mbit/sec 224 Mbit/sec

Accordingly, photodetectors that approximate a P-I-N diode can be fabricated in CMOS integrated circuits using intrinsic wells. CMOS logic gates and detector output circuits based on CMOS logic gates can also be produced on the same CMOS integrated circuit chip. Such photodetectors can have modulation rates and response times that are improved by an order to magnitude or more when compared with previous integrated circuit CMOS photodetector designs.

It will be understood by those having skill in the art that there are several ways to further improve performance of the photodetectors. The depletion layer 20 width can be further increased by decreasing the doping of epitaxial layer 12 or by applying a larger reverse bias voltage using improved detector output circuits. Also, anode diffusion currents can be reduced by adding recombination centers or diffraction gratings to the detector, as described in Clymer, Surface-relief Grating Structures for

Efficient High Bandwidth Integrated Photodetectors for Optical Interconnections in Silicon, Applied Optics, Vol. 28, pp. 5374-5382, 1989. Finally, a limiting factor for the output stage is the CMOS technology used. With the continuous improvements in CMOS technology, the photodetector circuit response should continue to improve.

In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

CLAIMS:

1. A CMOS integrated circuit comprising: a semiconductor substrate; a plurality of first wells of first conductivity type in said semiconductor substrate; a plurality of second wells of second conductivity type in said semiconductor substrate; a CMOS logic gate in said first and second wells; at least one intrinsic well in said semiconductor substrate; and at least one photodiode in said at least one intrinsic well, said at least one photodiode being electrically connected to said CMOS logic gate in said first and second wells, such that said at least one photodiode is responsive to a digital optical signal and said CMOS logic gate produces a digital bit stream in response thereto, at a modulation rate in excess of 50 Mbit/sec.

2. The CMOS integrated circuit of Claim 1 wherein said photodiode comprises a cathode and an anode contact of opposite conductivity type, formed at a face of said semiconductor substrate.

3. The CMOS integrated circuit of Claim 1 wherein said intrinsic well is lightly doped, relative to said plurality of first wells and said plurality of second wells.

4. The CMOS integrated circuit of Claim 3 wherein said intrinsic well has doping concentration of less than about 10¹⁵ carriers cm^"3 and wherein said first wells and said second wells have doping concentrations of more than about 10¹⁵ carriers cm^"3.

5. The CMOS integrated circuit of Claim 2 wherein said intrinsic well has a relatively low doping concentration of said first conductivity type, wherein said anode contact has a relatively high doping concentration of said first conductivity type, and wherein said cathode has a relatively high doping concentration of second conductivity type.

6. A method of fabricating an integrated circuit comprising the steps of: epitaxially forming a relatively lightly doped layer of a first conductivity type on a relatively heavily doped semiconductor substrate; forming a plurality of relatively heavily doped first regions of said first conductivity type and a plurality of relatively heavily doped second regions of a second conductivity type in said relatively doped layer, opposite said semiconductor substrate; forming complementary field effect transistors in said first and second regions, respectively; and forming at least one photodiode in said relatively lightly doped epitaxial layer, outside said relatively heavily doped first and second regions.

7. The method of Claim 6 wherein said first and second region forming step comprises the steps of: masking said relatively lightly doped epitaxial layer to expose first areas thereof; implanting ions of first conductivity type into the exposed first areas to form said first regions; masking said relatively lightly doped epitaxial layer to expose second areas thereof; and implanting ions of second conductivity type into the exposed second areas to form said second regions.

8. The method of Claim 6 wherein said plurality of complementary field effect transistors are a plurality of CMOS field effect transistors.

9. The method of Claim 6 wherein said photodiode forming step comprises the step of forming a cathode and an anode contact of opposite conductivity type, in said lightly doped epitaxial layer of said semiconductor substrate.

10. The method of Claim 6 wherein said relatively lightly doped layer has doping concentration of less than about 10¹⁵ carriers cm^"3 and wherein said first regions and said second regions have doping concentrations of more than about 10¹⁵ carriers cm^"3.

11. The method of Claim 9, wherein said anode contact has a relatively high doping concentration of said first conductivity type, and wherein said cathode has a relatively high doping concentration of second conductivity type.

12. An integrated circuit comprising: a semiconductor substrate; a first well in said semiconductor substrate; a second well of first conductivity type in said semiconductor substrate; a third well of second conductivity type in said semiconductor substrate; a fourth well of said second conductivity type in said semiconductor substrate, said fourth well being more lightly doped than said third well; a first field effect transistor in said first well; a second field effect transistor of said second conductivity type in said second well, and including a second gate; a third field effect transistor of said first conductivity type in said third well, and including a third gate; a photodiode in said fourth well, said photodiode including a first region of first conductivity type, and a second region of second conductivity type, said second region at least partially surrounding said first region in said fourth well; said first field effect transistor and said photodiode being serially connected between a first and a second reference voltage to define a first node therebetween such that said first field effect transistor reverse biases said photodiode; said second and third field effect transistors being serially connected between said first and second reference voltages to define a second node therebetween; said second and third gates being connected to said first node; and said second node defining a digital output for producing a digital bitstream in response to a digital optical signal which is received by said photodiode.

13. The integrated circuit of Claim 12 wherein said first region is connected to said first field effect transistor to define said first node.

14. The integrated circuit of claim 12 wherein said first, second and third field effect transistors and said photodiode are formed at a face of said semiconductor substrate.

15. The integrated circuit of Claim 12 wherein said fourth well has doping concentration of less than about 10¹⁵ carriers cm^"3 and wherein said first, second and third wells have doping concentrations of more than about 10¹⁵ carriers cm^"3.