WO1994023370A1

WO1994023370A1 - Two speed bus clock allowing operation of high speed peripherals

Info

Publication number: WO1994023370A1
Application number: PCT/US1994/003424
Authority: WO
Inventors: Robert H. J. Lee; John D. Kenny
Original assignee: Picopower Technology Incorporated
Priority date: 1993-04-02
Filing date: 1994-04-01
Publication date: 1994-10-13
Also published as: AU6622294A

Abstract

A high speed bus system of the present invention features generating first (SYSCLK) and second (TURBOCLK) clock signals, the first clock signal being at a first frequency and the second clock signal being at a second frequency greater than the first frequency. A first industry standard (ISA CLOCK DIVIDER) input bus to which peripherals to operate at the first clock signal frequency and asecond high speed (TURBO CLOCK DIVIDER) bus to which peripherals to operate at the second clock signal frequency are also provided, the peripherals connected to the second high speed input bus operating at a higher speed than the peripherals connected to the first industry standard input bus. Further, a program decoder identifies which peripherals are connected to the second high speed input bus. By utilizing such a system, the present invention allows high speed peripherals to run at their high speeds while other standard speed peripherals run at their standard speed. The present invention achieves this operation in the same system without requiring the high speed peripherals to have any special redesigning.

Description

Two Speed Bus Clock Allowing Operation of High Speed Peripherals

Technical Field

The present invention is directed to a system, for use in a computer system, which increases ISA bus peripheral performance by allowing the bus speed to change dynamically to match more nearly the optimal speed of the peripheral device. Unlike other solutions, this implementation can accommodate one at a time different speeds of various peripherals and is not limited to a single speed.

Background Art

For several years now, AT-compatible system and chipset vendors have offered options to run ISA buses at speeds above 8 MHz. The difficulty with using these high speed options is that the ISA bus can run no faster than the slowest peripheral unit attached to it. Thus, in these types of conventional systems, if a slow peripheral unit is attached to an ISA bus, no increase in processing speed and performance can be achieved. Thus, the de facto 8 MHz ISA bus clock standard has imposed severe performance limitations to peripherals attached to an ISA bus.

These bottlenecks are the major driving force behind the creation of EISA bus, the MicroChannel ™ (MC) bus and more recently, new "local bus" proposals like VL-Bus (VESA Local Bus) or PCI. One such method to overcome drawbacks in conventional systems is to use a "local bus" design system. A "local bus" design system allows a peripheral unit to interface directly to the CPU, and thus avoid using the ISA bus. In such a system, a high speed peripheral unit can be directly connected to a CPU, so that the high speed peripheral unit can operate at a high speed. However, such "local bus" systems suffer from significant drawbacks in that these types of "local bus" designs require major re-design of the planar motherboard and/or peripherals to take advantage of a direct interface.

However, almost all new peripheral devices designed to be compliant to new bus standards including EISA, MC, VLB or PCI have retained backward compatibility to some extent with the ISA interface. These peripheral devices can actually run at very high clock rates (with some wait states, if necessary) even if they are running in ISA mode. So that, by increasing the ISA bus clock only when accessing these high speed devices, an increase in the I/O performance can be achieved which is roughly proportional to the speed increase of the bus. Many core logic chipset vendors have offered options (using lower clock division ratio) to run the ISA bus at speeds above 8 MHz. However, as noted above, the difficulty with using these high speed options is that the ISA bus can run no faster than the slowest peripheral attached to it.

Disclosure of the Invention

Accordingly, one object of the present invention is to provide a novel high speed bus system hereafter called a turbobus which allows the bus speed to change dynamically to match more nearly the optimal speed of the peripheral devices.

In this way, this implementation of the present invention can accommodate, one at a time, different speeds of various peripherals and is not limited to a single speed.

The present invention also provides for a high speed bus which also supports a VESA-compatible local bus, and which allows for higher speed operation with existing ISA-compatible peripherals that are capable of running faster than at the conventional 8 MHz.

The present invention achieves these objectives by a combined software/hardware approach with a system featuring a means for generating first and second clock signals, the first clock signal being at a first frequency and the second clock signal being at a second frequency, the second frequency being greater than the first frequency. A first industry standard input bus means to which peripherals to operate at the first clock signal frequency and a second high speed input bus means to which peripheral to operate at the second clock signal frequency are also provided. Further, an identification means identifies which peripherals are connected to the second high speed input bus means.

The present invention utilizes two (or more, if necessary) programmable address range decoders, one for an I/O block and one for a memory block. The present invention also provides hard-wired decoders for complex address devices like VGA controllers. When the programmed address range (including the hard-wired address range, if enabled) is being accessed, the circuit will switch the ISA bus clock from the conventional 8 MHz to a pre-programmed higher speed clock.

Historically, to run a device on ISA over 8MHz is very difficult due to the ISA bus specifications on how the MEMCS16# is generated. The present invention has register bits to define the bus width of the high speed ISA device in the programmed address range, so that the MEMCS16# and IOCS16# will be automatically generated on-chip, when appropriate. To further enhance I/O performance, the device will assert OWS# to identify a zero wait state cycle whenever it can. However, OWS# is another timing critical signal on the ISA bus even at 8 MHz. To tackle this, the circuit of the present invention will delay sampling the OWS# by 1/2 of a TURBOCLK of this invention, during TurboBus operation to relax the timing for OWS# generation.

To get the same performance increase in 8-bit peripherals, the present invention has an optional bit, TURBOBUSII, to enable 8-bit peripherals running in 16-bit timing which cuts the cycle time by 50% (from 4 WS or 6 CLK to 1 WS or 3 CLK) which effectively doubles the performance, at same clock rate.

The present invention also has a programmable option to extend the command strobes (MEMR#, MEMW#, IOR# or IOW#) by one TURBOCLK after the IOCHRDY is sampled high. This will ensure compatibility with some VGS controllers which asserts IOCHRDY high long before the data is valid on the SD-bus.

During TurboBus cycles, the present invention may assert a special signal, TURBOBUS, high to indicate it is in a TurboBus operation. This signal can be used to gate off the TurboBus command strobes to the standard ISA devices, to ensure backward compatibility.

By utilizing such a system, the present invention allows high speed peripherals to run at their high speeds while other standard speed peripherals run at their standard speed. The present invention achieves this operation in the same system without requiring the system or high speed peripherals to have any special redesigning.

Brief Description of the Drawings

A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

Figure 1 shows a clock divider circuit according to the present invention; Figure 2 shows a control circuit according to the present invention;

Figures 3A and 3B show programmable decoding blocks utilized in the present invention;

Figures 4A and 4B show zero waiting sampling timings according to the present invention;

Figures 5A and 5B show further control timings for 8-bit I/O according to the present invention; and

Figures 6A and 6B show further control timings according to the present invention.

Best Mode for Carrying Out the Invention

There are several unique features in the high speed bus system of the present invention which enhances its operation, each one of which is discussed below.

The total effect of these features of the present invention is that a few high-speed ISA-compatible peripherals can run at much higher speeds in the system of the present invention, while total ISA bus compatibility is retained for those peripherals connected to the bus that would not support higher speed operations.

The circuit shown in Figure 1 generates the appropriate clock signals for the high speed bus system, hereafter referred to as the Turbo Bus system, of the present invention. As shown in Figure 1, according to the present invention an ISA bus clock (SYSCLK) is generated by dividing down a conventional CPU's CLK2 signal (the CPO is not shown or clarity) through clock divider 6. For example, if a 33 MHz 486DX CPU, has a 66 MHz CLK2 and then if first clock divider 6 is a clock divisor of 8, as selected by signal SDIV[0..2], this results in an ISA SYSCLK signal of 8.25 MHz. The CLK2 signal is also fed to the CLKIN input of a second clock divider 7, which is labelled as the Turbo Clock Divider as it outputs the TURBOCLK signal. This TURBOCLCK signal in this example is at a higher frequency that the SYSCLK signal. The present invention thus contains two separate clock dividers 6 and 7, one which runs all the time to support the ISA bus SYSCLK (clock divider 6) , and another one which supports Turbo Bus access (clock divider 7) . The clock divider 7 which generates the TURBOCLK should be programmed with a smaller divisor, resulting in higher clock speed for Turbo Bus access.

As shown in Figure 1, each of the clock dividers 6 and 7 has its own divisor inputs, allowing for different output speeds. The outputs of the ISA and Turbo Bus dividers 6 and 7 are respectively the SYSCLK and TURBOCLK pins respectively. These two outputs are multiplexed in multiplexer 8 to create a dual-speed ATMCHCLK signal which is used as the clock reference for the AT bus state machine.

The SLOWRUN signal is an internal signal to the circuit which is initially low after reset, but which goes high and stays high starting with the first ISA bus access by a CPU (not shown) , which is a ROM BIOS access in a typical PC/AT compatible system. This SLOWRUN signal is input into the RUN pin of clock divider 6, and is one input to AND gate 3. This keeps the ISA Bus clock divider 6 running at all times except during system reset.

A TBUSSEL signal is derived from a programmable decode block, discussed below, and goes active to indicate the present cycle is on the Turbo Bus. This TBUSSEL signal is input into AND gate 2 through inverter 1, and is also one input to AND gates 3 and 5. The output of AND gates 2 and 3 are input into the SYNC control of respective Turbo Clock Dividers 6 and 7. The TBUSSEL signal is also input to multiplexer 8.

The signal ATSTART is a pulse which goes active at the beginning of a cycle on either the ISA or Turbo bus. This ATSTART signal is the other input to AND gates 2 and 3, and is one input to OR gate 4. The ATCYCL signal will then go active and remain active until the bus cycle has been completed.

The AND gate 2, logically ANDs the ATSTART and the inverted TBUSSEL by inverter 1. This enables proper synchronization of ISA clock divider 6 with CLK2, during a standard ISA bus cycle. Similarly, the AND gate 3, logically ANDs the ATSTART and the TBUSSEL enables proper synchronization of turbo clock divider 7 with CLK2 during a Turbo Bus cycle.

The turbo clock divider 7 will start to run only if the output of the AND gate 5 goes high. The OR gate 4, logically ORs the ATSTART and ATCYCL. As discussed above, ATSTART will pulse high at the beginning of every AT bus (ISA or Turbo Bus) cycle followed by ATCYCL going active and it will remain active until the end of the bus cycle, which means the output of OR gate 4 will go high and remain high throughout the AT bus cycle. The AND gate 5 ANDs the output of OR gate 4 and TBUSSEL, its output will go high during an AT bus cycle if TBUSSEL is high when a device on Turbo Bus whose address range, which has been pre-programmed into the programmable decode block, is being accessed. The output of the turbo clock divider 7 TURBOCLK will then be transmitted through a Multiplexer 8 to ATMCHCLK which is the clock reference for the AT bus state machines.

Figure 2 illustrates the circuitry of the present invention to gate off the ISA bus command strobes to standard ISA during Turbo Bus cycle to ensure 8 MHz ISA backward co patibility. The control circuit 9, which implements the circuitry shown in Figure 1 and the programmable decode block discussed with respect to Figure 3 below, will drive the TURBOBUS pin high if the bus cycle is determined to be TurboBus access. This will turn off a bidirectional buffer 11 and resistors 12 will keep the command strobes high so that the ISA bus will have no detectable activities by the peripherals.

During a standard ISA bus cycle, TURBOBUS pin will be low, and the bidirectional buffer 11 will be enabled. This allow the command strobes to be passed to the ISA bus. During a master mode cycle, the direction of the bidirectional buffer 11 will be turned around and the command strobes from the ISA bus peripheral will be driving command strobes of the device on Turbo Bus and the control circuit 9, which become inputs during a master mode.

As shown in Figure 2, the bidirectional buffer 11 is employed to support bus master operation by ISA bus peripherals. Using TURBOBUS signal to disable the bidirectional buffer 11 effectively blocks the Turbo Bus strobes from the ISA bus.

For the Turbo Bus to maximize usefulness, the system of the present invention has to determine whether the current cycle is a Turbo Bus cycle to switch the clock from 8 MHz to the pre-programmed TURBOCLK as soon as possible. Local bus systems use an LDEV# signal for this purpose, but ISA bus peripherals do not commonly have such a signal. Also, since the ISA bus strobes must be disabled for Turbo Bus cycles, performance would be degraded significantly by waiting for the peripheral to reply to its address.

To get around this problem, the control circuit 9 of the present invention, as shown in Figure 2, has programmable Turbo Bus decoding units built in. As one example there may be three separate decoding units. Two of these are general purpose, one for a programmable I/O address range and the other for a programmable memory address range, and the third is hard wired to cover all the I/O and memory addresses normally used by VGA-compatible display adapters. Figure 3 shows a programmer's view of these decoding blocks.

Referring to Figure 3A, the register, Reg 0, is part of the Programmable I/O address decoding block. Bit 15 to Bit 11 are reserved. Bit 10, if set, will identify the device on Turbo Bus as a 16-bit device and will enable on-chip IOCS16# generation if the programmed address range is being accessed. Bit 9 to Bit 0 represents ISA bus addresses SA9 to SAO which specify the address to which the Turbo Bus peripheral will respond. Corresponding bits in Reg 1 (Bit 7 to Bit 0 only) indicate which of the address bits will be compared (if set) or ignored (if cleared) .

Bit 11 of Reg 1, when set, is used to enable the entire decoding block, which will be disabled otherwise. If Bit 10 of Reg 1 is 0, it is an indication that it is an I/O decoding block. Bit 9 of Reg 1, when set, will enable Turbo Bus timing on read cycles while Bit 8 governs the write cycles. For example, if an 16-bit IDE HDD controller is sitting on the Turbo Bus with I/O address range of 1F0-1F7 (hexadecimal) , and it can handle Turbo Bus cycles on both read and write, the Reg 0 and Reg 1 should be programmed to the values as shown in the following TABLE 1.

TABLE 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reg 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 Reg 1 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 The Programmable Memory address decoding block is defined in a similar manner, as shown in Figure 3B. Bit 10 of Reg 2, when set, will enable on-chip MEMCS16# generation when the programmed address range is being accessed. Bit 9 to Bit 0 of Reg 2 represents ISA bus address bits 23 to 14. Corresponding bits in Reg 3 (Bit 7 to Bit 0 only) indicate which of the address bits will be compared (if set) or ignored (if cleared) .

For example, if the system wants to access a 1MB 16-bit ISA bus memory block starting at 8 MB address boundary, but it can perform Turbo Bus timing only on a write cycle but not on a read cycle, the Reg 2 and Reg 3 should be programmed to the values as shown in the following TABLE 2.

TABLE 2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reg 2 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Reg 3 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0

I/O port decoding for VGA adapters may be too complex to be defined by one or two programmable blocks, so the control circuit 9 may provide a hard wired decode specifically for VGA. The memory block between OAOOOOh and OBFFFFh is included in the video Turbo Bus decode as well as the following I/O ports:

3B4h, 3B5h, 3BAh, #C0h, 3Clh, 3C2h, 3C4h, 3C5h, 3CAh, 3CCh, 3CEh, 3CFh, 3D4h, 3D5h and 3DAh

The I/O and memory addresses can be placed on the Turbo Bus individually.

Another advantage of the present invention is the resolution of OWS# and MEMCS16# or I0CS16# timing generation, at increased bus speeds. At higher bus speeds, the need for -li¬

the peripheral to return MEMCS16# or IOCS16# becomes a limiting factor to performance. These signals must both be returned to the system control circuit 9 before the start of the memory or I/O strobe signal. The limitation becomes severe with a high speed bus such as the Turbo Bus of the present invention. The programmable decode block solves this problem totally with a pre-defined bus width of the access associated with the programmed address range so that the MEMCS16# or the IOCS16# can be generated on-chip when the programmed address range is detected. Therefore, in the Turbo Bus cycle, the MEMCS16# or IOCS16# timing will be DON'T CARE as shown in Figure 4B.

The timing of OWS# is difficult even with an ISA bus running at 8 MHz as it is sampled in the middle of the 1st Tc as shown in Figure 4A. The circuit of the present invention relaxes the timing by sampling OWS# at the end of 1st Tc to allow proper zero wait-state operation at speed of the Turbo Bus, as shown in Figure 4B.

Per IBM's™ original PC/AT™ standard, the OWS# must not go active until MEMR# or MEMW# go active from the system. This happens at the rising edge of SYSCLK for 16-bit memory operations. OWS# is then sampled at the falling edge of SYSCLK. The present invention has retained this exact timing for 100% ISA compatibility, but for Turbo Bus accesses, the sample point of OWS# is moved to the next SYSCLK rising edge, as shown in Figure 4b. This gives the Turbo Bus peripheral more time to activate OWS# in response to MEMR# or MEMW#.

Although Turbo Bus cycles run with a faster clock, they still use the same relative timing as ISA bus cycles. This means that 16-bit accesses typically run in three TURBOCLK cycles, and 8-bit accesses typically run in six TURBOCLK cycles. As shown in Figures 5A and 5B, however, the circuit of the present invention has programmable options to further enhance I/O performance of an 8-bit peripheral access. An option bit called TURBOBUSII can select the faster 16-bit timing to be used in place of 8-bit timing even when accessing 8-bit Turbo Bus I/O ports, as shown in Figures 5A and 5B. This cuts the cycle time by 50% (from 4 WS or 6 CLK to 1 WS or 3 CLK) which will effectively double the performance at same clock rate. Figure 5A shows the 8-bit Turbo Bus cycle using the same relative timing of ISA bus cycles. Figure 5B shows the 8-bit Turbo Bus cycle with the TURBOBUSII feature turned ON. This option also makes a zero-wait 8-bit Turbo Bus cycle possible.

Many video graphic adapters (VGA) controllers need to add wait states when memory reads and writes are performed to a display memory. This is performed by means of de-asserting IOCHRDY. However, one potential problem with accessing a VGA adapter on the Turbo Bus is that their timing on IOCHRDY was optimized for use with an 8 MHz ISA bus. In that case, IOCHRDY can go from low to high as much as 60ns before the data is actually valid on the bus. Many video adapters make IOCHRDY high well before they actually present their data. Such an adapter would fail on an unmodified Turbo Bus because the MEMR# strobe would be turned off before the data ever becomes valid on the SD bus. The unmodified Turbo Bus cycle with added wait states is shown in Figure 6A.

To overcome this problem, the present invention may further provide an option bit TBRDYDLY which, when activated, will delay acceptance of IOCHRDY on the Turbo Bus, as shown in Figures 6A and 6B.

Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.

Claims

Claims ;

1. A high speed bus system comprising:

means for generating first and second clock signals, the first clock signal being at a first frequency and the second clock signal being at a second frequency, the second frequency being greater than the first frequency;

a first industry standard bus input means to which peripherals to operate at the first clock signal frequency may be connected;

a second high speed bus input means to which peripherals to operate at the second clock signal frequency may be connected, the peripherals connected to the second high speed bus input means operating at a higher speed than the peripherals connected to the first industry standard bus input means; and

programmable decode means for identifying which peripherals are connected to the second high speed bus input means.

2. The high speed bus system according to Claim 1, wherein the means for generating the first and second clock signals comprises:

an input means for receiving an input clock signal;

a first clock divider means connected to the input means for dividing the input clock signal to generate the first clock signal; and

a second clock divider means connected to the input means for dividing the input clock signal to generate the second clock signal.

3. The high speed bus system according to Claim 1, wherein the programmable decode means comprises at least one decoding block for storing an address of a peripheral connected to the second high speed bus means.