AU6622294A - Two speed bus clock allowing operation of high speed peripherals - Google Patents

Two speed bus clock allowing operation of high speed peripherals

Info

Publication number
AU6622294A
AU6622294A AU66222/94A AU6622294A AU6622294A AU 6622294 A AU6622294 A AU 6622294A AU 66222/94 A AU66222/94 A AU 66222/94A AU 6622294 A AU6622294 A AU 6622294A AU 6622294 A AU6622294 A AU 6622294A
Authority
AU
Australia
Prior art keywords
bus clock
peripherals
allowing operation
high speed
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU66222/94A
Inventor
John D Kenny
Robert H. J Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Picopower Tech Inc
Original Assignee
Picopower Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Picopower Tech Inc filed Critical Picopower Tech Inc
Publication of AU6622294A publication Critical patent/AU6622294A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
AU66222/94A 1993-04-02 1994-04-01 Two speed bus clock allowing operation of high speed peripherals Abandoned AU6622294A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US041994 1987-04-24
US4199493A 1993-04-02 1993-04-02
PCT/US1994/003424 WO1994023370A1 (en) 1993-04-02 1994-04-01 Two speed bus clock allowing operation of high speed peripherals

Publications (1)

Publication Number Publication Date
AU6622294A true AU6622294A (en) 1994-10-24

Family

ID=21919483

Family Applications (1)

Application Number Title Priority Date Filing Date
AU66222/94A Abandoned AU6622294A (en) 1993-04-02 1994-04-01 Two speed bus clock allowing operation of high speed peripherals

Country Status (2)

Country Link
AU (1) AU6622294A (en)
WO (1) WO1994023370A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5958033A (en) * 1997-08-13 1999-09-28 Hewlett Packard Company On- the-fly partitionable computer bus for enhanced operation with varying bus clock frequencies
US6134621A (en) * 1998-06-05 2000-10-17 International Business Machines Corporation Variable slot configuration for multi-speed bus

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237676A (en) * 1989-01-13 1993-08-17 International Business Machines Corp. High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device
US5191657A (en) * 1989-11-09 1993-03-02 Ast Research, Inc. Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus
US5263172A (en) * 1990-04-16 1993-11-16 International Business Machines Corporation Multiple speed synchronous bus having single clock path for providing first or second clock speed based upon speed indication signals
US5191581A (en) * 1990-12-07 1993-03-02 Digital Equipment Corporation Method and apparatus for providing high performance interconnection between interface circuits coupled to information buses

Also Published As

Publication number Publication date
WO1994023370A1 (en) 1994-10-13

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