WO1994017549A1 - Off-chip conductor structure and fabrication method for large integrated microcircuits - Google Patents

Off-chip conductor structure and fabrication method for large integrated microcircuits Download PDF

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Publication number
WO1994017549A1
WO1994017549A1 PCT/US1994/000373 US9400373W WO9417549A1 WO 1994017549 A1 WO1994017549 A1 WO 1994017549A1 US 9400373 W US9400373 W US 9400373W WO 9417549 A1 WO9417549 A1 WO 9417549A1
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Prior art keywords
layer
dielectric layer
substrate
conductor
interconnect
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Application number
PCT/US1994/000373
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French (fr)
Inventor
Ronald L. Williams
Ronald M. Finnila
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Hughes Aircraft Company
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Publication date
Application filed by Hughes Aircraft Company filed Critical Hughes Aircraft Company
Priority to GB9418875A priority Critical patent/GB2281659B/en
Priority to JP6517075A priority patent/JP2601640B2/en
Publication of WO1994017549A1 publication Critical patent/WO1994017549A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention generally relates to the art of very large integrated circuits or Multi-Chip-Module (MCM) microcircuits, and more specifically to an arrangement which locates power and other conductor lines on a struc ⁇ ture which is separate from the integrated circuit chip or the module chips and enables the fabrication of extremely large modules or chips with high heat dissipation.
  • MCM Multi-Chip-Module
  • an MCM includes a substrate on which one or more integrated icrocircuit chips are mounted.
  • the substrate has a multilevel structure including alternating patterned metal conductor and dielectric layers.
  • the conductors layers are formed by thin film screen printing, sputtering or plating, and are patterned as lines and planes to provide power and signal interconnections between chips.
  • Vertical interconnects are formed through the dielectric layers to appropriately interconnect adjacent conductor layers.
  • the dielectric layers are formed by deposition of polyi ide.
  • MCMs Although suitable for numerous applications, MCMs have been limited by the low resolution of current fabrication technology to relatively simple configurations.
  • the metal lines in the conductor layers are typically 13 micrometers wide, 3 micrometers thick, and are spaced from each other by 25 micrometers. The lines are too wide and far apart to enable high density arrangements.
  • the polyimide dielectric layers are poor conductors of heat, and complicated heat sinks are required to dissipate the heat generated in the chips and substrate.
  • conventional MCM fabrication is generally a low yield process due to technical difficulties including the formation of large metal areas and planar- ization problems associated with multiple level conductor patterns.
  • a method of fabricating an electrical conductor structure embodying the present invention includes thermal ⁇ ly processing a silicon carrier wafer to produce a silicon dioxide layer on a surface thereof. A patterned metal conductor layer is formed on the silicon dioxide layer.
  • a silicon nitride layer is formed on the conductor layer and exposed areas of the silicon dioxide layer. Vias are formed through the silicon nitride layer for ohmic contact to appropriate points of the conductor layer pattern. Thick metal contact layers are formed on the silicon nitride layer in ohmic connection with the vias, and indium bumps are formed on the contact layers.
  • the carrier which serves as a support during process ⁇ ing, is removed by etching, with the silicon dioxide layer acting as a etch stop.
  • Integrated circuit chips or a very large single chip are mounted on the silicon dioxide layer and connected to the conductor pattern through openings formed in the silicon dioxide layer.
  • a substrate which has electrical circuitry and bumps formed thereon is adhered to the silicon nitride layer, with the circuitry being connected to the conductor layer by the bumps.
  • the conductor pattern provides power and other interconnects for the chips and circuitry on the substrate, thereby increasing the size and density of circuit integra ⁇ tion and improving heat dissipation.
  • the present method allows metal conductor layers to be fabricated off-chip for later attachment through bumps or diffused contacts. This enables chips to be fabricated with high yield, since metal shorts are eliminated.
  • the present conductor structure is fabricated on silicon using standard silicon processing technology.
  • the conductor pattern is formed by chemical vapor deposition, which has at least an order of magnitude higher resolution than the processes used to form conductor patterns in conventional MCM substrates. This enables the fabrication of extremely large chips. Heat dissipation is more efficient with the present structure than with a conventional MCM structure, because the thermal drain paths include silicon oxides (glass) and metal which have higher thermal conductivity than poly ⁇ imide.
  • the present invention facilitates the fabrication of chips without the process problems involved in producing large metal areas or the planarization problems associated with multiple level metal interconnects on the chips. The ability to move metal routing off chips allows the produc- tion of large, thick power conductors which avoid resis ⁇ tance drops in supplying power.
  • FIG. 1 is a simplified sectional view illustrating an exemplary electrical conductor structure embodying the present invention
  • FIGs. 2 to 11 are simplified sectional views illus ⁇ trating a method of fabricating the structure of FIG. 1 in accordance with the invention.
  • FIG. 1 An electrical conductor structure 10 embodying the present invention is illustrated in FIG. 1, and includes a silicon dioxide outer dielectric layer 12 and a silicon nitride inner dielectric layer 14.
  • the layers 12 and 14 are each approximately one micrometer thick.
  • the silicon nitride layer 14 is extremely strong and durable, and provides effective structural rigidity even though it is very thin.
  • a patterned aluminum conductor layer 16 is formed on the lower (as viewed in FIG. 1) surface of the dielectric layer 12 such that the dielectric layer 14 covers the conductor layer 16 and exposed areas of the dielectric layer 12.
  • the conductor layer 16 is patterned to provide electrical interconnections between chips mounted on the dielectric layer 12 and circuitry provided on another structure as will be described below.
  • the primary intended function of the conductor layer 16 is D.C. power distribution.
  • the scope of the invention is not so limited, and the conductor layer 16 can be patterned to carry signals in any practical frequency range as required.
  • the particular pattern of the layer 16 is not the subject matter of the invention, and is designed in accordance with each individual application.
  • the arrange ⁇ ment illustrated in FIG. 1 is exemplary, and is greatly simplified for explaining the principles of the invention.
  • the conductor layer 16 will typically be patterned into a very large number of individual conductive lines in a practical application.
  • the conductor layer 16 is illustrated as including a first section 16a and a second section 16b which are electrically insulated from each other by the dielectric layers 12 and 14. .
  • An integrated circuit chip 18 is mounted on the dielectric layer 12 by an adhesive or the like.
  • Metal bonding pads 20 and 22 are provided on the chip 18 for interconnection with the sections 16a and 16b respec ⁇ tively. Openings 24 and 26 are formed through the outer dielectric layer 12 such that the sections 16a and 16b of the conductor layer 16 are exposed.
  • the pads 20 and 22 are connected to the sections 16a and 16b by wirebonds 28 and 30 which extend through the openings 24 and 26 respective ⁇ ly.
  • Conductive aluminum vias 32, 34 and 36 extend through openings in the inner dielectric layer 14.
  • the via 32 is ohmically connected to the left end portion of the section 16a of the conductor layer 16, whereas the vias 34 and 36 are ohmically connected to the left and right end portions of the section 16b respectively.
  • Conductive aluminum contact layers 38, 40 and 42 are formed on the inner dielectric layer 14 in ohmic connection therewith, and are preferably integral with the vias 32, 34 and 36 respective ⁇ ly.
  • the current carrying capacity of the structure 10 can be increased by forming intermediate layers 44, 46 and 48. preferably of copper, on the contact layers 38, 40 and 42 respectively.
  • Bumps 50, 52 and 54, preferably of indium. are formed on the intermediate layers 44, 46 and 48 respectively and protrude from the inner dielectric layer 14.
  • Each combination of contact layer, intermediate layer and bump constitutes an outer interconnect.
  • a dielectric semiconductor wafer or resin substrate 56 has electrical circuitry formed thereon.
  • the substrate 56 can be an integrated circuit chip package, especially for a very large chip such as a processor, an MCM structure having conductors and resistors formed thereon, or any other suitable electronic element.
  • thick copper conductors 58, 60 and 62 are formed on the upper surface of the substrate 56, and aluminum contact layers 64, 66 and 68 are formed on the conductors 58, 60 and 62 respectively.
  • Indium bumps 70, 72 and 74 are formed on the contact layers 64, 66 and 68 respectively and protrude from the substrate 56.
  • a polysilicon resistor 76 is formed on the substrate 56 and ohmically contacts the conductors 58 and 60 and contact layers 64 and 66 at its opposite ends respectively.
  • Each combination of conductor layer, contact layer and bump constitutes an inner interconnect.
  • the space between the inner dielectric layer 14 and the substrate 56 is filled with an adhesive 78 such as epoxy which bonds the substrate 56 to the layer 14.
  • an adhesive 78 such as epoxy which bonds the substrate 56 to the layer 14.
  • FIG. 1 illustrates the types of interconnections which are provided by the present structure 10.
  • the conductor section 16a provides connection between the conductor layer 58 on the substrate 56 and the bonding pad 20 on the chip 18.
  • the conductor section 16b provides connection between the conductor layers 60 and 62 on the substrate 56, and also between the conductor layers 60 and 62 and the bonding pad 22 on the chip 18.
  • the conductor sections 16a and 16b provide connection of the bonding pads 20 and 22 on the chip 18 across the resistor 76 on the substrate 56.
  • the present structure 10 enables the following interconnections in any desired arrangement and combination.
  • a material 80 includes a carrier 82 in the form of a silicon wafer, with the silicon dioxide outer dielectric layer 12 being formed thereon. Silicon dioxide is a thermal oxide, and the layer 12 is formed by thermally processing the surface of the carrier 82 in a known manner.
  • the carrier 82 is sacrificial, and is provided to act as a support during subsequent processing steps.
  • a preferred thickness for the carrier 82 is 525 micrometers.
  • the present invention is not limited to any particular material system, the combination of silicon for the carrier 82 and silicon dioxide for the outer dielectric layer 12 is preferred because silicon dioxide is resistant to potassium hydroxide etchant (as will be understood from further description) , and silicon is capable of withstand- ing the high processing temperature (approximately 1,000°C) required to thermally form silicon dioxide.
  • the silicon oxides (glasses) also have high thermal conductivity compared to the polyimide dielectric layers of conventional MCMs, providing increased heat dissipation.
  • FIG. 3 illustrates the formation of the patterned conductor layer 16 on the dielectric layer 12.
  • the layer 16 is formed using standard silicon processing, which enables much higher resolution than conventional MCM fabrication technology and a correspondingly large number of thinner conductor lines in a given space. Conductor lines with 2 - 4 micrometer pitch are attainable in accordance with the present invention. This enables the fabrication of extremely large chips.
  • the sections 16a and 16b are patterned by uniformly depositing aluminum (which may include approximately 1% silicon) to a thickness of typically 7,500 angstroms on the layer 12 using chemical vapor deposition (CVD) or other appropriate process.
  • a photoresist mask (not shown) is formed on the layer 16 using standard photolithography to delineate the sections 16a and 16b, and the areas of the layer 16 other than the sections 16a and 16b are etched away. The mask is then removed to produce the structure illustrated in FIG. 3.
  • the silicon nitride inner dielectric layer 14 is deposited on the sections 16a and 16b of the conduc ⁇ tor layer 16 and the exposed portions of the surface of the outer dielectric layer 12 using CVD.
  • photolith ⁇ ography and etching are used to delineate and form via openings 84, 86 and 88 through the layer 14 which expose the underlying portions of the conductor layer 16.
  • FIG. 6 illustrates how the vias 32, 34 and 36 and contact layers 38, 40 and 42 are integrally formed.
  • a layer of aluminum (which may include approximately 1% silicon) is deposited to a thickness of approximately 7,500 - 11,000 angstroms using CVD over the inner dielectric layer 14 and fills the openings 84, 86 and 88 to form the vias 36, 34 and 32 respectively.
  • the aluminum layer is then patterned and etched using photolithography to delineate the contact layers 38, 40 and 42.
  • FIG. 7 illustrates formation of the intermediate layers 44, 46 and 48 on the contact layers 38, 40 and 42 respectively.
  • the layers 44, 46 and 48 are preferably formed by deposition of copper using CVD to a thickness of approximately 3 - 6 micrometers.
  • the indium bumps 50, 52 and 54 are formed on the intermediate layers 44, 46 and 48 using photolitho ⁇ graphy and thermal evaporation to a thickness of approxi ⁇ mately 9 micrometers.
  • the copper intermediate layers 44, 46 and 48 are very thin compared to conventional MCM conductor layers. This enables the present structure 10 to have a substantially higher current carrying capacity than conventional MCMs.
  • the carrier 82 serves as a support for the standard silicon processing steps described above. Upon completion, the carrier 82 is removed as illustrated in FIG. 9. As indicated by arrows 90, the carrier 82 is etched away using potassium hydroxide etchant. The silicon dioxide outer dielectric layer 12 is resistant to potassium hydroxide and acts as an etch stop. It will be noted that the structure as illustrated in FIG. 9 is inverted from its orientation in FIG. 8.
  • the openings 24 and 26 are formed through the outer dielectric layer 12 using photolithography and etching.
  • the structure of FIG. 10 is attached to the substrate 56.
  • the adhesive 78 is applied to the inner dielectric layer 14 and/or the substrate 56, and the substrate 56 is pressed against the layer 14 and retained such that the bumps 50, 52 and 54 which protrude from the layer 14 are mashed against the bumps 70, 72 and 74 which protrude from the substrate 56 and make ohmic contact with each other.
  • the chip 18 is mounted on the outer dielectric layer 12 and the wirebonds 28 and 30 are formed to produce the structure 10 of FIG. 1. While an illustrative embodiment of the invention has been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art, without departing from the spirit and scope of the invention. Accordingly, it is intended that the present invention not be limited solely to the specifically described illustra ⁇ tive embodiment.
  • the indium bumps 50, 52, 54, 70, 72 and 74 can be replaced by diffused contacts or other types of interconnects.
  • the substrate 56 can be replaced with a very large chip which is interconnected with the lower capacitance, higher conductivity metallization of the layers 46 and 48.

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Abstract

A silicon carrier wafer (82) is thermally processed to produce a silicon dioxide layer (12) on a surface thereof. A patterned metal conductor layer (16) is formed on the silicon dioxide layer (12) using silicon processing technology which enables high resolution and density. A silicon nitride layer (14) is formed on the conductor layer (16) and exposed areas of the silicon dioxide layer (12). Vias (32, 34, 36) are formed through the silicon nitride layer (14) for ohmic contact to appropriate points of the conductor layer (16). Thick metal contact layers (38, 40, 42, 44, 46, 48) are formed on the silicon nitride layer (14) in ohmic connection with the vias (32, 34, 36), and indium bumps (50, 52, 54) are formed on the contact layers (38, 40, 42, 44, 46, 48). The carrier (82), which serves as a support during processing, is removed by etching, with the silicon dioxide layer (12) acting as an etch stop. Integrated circuit chips (18) are mounted on the silicon dioxide layer (2) and connected to the conductor pattern through openings (24, 26) formed in the silicon dioxide layer (12). A substrate (56) which has electrical circuitry (58, 60, 62, 76) and bumps (70, 72, 74) formed thereon is adhered to the silicon nitride layer (14), with the circuitry (58, 60, 62, 76) being connected to the conductor layer (16) by the bumps (50, 52, 54, 70, 72, 74). The conductor layer (16) provides power and other interconnects for the chips (18) and circuitry (58, 60, 62, 76) on the substrate (56), thereby increasing the size and density of circuit integration and improving heat dissipation.

Description

OFF-CHIP CONDUCTOR STRUCTURE AND FABRICATION METHOD FOR LARGE
INTEGRATED MICROCIRCUITS
BACKGROUND OF THE INVENTION Field of the Invention
The present invention generally relates to the art of very large integrated circuits or Multi-Chip-Module (MCM) microcircuits, and more specifically to an arrangement which locates power and other conductor lines on a struc¬ ture which is separate from the integrated circuit chip or the module chips and enables the fabrication of extremely large modules or chips with high heat dissipation.
Description of the Related Art
Hybrid or MCM modules provide reduced size and increased system level performance. As described in an article entitled "Thin Film MCMε, Meeting Advanced CMOS Challenges", Advanced Packing Vol. 1, No. 1, 1992, pp. 46 - 51, an MCM includes a substrate on which one or more integrated icrocircuit chips are mounted. The substrate has a multilevel structure including alternating patterned metal conductor and dielectric layers. The conductors layers are formed by thin film screen printing, sputtering or plating, and are patterned as lines and planes to provide power and signal interconnections between chips. Vertical interconnects (vias) are formed through the dielectric layers to appropriately interconnect adjacent conductor layers. The dielectric layers are formed by deposition of polyi ide.
Although suitable for numerous applications, MCMs have been limited by the low resolution of current fabrication technology to relatively simple configurations. The metal lines in the conductor layers are typically 13 micrometers wide, 3 micrometers thick, and are spaced from each other by 25 micrometers. The lines are too wide and far apart to enable high density arrangements.
The polyimide dielectric layers are poor conductors of heat, and complicated heat sinks are required to dissipate the heat generated in the chips and substrate. As yet another disadvantage, conventional MCM fabrication is generally a low yield process due to technical difficulties including the formation of large metal areas and planar- ization problems associated with multiple level conductor patterns.
SUMMARY OF THE INVENTION
A method of fabricating an electrical conductor structure embodying the present invention includes thermal¬ ly processing a silicon carrier wafer to produce a silicon dioxide layer on a surface thereof. A patterned metal conductor layer is formed on the silicon dioxide layer.
A silicon nitride layer is formed on the conductor layer and exposed areas of the silicon dioxide layer. Vias are formed through the silicon nitride layer for ohmic contact to appropriate points of the conductor layer pattern. Thick metal contact layers are formed on the silicon nitride layer in ohmic connection with the vias, and indium bumps are formed on the contact layers.
The carrier, which serves as a support during process¬ ing, is removed by etching, with the silicon dioxide layer acting as a etch stop. Integrated circuit chips or a very large single chip are mounted on the silicon dioxide layer and connected to the conductor pattern through openings formed in the silicon dioxide layer. A substrate which has electrical circuitry and bumps formed thereon is adhered to the silicon nitride layer, with the circuitry being connected to the conductor layer by the bumps. The conductor pattern provides power and other interconnects for the chips and circuitry on the substrate, thereby increasing the size and density of circuit integra¬ tion and improving heat dissipation. The present method allows metal conductor layers to be fabricated off-chip for later attachment through bumps or diffused contacts. This enables chips to be fabricated with high yield, since metal shorts are eliminated.
The present conductor structure is fabricated on silicon using standard silicon processing technology. The conductor pattern is formed by chemical vapor deposition, which has at least an order of magnitude higher resolution than the processes used to form conductor patterns in conventional MCM substrates. This enables the fabrication of extremely large chips. Heat dissipation is more efficient with the present structure than with a conventional MCM structure, because the thermal drain paths include silicon oxides (glass) and metal which have higher thermal conductivity than poly¬ imide. The present invention facilitates the fabrication of chips without the process problems involved in producing large metal areas or the planarization problems associated with multiple level metal interconnects on the chips. The ability to move metal routing off chips allows the produc- tion of large, thick power conductors which avoid resis¬ tance drops in supplying power. Three and four layer metal interconnect structures with large current carrying capacity are feasible because the planarization yield and associated technical problems are eliminated. These and other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which like reference numerals refer to like parts.
DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified sectional view illustrating an exemplary electrical conductor structure embodying the present invention; and FIGs. 2 to 11 are simplified sectional views illus¬ trating a method of fabricating the structure of FIG. 1 in accordance with the invention.
DETAILED DESCRIPTION OF THE INVENTION An electrical conductor structure 10 embodying the present invention is illustrated in FIG. 1, and includes a silicon dioxide outer dielectric layer 12 and a silicon nitride inner dielectric layer 14. The layers 12 and 14 are each approximately one micrometer thick. The silicon nitride layer 14 is extremely strong and durable, and provides effective structural rigidity even though it is very thin.
A patterned aluminum conductor layer 16 is formed on the lower (as viewed in FIG. 1) surface of the dielectric layer 12 such that the dielectric layer 14 covers the conductor layer 16 and exposed areas of the dielectric layer 12. The conductor layer 16 is patterned to provide electrical interconnections between chips mounted on the dielectric layer 12 and circuitry provided on another structure as will be described below.
The primary intended function of the conductor layer 16 is D.C. power distribution. However, the scope of the invention is not so limited, and the conductor layer 16 can be patterned to carry signals in any practical frequency range as required. The particular pattern of the layer 16 is not the subject matter of the invention, and is designed in accordance with each individual application. The arrange¬ ment illustrated in FIG. 1 is exemplary, and is greatly simplified for explaining the principles of the invention. The conductor layer 16 will typically be patterned into a very large number of individual conductive lines in a practical application.
The conductor layer 16 is illustrated as including a first section 16a and a second section 16b which are electrically insulated from each other by the dielectric layers 12 and 14. .An integrated circuit chip 18 is mounted on the dielectric layer 12 by an adhesive or the like. Metal bonding pads 20 and 22 are provided on the chip 18 for interconnection with the sections 16a and 16b respec¬ tively. Openings 24 and 26 are formed through the outer dielectric layer 12 such that the sections 16a and 16b of the conductor layer 16 are exposed. The pads 20 and 22 are connected to the sections 16a and 16b by wirebonds 28 and 30 which extend through the openings 24 and 26 respective¬ ly.
Conductive aluminum vias 32, 34 and 36 extend through openings in the inner dielectric layer 14. The via 32 is ohmically connected to the left end portion of the section 16a of the conductor layer 16, whereas the vias 34 and 36 are ohmically connected to the left and right end portions of the section 16b respectively. Conductive aluminum contact layers 38, 40 and 42 are formed on the inner dielectric layer 14 in ohmic connection therewith, and are preferably integral with the vias 32, 34 and 36 respective¬ ly.
The current carrying capacity of the structure 10 can be increased by forming intermediate layers 44, 46 and 48. preferably of copper, on the contact layers 38, 40 and 42 respectively. Bumps 50, 52 and 54, preferably of indium. are formed on the intermediate layers 44, 46 and 48 respectively and protrude from the inner dielectric layer 14. Each combination of contact layer, intermediate layer and bump constitutes an outer interconnect. A dielectric semiconductor wafer or resin substrate 56 has electrical circuitry formed thereon. The substrate 56 can be an integrated circuit chip package, especially for a very large chip such as a processor, an MCM structure having conductors and resistors formed thereon, or any other suitable electronic element. As illustrated, thick copper conductors 58, 60 and 62 are formed on the upper surface of the substrate 56, and aluminum contact layers 64, 66 and 68 are formed on the conductors 58, 60 and 62 respectively. Indium bumps 70, 72 and 74 are formed on the contact layers 64, 66 and 68 respectively and protrude from the substrate 56. A polysilicon resistor 76 is formed on the substrate 56 and ohmically contacts the conductors 58 and 60 and contact layers 64 and 66 at its opposite ends respectively. Each combination of conductor layer, contact layer and bump constitutes an inner interconnect.
The space between the inner dielectric layer 14 and the substrate 56 is filled with an adhesive 78 such as epoxy which bonds the substrate 56 to the layer 14. During fabrication, the bumps 70, 72 and 74 which protrude from the substrate 56 are aligned with the bumps 44, 46 and 48 which protrude from the inner dielectric layer 14. The substrate 56 is pressed against the layer 14 so that the respective bumps are mashed together and make ohmic contact with each other.
FIG. 1 illustrates the types of interconnections which are provided by the present structure 10. The conductor section 16a provides connection between the conductor layer 58 on the substrate 56 and the bonding pad 20 on the chip 18. The conductor section 16b provides connection between the conductor layers 60 and 62 on the substrate 56, and also between the conductor layers 60 and 62 and the bonding pad 22 on the chip 18. The conductor sections 16a and 16b provide connection of the bonding pads 20 and 22 on the chip 18 across the resistor 76 on the substrate 56.
In summary, the present structure 10 enables the following interconnections in any desired arrangement and combination.
1. Between any two points on the outer dielectric layer 12.
2. Between any two points on the substrate 56.
3. Between any point on the outer dielectric layer 12 and any point on the substrate 56.
A method of fabricating the present conductor struc- ture 10 is illustrated in FIGs. 2 to 11. In FIG. 2, a material 80 includes a carrier 82 in the form of a silicon wafer, with the silicon dioxide outer dielectric layer 12 being formed thereon. Silicon dioxide is a thermal oxide, and the layer 12 is formed by thermally processing the surface of the carrier 82 in a known manner. The carrier 82 is sacrificial, and is provided to act as a support during subsequent processing steps. A preferred thickness for the carrier 82 is 525 micrometers.
Although the present invention is not limited to any particular material system, the combination of silicon for the carrier 82 and silicon dioxide for the outer dielectric layer 12 is preferred because silicon dioxide is resistant to potassium hydroxide etchant (as will be understood from further description) , and silicon is capable of withstand- ing the high processing temperature (approximately 1,000°C) required to thermally form silicon dioxide. The silicon oxides (glasses) also have high thermal conductivity compared to the polyimide dielectric layers of conventional MCMs, providing increased heat dissipation. FIG. 3 illustrates the formation of the patterned conductor layer 16 on the dielectric layer 12. The layer 16 is formed using standard silicon processing, which enables much higher resolution than conventional MCM fabrication technology and a correspondingly large number of thinner conductor lines in a given space. Conductor lines with 2 - 4 micrometer pitch are attainable in accordance with the present invention. This enables the fabrication of extremely large chips.
The sections 16a and 16b are patterned by uniformly depositing aluminum (which may include approximately 1% silicon) to a thickness of typically 7,500 angstroms on the layer 12 using chemical vapor deposition (CVD) or other appropriate process. A photoresist mask (not shown) is formed on the layer 16 using standard photolithography to delineate the sections 16a and 16b, and the areas of the layer 16 other than the sections 16a and 16b are etched away. The mask is then removed to produce the structure illustrated in FIG. 3.
In FIG. 4, the silicon nitride inner dielectric layer 14 is deposited on the sections 16a and 16b of the conduc¬ tor layer 16 and the exposed portions of the surface of the outer dielectric layer 12 using CVD. In FIG. 5, photolith¬ ography and etching are used to delineate and form via openings 84, 86 and 88 through the layer 14 which expose the underlying portions of the conductor layer 16.
FIG. 6 illustrates how the vias 32, 34 and 36 and contact layers 38, 40 and 42 are integrally formed. A layer of aluminum (which may include approximately 1% silicon) is deposited to a thickness of approximately 7,500 - 11,000 angstroms using CVD over the inner dielectric layer 14 and fills the openings 84, 86 and 88 to form the vias 36, 34 and 32 respectively. The aluminum layer is then patterned and etched using photolithography to delineate the contact layers 38, 40 and 42. FIG. 7 illustrates formation of the intermediate layers 44, 46 and 48 on the contact layers 38, 40 and 42 respectively. The layers 44, 46 and 48 are preferably formed by deposition of copper using CVD to a thickness of approximately 3 - 6 micrometers. In FIG. 8, the indium bumps 50, 52 and 54 are formed on the intermediate layers 44, 46 and 48 using photolitho¬ graphy and thermal evaporation to a thickness of approxi¬ mately 9 micrometers.
The copper intermediate layers 44, 46 and 48 are very thin compared to conventional MCM conductor layers. This enables the present structure 10 to have a substantially higher current carrying capacity than conventional MCMs.
The carrier 82 serves as a support for the standard silicon processing steps described above. Upon completion, the carrier 82 is removed as illustrated in FIG. 9. As indicated by arrows 90, the carrier 82 is etched away using potassium hydroxide etchant. The silicon dioxide outer dielectric layer 12 is resistant to potassium hydroxide and acts as an etch stop. It will be noted that the structure as illustrated in FIG. 9 is inverted from its orientation in FIG. 8.
In FIG. 10, the openings 24 and 26 are formed through the outer dielectric layer 12 using photolithography and etching. In FIG. 11, the structure of FIG. 10 is attached to the substrate 56.
More specifically, the adhesive 78 is applied to the inner dielectric layer 14 and/or the substrate 56, and the substrate 56 is pressed against the layer 14 and retained such that the bumps 50, 52 and 54 which protrude from the layer 14 are mashed against the bumps 70, 72 and 74 which protrude from the substrate 56 and make ohmic contact with each other. Upon curing of the adhesive 78, the chip 18 is mounted on the outer dielectric layer 12 and the wirebonds 28 and 30 are formed to produce the structure 10 of FIG. 1. While an illustrative embodiment of the invention has been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art, without departing from the spirit and scope of the invention. Accordingly, it is intended that the present invention not be limited solely to the specifically described illustra¬ tive embodiment.
For example, the indium bumps 50, 52, 54, 70, 72 and 74 can be replaced by diffused contacts or other types of interconnects. Also, the substrate 56 can be replaced with a very large chip which is interconnected with the lower capacitance, higher conductivity metallization of the layers 46 and 48.
Various modifications are contemplated and can be made without departing from the spirit and scope of the inven- tion as defined by the appended claims.

Claims

WE CLAIM:
1. An electrical conductor structure, comprising: a thermal oxide outer dielectric layer; a patterned conductor layer formed over a surface of the outer dielectric layer; an inner dielectric layer formed over the conductor layer and exposed areas of said surface; and a conductive outer interconnect which extends through the inner dielectric layer and is ohmically connected to the conductor layer.
2. A structure as in claim 1, in which the outer dielectric layer includes silicon dioxide.
3. A structure as in claim 1, in which the inner dielectric layer includes silicon nitride.
4. A structure as in claim 1, in which the outer interconnect comprises a conductive bump which protrudes from the inner dielectric layer.
5. A structure as in claim 4, in which the bump includes indium.
6. A structure as in claim 4, in which: the outer interconnect further comprises: a conductive via which extends through the inner dielectric layer and is ohmically connected to the conductor layer; and a conductive contact layer which is formed over the inner dielectric layer and is ohmically connected to the via; and the bump is formed over the contact layer.
7. A structure as in claim 6, in which: the via and contact layer are integral; the outer interconnect further comprises a conductive intermediate layer formed over the contact layer; and the bump is formed over the intermediate layer.
8. A structure as in claim 7, in which: the contact layer and via include aluminum; and the intermediate layer includes copper.
9. A structure as in claim 1, in which: the outer dielectric layer includes silicon dioxide; and the inner dielectric layer includes silicon nitride.
10. A structure as in claim 9, in which the outer dielectric layer and the inner dielectric layer are each approximately one micrometer thick.
11. A structure as in claim 10, in which the conduc¬ tor layer comprises aluminum.
12. A structure as in claim 10, in which the conduc¬ tor layer is approximately 7,500 angstroms thick.
13. A structure as in claim 1, further comprising an opening which extends through the outer dielectric layer to the conductor layer.
14. A structure as in claim l, further comprising: a substrate; electrical circuit means formed on the substrate; a conductive inner interconnect which is formed on the substrate and is ohmically connected to the circuit means; and retaining means for retaining the substrate conjugate to the inner dielectric layer such that the outer interconnect is ohmically connected to the inner intercon- nect.
15. A structure as in claim 14, in which the outer interconnect and the inner interconnect each include an electrically conductive bump.
16. A structure as in claim 14, in which the retain¬ ing means comprises an adhesive which bonds the inner dielectric layer to the substrate.
17. A method of fabricating an electrical conductor structure, comprising the steps of:
(a) providing a material including a carrier having a thermal oxide outer dielectric layer formed thereon;
(b) forming a patterned conductor layer over the outer dielectric layer;
(c) forming an inner dielectric layer over the conductor layer and exposed areas of the outer dielectric layer;
(d) forming a conductive outer interconnect through the inner dielectric layer such that the outer interconnect is ohmically connected to the conductor layer; and (e) removing the carrier from the outer dielec¬ tric layer.
18. A method as in claim 17, in which step (a) comprises the substeps of:
(f) providing the carrier as including silicon; and (g) thermally processing the carrier to form the thermal oxide layer as including silicon dioxide.
19. A method as in claim 18, in which step (e) comprises etching away the carrier using an etchant to which the outer dielectric layer is resistant.
20. A method as in claim 19, in which step (e) comprises etching away the carrier using said etchant as including potassium hydroxide.
21. A method as in claim 17, in which step (c) comprises deposition of silicon nitride.
22. A method as in claim 17, in which step (d) comprises forming the outer interconnect as comprising an electrically conductive bump which protrudes from the inner dielectric layer.
23. A method as in claim 22, in which step (d) comprises forming the bump as including indium.
24. A method as in claim 17, in which step (d) comprises the substeps of:
(f) forming an opening through the inner dielec¬ tric layer to expose the conductor layer; (g) forming a conductive via in the opening such that the via is ohmically connected to the conductor layer; (h) forming a conductive contact layer over the inner dielectric layer such that the contact layer is ohmically connected to the via; and (i) forming an electrically conductive bump over the contact layer. 24. A method as in claim 23, in which: steps (g) and (h) are performed integrally and include deposition of a conductive material.
25. A method as in claim 24, in which: steps (g) and (h) comprise depositing said conductive material as including aluminum; and step (d) further comprises the εubstep, performed between steps (h) and (i) , of:
(j) forming a conductive intermediate layer which includes copper over the contact layer.
26. A method as in claim 23, in which step (i) comprises forming the bump as including indium.
27. A method as in claim 17, further comprising the step of:
(f) forming an opening through the outer dielec¬ tric layer to expose the conductor layer.
28. A method as in claim 17, further comprising the steps of:
(f) providing a substrate having an electrical circuit means formed thereon; (g) forming an inner interconnect on the sub¬ strate which is electrically connected to the circuit means; and
(h) attaching the substrate to the inner dielec¬ tric layer such that the inner interconnect ohmically contacts the outer interconnect.
29. A method as in claim 28, in which: step (d) comprises forming the outer interconnect as comprising a conductive bump which protrudes from the inner dielectric layer; step (g) comprises forming the inner interconnect as comprising an inner conductive bump which protrudes from the substrate; and step (h) comprises pressing the substrate and inner dielectric layer together such that the inner bump is ohmically pressed against the outer bump.
30. A method as in claim 29, in which: step (h) further comprises applying an adhesive between the substrate and the inner dielectric layer; and step (h) further comprises pressing the substrate and the inner dielectric layer together such that they are adhered to each other by the adhesive.
PCT/US1994/000373 1993-01-19 1994-01-10 Off-chip conductor structure and fabrication method for large integrated microcircuits WO1994017549A1 (en)

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GB9418875D0 (en) 1994-11-09
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GB2281659B (en) 1996-07-03
JPH07506939A (en) 1995-07-27

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