JPH04230067A - Method for integration of wafer scale by arranging and installing fine-shaped chips so as to be adjacent - Google Patents

Abstract

PURPOSE: To minimize a number of mutually connecting networks and the width of connecting lead by forming plural vias through flattened layers onto circuit chips, depositing the vias by patterning metalized layers on the flattened layers formed inside, and electrically connecting plural number of circuit chips inside a module. CONSTITUTION: Flattened layers 14 of insulating materials are added to circuit chips and a substrate 12. The layers 14 communicate spaces among the circuit chips, and thin insulating films are formed on the chips 10. After the flattened layers 14 have been formed, plural vias 16 are formed inside these layers and communicated through the layers 14 with contact pads on the circuit chips 10a-10c. The circuit chips 10a, 10b and 10c are connected electrically by patterning the flattened layers 14, performing a metalizing process to this assembly and forming a line of mutually connecting lattices 18.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD This invention relates generally to the fabrication of electronic modules, and more particularly to modules fabricated from a plurality of integrated circuit chips.

0002

BACKGROUND OF THE INVENTION Traditionally, there have been two types of efforts in assembling electronic modules from individual integrated circuit chips. One of these methods, the flip-chip method, places individual circuit chips on a fired multilayer ceramic substrate. This system allows the use of individually pre-tested chips and also chips of different technologies (CMOS, memory, bipolar, etc.). However, this method has some drawbacks. The dimensions of the chip are limited by the different coefficients of thermal expansion between the ceramic substrate and the material from which the chip is fabricated, traditionally silicon. Such mismatch leads to distortion, which causes separation between the chip and the substrate at high temperature conditions, such as when soldering the chip. The circuit chip is placed upside down and placed on the board with the circuit side facing down, so unless other steps are taken to protect the circuit side, such as applying a protective layer, the chip on the board will remain intact. If it moves, it may damage the circuitry formed on this chip. This manufacturing method also requires multiple ceramic substrates to achieve electrical interconnections between the chips through the substrates. Interconnecting these integrated circuit chips requires multiple insulating and conductive layers because the electrical leads must be screen printed. Although screen printing can produce leads as small as 4 to 10 mils wide, this limits the lead density on each conductive layer, thereby requiring multiple insulating and conductive layers (overall) to interconnect an integrated chip. (up to 17 layers) is required. This also tends to slow down the module due to the capacitance created by the relatively wide leads. Also, because this manufacturing method utilizes flip chip assembly, another fabrication step must be performed on the module.

Other efforts to fabricate electronic modules include:
Wafer scale integration is included, where modules are formed on silicon wafers by well-known masking and etching techniques. This technique allows the use of integrated circuit chips of any size by incorporating the desired chip into the mask/etch process. Chip-to-chip interconnections can be simplified because they can be realized by one or two conductive layers with fine pitch metallization that can be provided directly on the wafer. The fine metal lines interconnecting these chips minimize capacitance and therefore minimize module speed degradation. Compared to screen printing, where the conductor pitch is approximately 100 microns, metallization of integrated circuits is performed with a pitch of 1 to 10 microns. However, redundant circuitry is necessary to prevent loss of an entire wafer due to malfunction of one or more integrated circuits. This reduces the effective circuit density of such wafers. Furthermore, the entire wafer must be processed through all processing steps necessary to form a particular integrated circuit on the wafer. This increases the potential for damage and malfunction of the integrated circuit, making it less attractive to implement modules with multiple technologies.

The present invention provides a method for forming electronic modules from a plurality of small scale integrated circuit chips in a manner that has the advantages of flip chip and wafer scale integration methods, but without the disadvantages of each method. It is. It is an object of the invention to provide an electronic module incorporating a plurality of integrated circuit chips, some of which may be different in type and size from other chips.

Another object of the present invention is to provide a method for making electronic modules from a plurality of precisely formed and pretested integrated circuit chips. Yet another object of the invention is to increase the speed of electronic modules incorporating multiple integrated circuit chips by minimizing the number of interconnect networks required and minimizing the width of electrical interconnect leads. It is about improving.

Still another object of the present invention is to simplify the fabrication of electronic modules incorporating multiple integrated circuits by reducing the number of insulating and conductive layers required for interconnections between chips. The goal is to reduce manufacturing costs and improve reliability.

[0007]

SUMMARY OF THE INVENTION The above and other objects of the present invention are to provide integrated circuits by mounting a plurality of precisely formed integrated circuit chips on a support substrate and bringing these chips into precise contact with each other on the substrate. This is accomplished by forming an array of chips. A flattened insulating film is formed on the circuit chip. Vias are formed in this planarized film to communicate with selected points on each integrated circuit chip. After forming these vias, a patterned metallization layer is formed on this planarization layer in contact with these vias, thereby forming an electrical interconnect network and interconnecting multiple circuit chips within the module. Connect to.

[0008]

[Example] The present invention will be explained with reference to the following drawings.
Identical reference numbers here indicate identical parts. FIG. 1 shows the first steps in making an electronic module. A plurality of integrated circuit chips 10a, 10b and 10c are placed on a support substrate 12. These integrated circuit chips 10
a, 10b and 10c may have different dimensions as shown, or the same dimensions, and may be of various types (CMOS, memory, bipolar, etc.). Ideally, these integrated circuit chips are inspected and tested prior to use, so that only known working chips are placed on support substrate 12. These chips are formed by well known techniques such as precision dicing, particularly dicing employing resinous cutting blades and cutting saws. See also U.S. Pat. No. 4,542,397 to Biegelsen et al.
For example, circuit chips separated from a silicon wafer can be used in this method by the orientation-dependent etching technique disclosed in U.S. Pat. No. 4,830,985 to et al., the disclosures of which are incorporated herein by reference. can do. Similarly, other chip delineation methods may be used as long as circuit chips 10a, 10b, and 10c are formed with edges precisely aligned with the circuitry contained on each chip.
d) and chip separation methods can be used to form these chips. Additionally, the edges of each chip must be sufficiently precise and uniform so that the chips can face each other with minimal spacing between adjacent chips. The chips are arranged on substrate 12 so that each integrated circuit chip is precisely aligned with the other chips to provide maximum circuit density for the module. For this purpose, the precision abutment technique disclosed in US Pat. No. 4,542,397 can be used. For example, adjacent chips can abut against each other to form an array of tightly packed chips. or
It is possible to abut the chips against precision alignment structures formed on the substrate 12, or the chips can be placed, for example, against alignment structures on their base side (opposite the side containing the circuitry). It is also possible to form the alignment structure with a corresponding alignment structure formed on the substrate 12. The latter method is advantageous if the chip 10 has sensing circuitry at its end that can be damaged by abutment.

In wafer-scale or near-wafer-scale integration, circuit chips are mounted on a substrate 12 in a two-dimensional array, as shown in FIG. Circuit chips 10a, b, c extend on substrate 12 in a first direction. The second group of circuit chips 11a, b, c are as follows:
It abuts the chips 10a, b, c and extends the chip array in a second direction on the substrate 12. By repeatedly placing circuit chips in this manner, a two-dimensional array of chips is formed on the substrate 12. These circuit chips are secured onto the substrate by well known techniques such as epoxy adhesive or crystal bonding.

Substrate 12 is preferably made of an inert material and has high thermal conductivity and a coefficient of thermal expansion that is the same or substantially equal to that of chips 10a, 10b, and 10c. Examples of suitable materials are graphite, silicon and alumina. The thermal conductivity of the substrate dissipates heat away from the circuit chips during use, thereby increasing their lifetime. By making the coefficient of thermal expansion of the substrate 12 and the integrated circuit chips 10a, b, c and 11a, b, c (FIG. 5) the same, the chips relative to the substrate will (and thus relative to each other) is minimized.

In situations where it is desirable to ground the system through the backside of the integrated circuit chip, this substrate 1
2 can have a conductive layer 15 of, for example, gold. In such cases, the circuit chip is secured to substrate 12 in a manner that provides electrical interconnections between the backside of the circuit chip and layer 14, such as by silver-loaded epoxy or crystal bonding.

In the next step, shown in FIG. 2, a planarization layer 14 of insulating material is applied to circuit chip 10 and substrate 12. Layer 14 connects the spaces between these circuit chips, forms a substantially planar outer surface, and provides a thin insulating film over the chips. The film 14 is a polyimide film that can be patterned by light, and is preferably formed by polymerization at a suitable location on the module. Film 14 can also be formed by spin deposition of glass or plasma deposition of silicon dioxide or silicon nitride. Techniques of this type are well known to those skilled in the art and there is no need to further describe these steps or materials. The thickness of this layer 14 is determined by the amount of spacing between the circuit chips and is in the range of about 1 to 10 microns when polyimide is used. For example, if the average chip spacing is less than about 1 micron, a film thickness of about 3 microns is desirable.

Referring to FIG. 3, after forming the planarization layer,
A plurality of vias 16 are formed within this planarization layer 14 and layer 1
4 to communicate with the contact pads on the circuit chips 10a to 10c. The formation of this via is performed by the planarization layer 14.
This can be done by known methods, such as photolithographically forming a pattern thereon. This patterned layer 14 is then subjected to a suitable material removal step, such as etching, to remove material from layer 14 and form vias 16. If polyimide is used to form membrane 14, it is desirable to form these vias before the membrane is finally cured, since this type of membrane can be difficult to process. This is because it is difficult to remove once it has finally hardened. Techniques for using such photopatternable polyimides are shown in US Pat. No. 4,774,530 to Hawkins, the disclosure of which is incorporated herein by reference. The pattern of vias 16 corresponds to the known locations of metallized contact pads on chips 10a-10c that must be electrically interconnected with other chips in the module.

Electrical interconnections of circuit chips 10a, 10b and 10c are made by patterning planarization layer 14 and subjecting the assembly to a metallization process to form electrical interconnection grid 18.
This is done by forming lines of . A portion 20 of the grid 18 passes through the membrane 14 within the vias 16 to the circuit chip 10.
a, b, c and 11a, b, c contact pads. Using well-known metallization techniques, such as vapor deposition, the grid 18 can be formed from fine metal lines interconnecting these chips. This minimizes the capacitance of the interconnect system and
Module speed increases. Aluminum is a preferred metallization material because this fine pitch can be achieved by well-known deposition techniques. As metallization material it is possible to use aluminum alloyed with silicon or also aluminum alloyed with copper. The ability to form fine leads allows interconnections to be achieved with only one or two conductive layers. The aluminum or aluminum alloy is deposited to a thickness in the range of about 250 nm to 3 microns, preferably about 1.25 microns, to form fine thin leads.

Referring to FIG. 6, forming a planarization layer 14a on layer 14 to form a second conductive network;
A via 16a is formed through the second insulating film 14a. This second planarization and via formation step is performed as described in connection with membrane 14 and via 16. A second patterned metallization is performed to form a second electrical interconnect network 18a. This network consists of membrane layer 14
has a portion 20a extending through a via formed in a. If a second interconnection network is required, the first
The metallization steps used to form the interconnect network also include forming contact pads on membrane 14. Vias formed in this second film 14a are patterned to communicate with contact pads on layer 14 through this second film.

[0016] After the above steps are completed, the module is provided with a lead frame by well known techniques and encapsulated. The preferred embodiments of the invention described herein are intended to be illustrative and not limiting. Various modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

[Brief explanation of the drawing]

FIG. 1 is an enlarged end view of an electronic module under construction.

2 shows the assembly of FIG. 1 with an insulating layer and a planarization layer provided in FIG. 1a; FIG.

FIG. 3 shows the assembly of FIG. 2 with vias formed in the planarization layer.

FIG. 4 shows a module with an electrical interconnection network formed on the module.

FIG. 5 shows a two-dimensional array of integrated circuit chips.

FIG. 6 is a variant of the module with a second interconnection network;

[Explanation of symbols]

10a, b, c, 11a, b, c circuit chip 12
Substrate 14 Planarization layer of insulating material 15 Conductive layer 16 Via 18 Grid of fine metal wires 20 Extensions

Claims (1)

[Claims] 1. A method of fabricating an electronic module, comprising: placing a plurality of precisely formed integrated circuit chips on a substrate; aligning the chips on the substrate; and aligning the chips on the substrate; forming an array; securing the circuit chips on a substrate; providing a planarizing insulating material on the circuit chips to form a first planarizing layer on the circuit chips; through the planarization layer on the circuit chip; and patterning and depositing at least one metallization layer on the planarization layer with the via formed therein; electrically interconnecting a plurality of circuit chips within the circuit.