WO1994015269A3 - Apparatus, system and method for facilitating communication between components having different byte orderings - Google Patents

Apparatus, system and method for facilitating communication between components having different byte orderings Download PDF

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Publication number
WO1994015269A3
WO1994015269A3 PCT/US1993/012416 US9312416W WO9415269A3 WO 1994015269 A3 WO1994015269 A3 WO 1994015269A3 US 9312416 W US9312416 W US 9312416W WO 9415269 A3 WO9415269 A3 WO 9415269A3
Authority
WO
WIPO (PCT)
Prior art keywords
components
facilitating communication
different byte
orderings
byte orderings
Prior art date
Application number
PCT/US1993/012416
Other languages
French (fr)
Other versions
WO1994015269A2 (en
Inventor
Stephen Yiu-Ming Tam
Original Assignee
Olivetti Advanced Technology C
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olivetti Advanced Technology C filed Critical Olivetti Advanced Technology C
Priority to JP6515373A priority Critical patent/JPH07505972A/en
Priority to EP94905455A priority patent/EP0629303A1/en
Publication of WO1994015269A2 publication Critical patent/WO1994015269A2/en
Publication of WO1994015269A3 publication Critical patent/WO1994015269A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/768—Data position reversal, e.g. bit reversal, byte swapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4013—Coupling between buses with data restructuring with data re-ordering, e.g. Endian conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion

Abstract

A system and method for allowing a component having a first byte ordering to effectively transfer information to another component having a second byte ordering. The present invention envisions embodiments where facilitation of the information transmission is set depending upon whether the two components have the same byte ordering or whether they have different byte orderings.
PCT/US1993/012416 1992-12-21 1993-12-17 Apparatus, system and method for facilitating communication between components having different byte orderings WO1994015269A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP6515373A JPH07505972A (en) 1992-12-21 1993-12-17 Apparatus, system and method for facilitating communication between elements with different byte orders
EP94905455A EP0629303A1 (en) 1992-12-21 1993-12-17 Apparatus, system and method for facilitating communication between components having different byte orderings

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US99440592A 1992-12-21 1992-12-21
US07/994,405 1992-12-21

Publications (2)

Publication Number Publication Date
WO1994015269A2 WO1994015269A2 (en) 1994-07-07
WO1994015269A3 true WO1994015269A3 (en) 1994-11-24

Family

ID=25540637

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1993/012416 WO1994015269A2 (en) 1992-12-21 1993-12-17 Apparatus, system and method for facilitating communication between components having different byte orderings

Country Status (3)

Country Link
EP (1) EP0629303A1 (en)
JP (1) JPH07505972A (en)
WO (1) WO1994015269A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627975A (en) * 1994-08-02 1997-05-06 Motorola, Inc. Interbus buffer for use between a pseudo little endian bus and a true little endian bus
US5928349A (en) 1995-02-24 1999-07-27 International Business Machines Corporation Mixed-endian computing environment for a conventional bi-endian computer system
US5687337A (en) * 1995-02-24 1997-11-11 International Business Machines Corporation Mixed-endian computer system
US5778406A (en) * 1995-06-30 1998-07-07 Thomson Consumer Electronics, Inc. Apparatus for delivering CPU independent data for little and big endian machines
US5819117A (en) * 1995-10-10 1998-10-06 Microunity Systems Engineering, Inc. Method and system for facilitating byte ordering interfacing of a computer system
WO1997044739A1 (en) * 1996-05-23 1997-11-27 Advanced Micro Devices, Inc. Apparatus for converting data between different endian formats and system and method employing same
US6351750B1 (en) * 1998-10-16 2002-02-26 Softbook Press, Inc. Dynamic conversion of byte ordering for use on different processor platforms
FR2795573B1 (en) * 1999-06-25 2001-11-30 Inst Nat Rech Inf Automat DEVICE FOR MANAGING THE EXCHANGE OF DATA BETWEEN COMPUTER EQUIPMENT
EP2177987A1 (en) * 2008-10-17 2010-04-21 Alcatel Lucent A method for handling different types of data, corresponding device, storage means, and software program therefore
US10025555B2 (en) 2016-08-31 2018-07-17 Mettler-Toledo, LLC Byte order detection for control system data exchange

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0282969A2 (en) * 1987-03-18 1988-09-21 Hitachi, Ltd. Computer system having byte sequence conversion mechanism
EP0470570A2 (en) * 1990-08-09 1992-02-12 Silicon Graphics, Inc. Method and apparatus for byte order switching in a computer
US5107415A (en) * 1988-10-24 1992-04-21 Mitsubishi Denki Kabushiki Kaisha Microprocessor which automatically rearranges the data order of the transferred data based on predetermined order

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0282969A2 (en) * 1987-03-18 1988-09-21 Hitachi, Ltd. Computer system having byte sequence conversion mechanism
US5107415A (en) * 1988-10-24 1992-04-21 Mitsubishi Denki Kabushiki Kaisha Microprocessor which automatically rearranges the data order of the transferred data based on predetermined order
EP0470570A2 (en) * 1990-08-09 1992-02-12 Silicon Graphics, Inc. Method and apparatus for byte order switching in a computer

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
H. KIRRMANN: "Data Format and Bus Compatibility in Multiprocessors", IEEE MICRO, vol. 3, no. 4, August 1983 (1983-08-01), NEW YORK US, pages 32 - 47 *
P. KNEBEL ET AL.: "HP's PA7100LC: a low-cost superscalar PA-RISC processor", 38TH ANNUAL IEEE COMPUTER SOCIETY INTERNATIONAL COMPUTER CONFERENCE - COMPCON SPRING '93, 22-26 FEB 1993 SAN FRANCISCO, CA, USA, 1993, IEEE, PISCATAWAY, USA., pages 441 - 447 *

Also Published As

Publication number Publication date
JPH07505972A (en) 1995-06-29
EP0629303A1 (en) 1994-12-21
WO1994015269A2 (en) 1994-07-07

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