JPH07505972A - Apparatus, system and method for facilitating communication between elements with different byte orders - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Apparatus, system and method for facilitating communication between elements having different byte orders Ming background 10 Fields of invention The present invention provides a computer with a first byte ordering. data-related elements have a second byte order and computer-related elements. TECHNICAL FIELD The present invention relates to systems and methods that enable communication. There are two embodiments of the present invention. Determine whether the elements of have the same byte order and whether the two elements are mutually exclusive. It also contemplates systems and methods for creating conditions that enable communication between Ru. Furthermore, embodiments of the invention enable the two elements to communicate with each other. It takes into account that the conditions that apply can be managed dynamically.

■ Related technology Over the past few decades, various types of computer architectures have evolved. Ta. Many computer manufacturers each have their own schemes and protocols. evolving and often between devices using different schemes and protocols. It has hindered communication. As a result, in recent years within the computer industry, Much effort has been expended trying to enable previously incompatible devices to communicate with each other. It's coming.

One such protocol difference that has arisen among computer manufacturers is There is a "byte order" within a computer system. Byte order is lowest The bytes are run from position to most significant (typically within a “word” or part thereof). The bit order (this refers to the order in which the bits are ranked) ).

Elements such as processor interface, memory device, I10 interface, etc. typically has to be preconfigured to take advantage of a particular byte order. is necessary. Thus, these elements can be used within traditional computer systems. Communication can be performed efficiently. operating system and applications Software elements, such as application programs, typically It takes advantage of the byte ordering of the hardware that is ). The byte order is determined by the processor's own register. It's not a star issue. This means that bytes within a register are typically selectively accessed. (Thus, the least significant byte consists of the lowest order bits.) This is because

Most computer architectures rely on byte-ordered schemes. One of two different types is used. In the first type, the least significant byte consists of the 8 least significant bits of a word. Similarly, the least significant byte is the 8 most significant bytes. Consists of. The status of each byte (s1gn1f1cance) is therefore , proportional to the status of the bits it contains.

This first type of byte ordering is known in the industry as "little endian" (l Ittle endian) is known as the J byte order. This term is D anny Cohen, +On Holy Wars And A PleaF or Peace+ (IEEE Computer, 0ctover, 19 81). Little endian byte order The introduction is from Digital Equipment in Maynard, Massachusetts. VAX-type computers manufactured by the Sunta Clara, Calif. It is used in computers using processors manufactured by Intel Corporation.

In the second type of byte order, the least significant byte is the 8 most significant bits of a word. Consists of. Therefore, the status of each byte is therefore contrary to the status of the bits it contains. It's proportional. This type of byte ordering is commonly used in this industry as a Known as the big endian order, located in New York - Monk's 370 mainframe computer manufactured by 18M Company, 68000 processor manufactured by Motorola of Schaumburg, Neue. It is adopted by the computer used. Be careful of big endian type In both types of byte order, little-endian and little-endian, the bit status (ie, focus order) is a point that is not affected by byte order.

The type of byte order used by elements within a particular computer system is, among other things, These elements if less than one word is transmitted at any given time. affects the manner in which information is transmitted between This information (usually some type of The specific aspects of the transmission (over the bus) are determined by practice and are obvious Don't follow patterns. For this reason, big-endian computers data system (i.e., elements with big-endian byte ordering) computer system used) and little endian computer system. Examples of information communication with the system are described below with reference to FIGS. 1-3.

Referring first to Figure 1, the diagram shows two different computer systems ( each having a processor and registers 102). The effect of one byte of information sent from register 102 in a processor (not shown) This shows the results. For more information, see Little Endian Computer Systems A big-endian type controller is also connected via a 32-bit bus 104. Information is transmitted within a computer system over a 32-bit bus 106. There is. Since only one byte is being sent, the information is Located within a bit. Therefore, the register 102 is the same as the example using the bus 104. Using a processor with little endian byte ordering and bus 106 Example internals with a processor that has big endian byte ordering Assume that

In Figure 1, buses 104.106 are labeled "Byte 0" through "Byte 3". It is being This represents the status of each byte sent over the bus (byte 0 is the least significant byte). Here, 1 byte of information from register 102 (information information (A)) is transmitted via each bus in byte 1, is shown (for each computer system) as being sent to a location representing ing. Buses 104.106 therefore represent the byte bytes received by the element. Reflects the order of prints. As a result, byte information is transmitted on bus 104.106. Use of big endian or little endian byte order It can be used to accurately illustrate the differences between

Little endian byte order indicated by bus 104 and bus 106 The most obvious difference between the big-endian byte ordering indicated by In little endian byte ordering, byte O consists of the 8 least significant bits. whereas in big endian byte ordering, byte 0 is the 8 most significant bits. It is a point consisting of cuts. Therefore, as mentioned above, little endian type In big end order, byte order is directly proportional to bit order, whereas in big end order, byte order is directly proportional to bit order. In untyped byte ordering, byte order and bit order are inversely proportional.

Thus, the example of little endian byte ordering indicated by bus 104 , the byte of information (A) appears at position byte 1 along bus 104 .

Here, byte 1 consists of bits 8-15. indicated by bus 106. In the big-endian byte ordering example, the information (A) bytes are Appears at position byte 1 along bus 106. However, this time, byte 1 is It consists of parts 16 to 23. As a result, little endian byte ordering The big endian byte order is swapped (free) in this example. (up) to appear.

Next, using FIG. 2, half a word (2 bytes) of information from register 102 is transferred to the bus The effect when transmitted via 104.106 will be explained. In Figure 2, register 102 via buses 104.106 at their respective computer systems. Byte 0 and byte 1 of the element (not shown) contain half a word of information to be sent. It is rare. A little endian computer system represented by bus 104 In the stem, the first byte in the register (information (A)) appears in byte 0, The second byte in the star (information (B)) appears in byte 1. Therefore, information (A) is transmitted via the 8 least significant bits, and information (B) is transmitted via the 8 next least significant bits (bits). 8 to 15).

In contrast, big-endian computer systems (bus 10 6), the information (A) appears in byte 1 (bits 23-16) and the information Information (B) appears in byte 0 (consisting of the 8 most significant bits). via bus 106 The information sent via the bus 104 is not flipped compared to the case when It should be noted that the Byte O of the big byte order contains information (A), whereas the big In a Dian computer system, byte 1 rather than byte 0 contains information ( A).

Figure 3 shows one word (4 bytes in this example) sent over bus 104.106. ) shows the effect of information. Referring to FIG. 3, the order of information in register 102 is The sequence of information over bus 104 represents a little endian byte order. It can be seen that the order is the same. Therefore, information (A) is also stored in the register 102. Both also include the 8 least significant bits through the 8 least significant bits.

With big endian byte ordering over bus 106, one word of information The information is the same as for little endian byte ordering over bus 104. Sent in a sequence of bits. Therefore, one word is transmitted via bus 106. For example, if the information (A) is sent via the network. However, the order of each byte is byte 0, node 1, etc. Note that the order of thinking does not change.

Order of little endian and big endian protocols Further explanation of the introduction can be found in “On Holy Wars And A” above. "Plea For Peace". Also, in the above example, 32 bits Although the various concepts described are The same applies to size architectures.

Traditionally, where all elements (processor, memory, etc.) use the same byte order When operating in a type computational environment, byte order is typically is of no interest to the average user or programmer. this The byte size information is typically the same once written to a particular address. This is because they can be accessed at the same address. This is a basic principle , without which a computer would hardly be able to function.

Incompatibility issues that arise between two byte ordering schemes (this is explained below) Because of the byte order on a particular computer, the user limits the decisions you can make when deciding whether to purchase software.

More specifically, the operating system typically uses one or the other byte order. For example, Microsoft NT is designed for use in little endian computer systems. On the other hand, most Unix operating systems -Designed for use on endian computer systems.

Consequently, the type of operating system the user intends to use will determine the type of computer system users can purchase . Another way to look at it is if the user has already purchased a computer that consists of Your options for purchasing a marketing system are limited.

Therefore, either big endian type or little endian type 7 (i.e. The operating system (and any software running on it) A need arose for computer systems that could run It has come. If so, the user may purchase such a computer system. Yes, and you can use software with either byte order. Therefore, the controller A computer system can operate using either byte ordering scheme. The user can use big-endian or little-endian It can be used with either operating system.

Use either big-endian or little-endian ordering. The key to designing a computer system that can run software even when The step is for either big-endian or little-endian models. The goal is to design a processor that can operate at high speeds. Sunive, California MIPS Computer Systems, Inc. is a pie-endian (i.e. It can operate in either big endian or little endian mode. A microprocessor (R-4000) was designed. As a result, Bi-So operations using either game-endian or little-endian byte order. Operating systems can also be run using this microprocessor. Wear.

However, it is not enough to simply create a processor that is pie-endian. stomach. This means that traditional computer elements can be either big endian or little endian. ・This is because the endian type is designed to use either byte order. be. In other words, elements such as memory devices are arranged in big-endian sort order. in either the ordinal scheme or the little-endian byte ordering scheme. The structure is such that it is possible to specify addresses appropriately.

Build a computer system in which all elements are pie-endian. It may be possible to It is more cost-effective to create a computer system using right. In order to create such a computer system, the computer system must be The designer of the stem is either big endian or little endian. element (i.e., whether it is of big-endian or little-endian type) elements with a certain byte order). Payen A Dian-type processor is configured to operate in the first byte ordering mode. and the elements with which the processors exchange information have a second byte order mode. A problem arises when An example of the problem encountered in this situation is shown in Figure 4. It may be best explained with reference to an example.

Referring to FIG. 4, a pie-endian processor 402 is a big-endian processor. It is shown operating in an illustrative mode. Therefore, Paiendia In the bus interface 408 of the processor 402, byte O is the 8 lowest Contains the digit bit. In this particular example, one byte of information (A) is ・It is transmitted via 4.

The bus 404 also has little endian elements attached to it. This cornerstone The element may be, for example, a memory device.

The pie-endian processor 402 sends information (A) on the bus 404 in byte 0. , the signal is also sent to the receiving element 406 with byte O. Reception required If the element 406 has a big endian byte order, then this process The expected result is that the portion of element 406 that receives information (A) is enabled. It is to be bullied. However, in this example, byte O of element 406 is enabled. is enabled (can receive information), but the information (A) is byte 3 (enabled). (not received).

For more details, please refer to the standard design in the industry (industrial design) rddesigns), a byte moves on the bus to a specific byte location (e.g. , byte 0), the corresponding byte position of the receiving element is Enabled. Because of this and industry standard designs, information (A) is All (which will not be received) any part of the true-endian element 406 .

The same type of problem as above is a problem where the half word is a little endian element 4. This also occurs when the message is sent on 06. However, if an entire word is sent, , as can be expected by also referring to Figure 3, the little endian type All four bytes of element 406 are enabled, so all information is received. It will be done. In particular, the bus interface in byte 0 of pie-endian processor 402 The information in face 408 is stored in byte 3 of little endian element 406. Therefore, byte 1 of the bus interface 408 is received as a little endie. It is written to byte 2 of element 406 of type Un, and so on. The entire word is then lit When read from element 406 of type endian, it is the pie-endian processor 402 bus interface in the same order as when 402.

Has a big-endian or little-endian byte ordering scheme? As can be understood from the complex nature of to communicate efficiently for a large number of possible byte-sending situations with Indian-type elements. It is not easy to create solutions that make it possible. 1 for this problem The answer is European Patent Application No. 470 by MIPS Computer Systems, Inc. It is disclosed in No. 57082. In this application, the target element (i.e. information the byte address of the element (that receives the information) is translated such that the information can be received. It will be done. Using the example shown in Figure 4 in more detail, information (A) is data starting from byte 0. Receiving little-endian elements when transmitted over bus 404 The side byte address is translated from byte O to byte 3. As a result, Little Byte 3 (rather than byte O) of endian element 406 is enabled. , byte 3 is bus interface 4 of pie-endian processor 402 Information (A) is received from byte O of 08.

The problem with the MIPS approach is that it cannot be integrated into existing computer systems. The problem is that it is difficult to install it inside the building. In particular, all target elements address controller must be redesigned. by this , it may be necessary to further modify the internal mechanisms of existing computer systems. Ru.

Another problem that is not adequately addressed by the MIPS approach is that the information sent from an element with byte order to some external medium, and then from that medium For the situation where it is sent to another element with a second byte order. this problem will be explained below with reference to FIGS. 5 and 6.

Referring first to FIG. 5, this diagram shows that the bytes of information in a word in a memory device are , after that information is received from the big endian processor. This is an example of what the situation is like. More specifically, Figure 5 shows the big One of the endian memory 506 and the little endian memory 512 This information is received from the big endian processor 502. shows the byte order after the The byte order of the information is determined by the byte [status ( sign i f i cancel) J is reversed (already with respect to Figure 3 Despite being the same for both memory devices (as explained) You should be careful. Further, the little endian type memory 512 has one word. A big-endian process simply because the entire information is sent It should be noted that information can be received from the processor 502.

Referring now to FIG. 6, the byte order shown on media 602 indicates that media 602 is 5 big endian type processor 502 (not shown, I10 device). From the medium 602? Byte O of big endian memory 506 (this is here , representing a byte address and containing information (D)) is stored on the medium 602 at location 0. and then the increased status byte is then written to the next location on the medium 602. will be written to. This is the traditional manner in which information is written on such media. represents.

Information on medium 602 is read back into big endian memory 506 , then location O of medium 602 is a byte of big endian memory 506. By O, position 1 is received by byte 1, and so on. Therefore, medium 6 Reading information from 02 onto big endian memory results in the following: produces information having the order indicated by big endian memory 506; Ru.

If the information on medium 602 is - If sent to an endian memory, it is still at position 0 of the medium 602. is read into byte O of little endian memory 604, and position 1 is read into byte 1. Served. If the entire word is read from the medium 602, the information is • The order is as indicated by the endian memory 604. However, The order of the bits is as shown by little endian memory 512 in FIG. It should be noted that the opposite is true. As a result, the little endian type The byte information in memory 604 is in the opposite order as it should be.

The above problem is caused by MIPS because the information is not lined up properly across the bus. cannot be resolved by manipulating the addressing scheme of the answer. In other words, the information , via bus 608 as shown, big endian processor 606 Even if you manipulate the byte address enable method, This situation cannot be changed.

One solution to the above problem is to store the information in little endian memory 604. All bytes are accessed by big endian processor 606. (i.e., in this example, the information (D) is 3, information (A) to byte O, etc.). but , this method is time consuming when there is a large amount of information (a large number of words). system is not very effective.

Some form of media is used to store information in little endian memory 604 and big endian memory 604. A mixed-type computer as illustrated by an endian-type processor 606. The problems shown in Figures 5 and 6 are important because I want to emphasize that it is large. Also, the above example only deals with the processor/memory relationship. (This also applies to the relationship between two elements in a computer system.) I also want to emphasize.

Summary of the invention The present invention allows transfer of one byte, one half word, one word (or depending on the bus width). is an integer multiple of systems and methods that enable elements to communicate information with each other in an efficient manner. Overcoming the shortcomings of conventional devices by providing The present invention includes 2. , element within a communication link (e.g., a bus) between elements if they have different byte orders. This can be done by providing an example of a crossover byte line of information. These results are achieved in an excellent manner. According to one embodiment, the two elements are in the same bar. If an indication is received that the byte line has a stop the server.

Embodiments of the invention are envisioned for use in existing systems; have a different byte order than other elements in the computer system One or more elements are inserted into an existing system. The invention then provides different Allows communication between these elements with byte order.

According to embodiments of the present invention, big endian or little endian Which byte ordering operating system (and other A pie-endian processor that can also be used with computer programs). a computer system (or within a computer system) that has use) is envisaged. In such a situation, the present invention is a pie-endian A computer program running on a processor and its computer program is designed to communicate between elements that have a different byte order than the gram. In cases where the byte lines cross over and the elements are do not intersect if they have the same byte order.

According to yet another embodiment, the present invention may If set during operation, reconfiguration (i.e. crossover or (mode change from to non-crossover and vice versa) is not performed. Also , according to another embodiment, the bytes of the computer program currently running. The present invention can be dynamically reconfigured depending on the order of execution. In this latter embodiment According to can call another computer program with an order Ru. As a result, it is necessary to change the mode of the pie-endian processor, At the same time, resetting whether the byte lines are crossed over or not will also be required.

Brief description of the drawing Various objects, features, and achieved effects of the present invention can be seen in the following description of the invention along with the accompanying drawings. It will be better understood by referring to the detailed description.

Figure 1 shows elements and bits with little endian byte ordering from registers. Transfer of one byte of information to and from an element with double-endian byte ordering FIG.

Figure 2 shows elements and bits with little endian byte ordering from registers. Transfer half-word of information to and from an element with double-endian byte ordering FIG.

Figure 3 shows elements and bits with little endian byte ordering from registers. Transfer one word of information to an element with double-endian byte ordering FIG.

Figure 4 is a block diagram showing the transfer of information between two elements with different byte orders. It is a diagram.

Figure 5 shows a big endian memo from a big endian processor. A block indicating the sequence of information written to the memory and little endian memory. It is a lock diagram.

FIG. A block indicating the sequence of bytes sent to the big-endian processor. This is a diagram.

Figure 7A shows a conventional computer system using big endian elements. and traditional computer systems using little endian elements. FIG.

Figure 7B shows a little endian processor and a big endian element. A computer system according to an embodiment of the present invention having According to an embodiment of the invention having a small endian type processor and a little endian type element. FIG. 2 is a block diagram of a computer system.

FIG. 8 shows a processor with a pie endian type processor and a big endian type element. A computer system according to an embodiment of the present invention and a pi-endian type program A computer according to an embodiment of the invention having a processor and a little endian type element. FIG. 2 is a block diagram of a computer system.

FIG. 9 is a diagram illustrating an embodiment of the invention in active mode.

FIG. 10A is a diagram of a switch in an inactive mode according to an embodiment of the invention.

FIG. 10B is a switch in active mode according to an embodiment of the invention.

FIG. 11 is a circuit diagram of a switch according to an embodiment of the invention.

FIG. 12A is a diagram illustrating the use of a switch in an inactive mode according to an embodiment of the invention. It is.

FIG. 12B is a diagram illustrating the use of a switch in active mode according to an embodiment of the invention. be.

FIG. 13 is a flowchart of a method according to an embodiment of the present invention for swapping information. Ru.

Figure 14 shows the transition from an element with a first byte order to an element with a second byte order. , is an example of the operation of the present invention to transfer one byte of information.

Figure 15 shows the flow from an element with a first byte order to an element with a second byte order. , is an example of the operation of the present invention to transfer half a word of information.

FIG. 16 transfers information originating from elements originally having the first byte order from the medium to the first byte order. Transfer to element with byte order of 2 and then to element with byte order of 1 This is an example according to an embodiment of the present invention.

FIG. 17 illustrates the use of a computer program with a first byte order and a second byte order. Dynamically switching between using computer programs with byte ordering 1 is a block diagram of an embodiment of the present invention; FIG.

Figure 18 shows how to dynamically change the byte order of a processor to have various byte orders. Flowchart of a method according to an embodiment of the invention adapted to a computer program It is the default.

Detailed Description of the Preferred Embodiment ■Overall image and configuration example The present invention provides a computer-related element having a first byte order that has a second byte order. systems and systems that enable effective communication with computer-related elements having and methods. According to an embodiment of the invention, two elements have the same byte order. determine whether the two elements communicate, and then create a system that allows the two elements to communicate. Systems and methods are provided. Further, according to embodiments of the invention, two elements A dynamic management of these measures is made to enable communications between the parties.

In general, the present invention uses an elegant scheme to overcome the drawbacks of conventional devices. There is. In particular, the present invention provides that a computer-related element having a first byte order To enable communication with computer-related elements that have a byte order of 2. , using an information swap scheme. Byte tubes within two byte ordering schemes The complexities mentioned above regarding the Despite the difficulties, the swap scheme according to the invention achieves the desired result. achieve.

Before explaining the details of the scheme used to perform the actual swap of information, we The following describes various configuration examples and assumed situations according to embodiments of the present invention in which Ru. These embodiments are suitable for use within existing computer systems and also for use within existing computer systems. At the same time, it is considered for use on its own, including the entire computer system. . These embodiments will be described with reference to FIGS. 7A to 70.

Referring first to FIG. 7A, this figure shows one "mask" and two "masks" each. Two conventional computer systems are shown with "slave" elements of There is. In particular, these computer systems each have a A memory and an I10 device (slave). For more details, Computer system 702A has big endian memory and big endian memory. A big endian type processor with endian type I10 (e.g. , Motorola 68000). Similarly, computer system 70 4A is equipped with little endian type memory and little endian type I10. If you have a small-endian processor (for example, the Intel 80486) are doing. On computer system 702A, big endian operating systems and other computers designed to function in the environment. Only the data program works. Similarly, on computer system 704A, An operating system designed to function in a little-endian environment. Only systems and other computer programs are active (.

The conventional computer system of Figure 7A was originally intended to run This allows you to run software with a different byte order than what you are using. the processor uses the same byte order of the operating system. It has to work properly. This means, for example, that big-endian code A little endian operating system on your computer system In order to use It needs to run on the same mode. One way to do this is to simply use a computer Reverse byte order (i.e., operating system There is a way to replace it with a processor that has a different system byte order). But this is it However, this is insufficient due to the problems described above in connection with FIG. this problem The solution will now be described with reference to FIG. 7B.

Referring to FIG. 7B, computer system 702B is a big endia memory 712 and big endian 110714 in the computer of FIG. 7A. It is equipped in the same way as the data system 702A. Also, little endian type The remaining components of computer system 702B include processor 706 and bus 710. A swap device 708 is placed in communication between the device and the device. This swa The information is transferred to the little endian processor 706 by the backup device 708. Between big endian type elements such as big endian type memory 712 communicated effectively. This actually creates a little-endian operating system. system and a computer running on a little endian processor 706. A computer program is stored in big endian memory 712 and big endian memory 712. It becomes possible to communicate with the Dian type 110714.

Swap device 708 “swaps” bytes (continuing) in a manner described below. By switching around (switch around), the above perform the work of However, the byte addresses of the various elements are not modified and the The information is swapped by swapping device 708 as it travels to its destination. Please note that

Similar to computer system 702B, computer system 704B In this case, the big endian processor 716 is connected to the computer system 704. It replaces A's little endian processor. After all, the swap device The existence of 708 allows big-endian operating systems and A computer system running on a big endian processor 716 The memory is little endian type 722 or little endian type ■10. It becomes possible to communicate with 724.

According to an embodiment of the invention, replacing the processor with one having a reverse byte order Some of the interfaces of the processor into the computer system are Needs to be fixed. Therefore, [glue logic J correction is necessary. Such modifications will be apparent to those skilled in the art.

Swap device 708 is installed in the processor as shown in the computer system of FIG. 7B. In addition to being placed in communication with the server and other elements, embodiments of the present invention For example, swap device 708 may be configured to communicate between elements in a manner other than that shown in FIG. 7B. can be placed in the desired position. See, e.g., computer system 702A. Big endian memory is then swapped into swap device 708 and little endian memory. It can be replaced with Indian type memory. As a result, it has the second byte order convert any one or more elements into a computer code with elements in the first byte order; It can be installed in the system, and by using the swap device 708, the can function within a computer system.

According to embodiments of the invention, each processor has a parallel processor in communication with swap device 708. Computer systems having a physical architecture are also possible.

Rather than replacing the processor in a computer system, embodiments of the invention ( and the environment used therein), the above-mentioned MIPS R-4000 and other The use of endian processors is also considered. This R-4000 is a big - Can operate in endian or little endian mode, so big ・Whether endian or little endian operating system system (and any other computer program) can also be run by this processor. Available for use.

Most of the elements (e.g. memory and I10) are big endian or read It is designed for either true-endian or true-endian (but not both) All are either big endian or little endian. A code using a pie-endian processor with elements having a byte order of It is typically most effective to design a computer system. Implementation of the invention Although the example includes cases where this is not the case, such a situation is disclosed in Figure 8. ing.

Referring now to FIG. 8, a pie-endian processor 806 and a big big endian type memory 712, big endian type 110714, and bus 71 A computer system 802 is shown with 0 and 0. Swap device 70 8 is a pie-endian processor 806 or a computer/system 802. Communicate with other elements. Big endian operating system Pie-endian processor 806 (set to big-endian mode) swap device 708 is in inactive mode ( i.e. no byte swapping occurs), but this Do all elements in 802 have big endian byte order? It is et al. However, if a little endian operating system endian processor 806 (in this case, little endian mode) swap device 708 is in active mode. Yes, the information is stored on computers with little endian operating systems. Enabled when passing between big endian type elements of the data system 802. It becomes possible to be used. The same concept applies to computer system 804. applicable, where the element is not a big-endian type element (rather than a little-endian type element). Untype elements are used.

With respect to the elements shown in FIG. 8, according to some embodiments, pie-endian processing The processor 806 is configured according to the byte order of the particular operating system. It is not reset during operation. In another embodiment of the invention, the pie end The virtual processor 806 can be reconfigured under appropriate circumstances, and this ・An endian operating system becomes a little endian software (or vice versa). In that case , swap device 708 similarly changes from active to inactive or vice versa at that time. ) change state. In the example of computer system 804, swap device 70 8, a big endian operating system is a little endian operating system. If you call an untyped software routine, it will change from inactive to active. Rutsu According to embodiments of the invention, memory elements with either byte order are Can be any type of computer memory device, including M or CM OS. stomach. In another embodiment, memory is controlled by a scheme such as direct memory access. It can be controlled. According to an embodiment of the invention, the I10 element provides a (hardware) connection to the I10 device. (disk controller, LAN controller, etc.) interface. Ru.

Also, in other embodiments, swap device 708 is not a separate entity; an integrated part of one or more elements (such as a bus or memory device) of a computer system It is.

■,Constructions considered According to embodiments of the invention, it is possible to configure a swap of information that facilitates the features described above. is envisioned. First, the swap device f envisaged in various embodiments of the present invention 1708 will be conceptually explained with reference to FIG.

Referring to FIG. 9, four lines (A, B, C, D) pass through swap device 708. It is shown that they intersect inside the shiso. Each of these lines is one bar wide. It is. In Figure 9, there are four lines (hereinafter referred to as "byte lines"). However, any number may be used in various embodiments of the present invention.

From Figure 9, the outermost bite lines (A and D) swap positions with each other. I can see how it is. The inner bite lines (B and C) also scan their positions relative to each other. I'm wappling. A similar pattern occurs even if more byte lines are used. A sound occurs. For example, two more byte lines are byte lines A and B. If there is one between C and D, then these two bytes The lines swap positions with each other as they pass through swap device 708 .

The swap device t708 of FIG. 9 is in active mode (the byte lines are swapped). ) is displayed. As mentioned above, this swap device 708 can be placed in an inactive mode. mode in which no byte or byte lines are swapped (swap device 708 is fully It is also possible to set it to a state as if it does not exist. Swap device 70 8 will be described below.

In some embodiments of the invention, swap device 708 includes one or more Use a switch. Each of these switches determines when the swap device is set to active mode. If the two byte lines are crossed over (i.e. swapped) Tsubu) to do. Examples of these switches are shown in FIGS. 10A and 10B.

The labeling of the byte lines in these figures (see Figure 11 and below) Byte line labeling in Figure 9 (same for Figures 12A and 12B) and are related for clarity.

Referring first to FIG. 10A, a switch 1002 is shown, with a byte Tunes A and D are passing through it. Non-crossover signals (e.g., in Figure 10A 0 as shown, which means that swap device 708 is in inactive mode. ) is sent to the crossover human power 1004, the switch 100 2 is inactive and byte lines A, D are not swapped. But the cross If an over signal (for example, 1) is sent to the crossover human power 1004 , switch 1002 is active and byte lines A, D are shown in FIG. 10B. It is swapped like this. Of course, in embodiments of the present invention, FIG. Activation or inactivation of the switch 1002 is expressed using values other than those described here. is free.

A more detailed embodiment of the switch 1002 will be described using the example shown in FIG.

Referring to FIG. 11, switch 1002 includes four switches configured as shown. It has a switch 1104. These switches 1104 are, for example, A transistor is fine. Further, an inverter 1102 is configured as shown in the figure. child In this particular example, crossover human power 1004 may be ), then byte line 1.2 is not swapped. But the cross If the overpower 1004 is no\i (for example, represented by digital 1), / Kuit line 1.2 is swapped.

In the present invention, the switch 1002 may be configured in a manner other than that shown in FIG. Please understand that this is possible.

According to an embodiment of the invention, how switch 1002 in swap device 708 An example of how this may be used will now be described with reference to FIGS. 12A and 12B.

Referring first to Figure 12A, two switches (1002A, 1002B) It is used in the wap device 708. Each switch has two bytes - Since the swap device 708 controls the line, the swap device 708 has four banks (as in the case of FIG. 9). control bit (that is, 32 bits) of information.

As shown in Figure 12A, byte line A consists of the eight least significant bits (i.e. Byte line D contains the 8 most significant bits (i.e., bits 0-7); bits 24-31). These two byte lines are connected to swap device 7. The same switch 1002A in 08 is shared. In other words, crossover human power If the 1004 receives a crossover signal, these two byte Ins are swapped. The remaining two byte lines passing through swap device 708 In (byte line BSC), bits 8 to 15 and bits 16 to 23 are and share the switch 1002B. Bytes on both sides of swap device 708 ・Lines A-D are big endian or little endian, respectively. communicate with some element (not shown) that has a byte order of either . Figure 12 In example A, the non-crossover signal (O in this example) 004 is shown. As a result, the byte line Not wapped. FIG. 12A thus shows that the elements on both sides of swap device 708 are the same. Represents a situation that has a byte order. That is, the bytes of swap device 708 Both elements that the line communicates with are big endian or little endian It will have the byte order of either type.

Conversely, FIG. 12B shows that the elements on both sides of swap device 708 have the same byte order. A situation is shown in which it does not have . This is a crossover human power invocation (in this example 1) is shown by the fact that the crossover human power 1004 is receiving Ru. Therefore, switches 1002A, 1002B are active and as shown. , swap byte lines. Specifically, byte lines A and D are and the byte line BSC is swapped. As a result, it is already in line with Figure 9. The effect described in relation occurs.

A crossover human signal is actually a source element (the element that sends the information) has a different byte order than the target element. You should be careful.

According to an embodiment of the invention, two swap devices, including swap device 708 of FIGS. The combination of switches 1002A and 1002B is located in Suntak, California. [Quick Switch] manufactured by Lara's Quality Semiconductor Company This can be achieved using a product called 74QST3383). However, the original In the present invention, the swap device 708 is realized using a different ASIC technology, for example. It should be understood that it is also possible to These other schemes may or may not use a switch (i.e., a multiplexer may or may not be used). ).

In the present invention, crossover human input signals can occur as a result of various stimuli. is now available, and the swap settings specify when byte lines should be swapped. 708. One example is that the processor has a crossover human power 1004 is to write to some address port that responds. swap equipment Whether fit 708 should be activated is determined by the user or by activation/ interactively by storing inert settings in some non-volatile memory. Set. In this way, swap device 708 is used to Can be set appropriately based on raw byte order state.

In FIGS. 9, 12A1 and 12B, the swap device 708 handles 4-byte information. However, this is just an example; the present invention can be used to swap any number of bytes. It is to be understood that implementations are possible. In addition, in the embodiment of the present invention, the swap If the elements placed so that both sides of the layout communicate always have different byte orders, then , the swap device 708 may be permanently active.

An embodiment of the method of operation according to the invention will now be described with reference to FIG. See Figure 13. In comparison, the first step is to identify the buffer used by the first element in the computer system. The purpose is to determine the order of the This is shown in block 13o2.

Next, a decision regarding the byte order used by the second element (which communicates with the first element) is made. It will be done. This is shown in block 13o4.

Then the byte order used by the first element is the same as the byte order used by the second element. A determination is made as to whether or not. This is indicated by decision block 13o6. Ru. If they are the same, no further action is required and communication between the two elements is straightforward. It can be started immediately. This is block 1 connected to decision block 1306. 310.

However, if the byte order used in the first and second elements is not the same To do so, swap device 708 must be activated. This is block 1308 is shown. Once energized, communication between the first and second elements begins , which is shown in block 131o.

■Illustration of operation An example illustrating the effective operation of embodiments of the present invention will be described with reference to FIG. Figure 14 Referring to the big endian processor 14o2 and little endian processor An example is given showing a computer system having an unshaped memory 1406. Ru. In this example, the information is shared between big endian processor 14o2 and little endian processor 14o2. The data is sent via the 4-byte bus 141o to the endian memory 1406. It will be done. Swap device 708 is active (because the two elements have different byte orders) is shown as a big endian processor 14o2 and a little endian processor. The bus 141o is connected to the Indian memory 1406.

In this particular example, register 14o8 contains one byte of information (Information (A)). . When transmitted on bus 141o via bus interface 14o4 In this case, information (A) is sent in byte 0 as shown. Swap device 7゜8 If there is no intervening information (A), the information (A) is as described in connection with FIG. As mentioned above, little endian memory 1406 (which receives information is received in byte 3 of (not enabled). This is the original is intended to be used in (and in the environments used with) the specific embodiments. standard used with memory management schemes in computer systems that This is the result of the protocol. For this protocol, information is passed to the sending element (this In this case, it is sent at the byte 0 position of the big endian processor 1402). If the receiving element (in this case little endian memory 1406 ) is enabled.

Therefore, in the present invention, active swap device 708 places information (A) in the proper location. Swap as sent. Specifically, information (A) is Byte address (i.e., byte O) in true-endian memory received.

Figure 15 shows a half word (i.e. two bytes) instead of one byte as described in the previous figure. An example is shown in which information on Referring to FIG. 15, information (A ) and information (B) are said to exist inside the register 1408. This information is sent on bus 1410 via bus interface 1404 and the information (A) is sent in byte 0 and information (B) is sent in byte 1. mentioned above Considering the memory management scheme, this information can be stored in little endian memory1 By writing to little endian memory 1406, Bits 0 and 1 are enabled. As shown in FIG. 15, swap device 708 information is stored in the enabled portions of little endian memory 1406. can be received within minutes.

The invention is not limited to the examples of FIGS. 14 and 15. For example, any number of bytes The bus width of the target bus can be taken into account, and the above concepts can be Applicable regardless of which byte location (byte address) of the element is being sent. It is. This example also uses a big-endian type mask element (here: processor) is a little-endian slave element (memory here) Although shown communicating, other combinations, e.g. slave and slave Combinations such as mask and master may also be envisaged.

The present invention also relates to the medium described with reference to FIGS. 5 and 6 in the detailed description of the invention. It also solves the problem of receiving information from. This example will now be described with reference to FIG. Bell.

Referring to FIG. 16, a medium 1602 (this may be a floppy disk, tape, , or even any type of movable medium, such as a LAN), as already shown in FIGS. 4 bytes of information from the big endian type element as explained in relation to Figure 6. It shows how the information is received. Therefore, bytes of big-endian elements Information (D) transmitted from point 0 is shown at position 0 of medium 1602. information In (C), water is sequentially poured into position 1.

Information is stored by little endian memory 1406 on medium 1602 (not shown). (but not via some I10 device), the byte positions are aligned. will be combined. In other words, any information at position 0 on medium 1602 is are placed in byte 0 of Indian memory 1406, and those in position 1 are placed in byte 1. He, etc. This is due to the industry standard protocols mentioned above.

If the information is placed in little endian memory 1406 as described above , the byte order of that information is the little endian memory 6 shown in Figure 6. It will be the same as shown in 04. As explained in connection with Figure 6, the little en The information in the big-endian memory 604 is, as it is, big-endian. Processor 606 is unavailable. For use, this information must be The first format (this was the big-endian processor in Figure 5) 502 and the format indicated by the big endian memory 506). No.

Referring again to FIG. 16, the swap device 708 allows the As envisioned, the big endian processor 1402 is information from Indian memory 1406 can be received and used. Ingredients Specifically, the swap device 708 swaps information such as ) information (D) sent from the endian memory 1406 at the location of byte 0. , byte of big endian processor 1402 as occurred in the example of FIG. Received with byte O instead of 3. Therefore, as a result of swap device 708, The information received by the high endian processor 1402 is is the file originally sent by big endian processor 502 in FIG. It's in the format. In this way, if the information is in memory, it will not be swapped. This saves significant time.

Embodiments of the present invention utilize an I10 element (not shown) to link media 1602. Information transmission to and from true endian memory 1406 is facilitated.

Generally, the I10 element contemplated for use in embodiments of the invention as described above is , the information is in a byte-wide fashion (I10) I am thinking of sending it to the element and from the I10 element. Information is transmitted in parallel manner (i.e., sent using a width of multiple bytes), the information 10 element and must be swapped prior to receiving from the I10 element. Ru.

In an embodiment of the invention, when using the parallel method, data is written to the I10 element. This is done by using a device driver that swaps before (or reading from) it.

The design and construction of such device drivers is known to those skilled in the art. Also, additional The swap device 708 can be used instead to replace the I10 element and the computer system. It is also possible to place it between other elements.

■Specific example of dynamic swap device As discussed above, the computer systems contemplated by the various embodiments of the present invention may be The byte order mode of pie-endian processors can be changed dynamically. The swap device 708 allows the operating system to You can also use software routines that have a different byte order than . An example of that scheme is shown in FIG.

Referring to FIG. 17, the pie-endian processor 1708 uses the first byte order mode (either big endian or little endian). using an operating system (not shown) with a first byte order. Assume that the system is configured to operate as follows. Memories that both have first byte order Computer program 1704 within 1702 is subsequently accessed and Using swap device 708 by endian processor 1708 not needed (i.e. swap device ff1708 is inactive and the byte line is run (not swapped).

Calls to software routines 1706 within computer system 1704 (Software routine 1706 sets the second byte order. (originally generated using a processor with Firstly , pie-endian processor 17o8 sets its byte order mode to the second switch to write order mode and correspond to routine 1706 of this software. . Second, pie-endian processor 17o8 now has memory 17o2 Since we are using a different byte order, swap device 708 becomes active (i.e. (The device is then reset to active mode.) As a result, the bytes in swap device 708 The lines swap bytes of information as described above.

Once the pie-endian processor 1708 and the swap device 708 are Once reconfigured to correspond to the software routine 1706, the software Routine 1706 is then received by pie-endian processor 1708. be believed. When the routine completes execution (or the software routine 1706 itself calls a routine in another software that has the first byte order ), pie-endian processor 17o8 and swap device 7o8 and return to its original mode.

According to an embodiment of the present invention, software is installed in the computer system 1 file 02. pie-endian processor 170 in conjunction with a call to routine 1706; 8 and swap device 708 to different states. determined. However, the invention also includes embodiments in which the state can be set in other ways. .

FIG. 18 shows an embodiment of the method of operation of the present invention. Referring to FIG. 18, the first In step , computer program 1704 selects a first byte order mode. The program is executed in a pie-endian processor 1708 running in a pie-endian mode.

This is shown at block 1802. Computer program 1704 is then configured to run in the second byte order mode. 1706 is called. This is indicated by block 1804. Ru.

The next step is the pie-endian processor 1708 and the swap device 708. and to operate in the second byte order mode. That is, The byte order of pie-endian processor 1708 is switched and swapped. Device 708 is activated. This is shown at block 1806. said Once this is done, as indicated by block 1808, the software The software routine 1706 is loaded and the pie-endian processor 1708 It is executed in

In the embodiment of the present invention illustrated in FIGS. 17 and 18, the software routine Although 1706 has a different byte order, computer program 17 Although it is assumed that memory 1702 and memory 1702 have the same byte order, the present invention In this embodiment, computer program 1704 resides in a different memory than memory 1702. software routine 1706 and memory 1702 have the same byte order. It is also possible to have an order of In that case, the swap device 708 Software 1 is active during execution of computer program 1704; It is inactive during execution of 706.

The present invention requires dynamically changing the active/inactive state of the swap device 708. Or understand that it is also intended for use in pond situations and examples where it may be effective. I want to be understood.

Various elements of embodiments of the invention may include hardware, software, and combinations thereof. It should be emphasized that this is possible. In such embodiments, the species implemented in hardware and/or software. and perform the functions of the present invention. Compilations currently available or that may be developed in the future The language and/or hardware elements of the computer software may be may be used in such embodiments.

The invention is not limited to the embodiments described above, and the examples used are for illustrative purposes only. should be understood. The scope of the invention is, therefore, determined by the foregoing detailed description and drawings. Accordingly, it should be construed in accordance with the scope of the claims as defined herein.

~ One Big endian format (on media) FIG, 7A FIG. 7B Fi(1,9 f:”i(1,l0A f: iQ, IOB Fig, 12A File, 73 Fill, 14 Big endian format (on media) procedural amendment September 1994 and iv

Claims (1)

[Claims] 1. a device that facilitates the transmission of information consisting of bytes within a computer system Leave it behind. having a first byte order and providing information to the computer system; The first element that can be a second element capable of receiving the information from the first element; communicatively disposed between the element and the second element, the byte order of the second element If the order is a second byte order, then the previous byte order is swapping means for swapping the bytes of recorded information. device to do. 2. 2. The apparatus of claim 1, wherein the first element is in a first byte order mode. It is a bi-endian processor originally configured using The bi-endian processor processes a first computer having the first byte order. A device characterized in that it is running a computer program. 3. 3. The apparatus of claim 2, wherein a second compiler having a second byte order by said first computer program running a computer program; When the bi-endian processor receives a request for a second byte order, the swap means is reconfigured using the bi-endian bytes of information when the computer is running said first computer program. stopping swapping of the bytes of information at the location to be swapped, said swapping means comprising: the bi-endian processor runs the first computer program; swapping bytes of information in locations where bytes of information would not be swapped if A device characterized by: 4. 2. The apparatus of claim 1, wherein the swapping means has a 2-byte line. at least one switch means passing therethrough; The at least one switch means is configured to instruct the switch to be activated. Connectively swaps two byte lines when a crossover input signal is received. A device characterized by: 5. 2. The device according to claim 1, wherein said swapping means comprises said first element or is an integral part of said second element. 6. A compiler sent by a source element consisting of bytes and having a byte order. In a device that facilitates the transmission of information within a computer system, a first byte order a target element having: a target element configured to receive said information; swapping means for receiving an indication regarding the byte order of the source element. and the source element is in a different order than the first byte order of the target element. upon receiving an indication that the swapping means has a byte order of the bytes of the information prior to the information being received by the target element; is set to active mode where it is swapped, Upon receiving an indication that the source element has the first byte order, The swapping means is configured to swap the information before the information is received by the target element. means that said bytes of said information are set to an inactive mode in which they are not swapped. Featured device. 7. 7. The apparatus of claim 6, wherein the target element is a memory device. A device characterized by: 8. 7. The apparatus of claim 6, wherein the source element is in a first byte order mode. It is a pie-endian processor originally configured using The bi-endian processor processes a first computer having the first byte order. A device characterized in that it is running a computer program. 9. 9. The apparatus of claim 8, wherein a second compiler having a second byte order by said first computer program running a computer program; When the bi-endian processor receives a request for a second byte order, If the swapping means is set to inactive mode, If so, the swapping means is reset to the active mode, and the swap means is set to the active mode. device, characterized in that it is reset to an inactive mode if the 10. use a computer program that consists of bytes and has a byte order In computer systems, operating in either the first byte order mode or the second byte order mode; a computer program configured to operate using said byte order mode; processor means, has a byte order, stores the computer program and executes the process. an element that allows the computer program to be accessed by the computer program; and, communicatively disposed between said processor means and said element; receiving an indication of the byte order mode of the stage, the byte order of the element is If different from said byte order of the processor means, said computer program swapping means for swapping the bytes of the program. computer system. 11. 11. The device according to claim 10, wherein the swapping means is a 2-byte memory card. at least one switch means through which the switch passes; The at least one switch means is configured to instruct the switch to be activated. Connectively swaps two byte lines when a crossover input signal is received. A device characterized by: 12. 11. The apparatus of claim 10, wherein the element is a memory device. Featured device. 13. Within a computer system, the first A method for facilitating transmission of information between an element and a second element, comprising: (1) said first element; whether the byte order of one element is the same as the byte order of the second element; (2) the byte order of the first element is determined by the second requirement; If it is determined in step (1) that the byte order is not the same as the original byte order, energizing a byte swap device; (3) the byte order of the first element is the same as the byte order of the second element; disabling the byte swapping device if it is determined that the byte swapping device is the same; , A method characterized by having the following. 14. 14. The method of claim 13, wherein the byte order of the first element and receiving information regarding the byte order of the second element. prior to step (1), the method further comprises the step of receiving information. How to make it a sign.