WO1994008398A1

WO1994008398A1 - Line driver circuit

Info

Publication number: WO1994008398A1
Application number: PCT/FI1993/000400
Authority: WO
Inventors: Markku Henriksson; Marcos Katz; Hemmo RISTIMÄKI; Kari Sahlman
Original assignee: Nokia Telecommunications Oy
Priority date: 1992-10-07
Filing date: 1993-10-06
Publication date: 1994-04-14
Also published as: FI924523A0; FI100069B; GB2287145A; HK1006613A1; FI924523A; AU5112593A; DE4394820T1; GB2287145B; GB9507067D0

Abstract

The invention relates to a line driver circuit, comprising a driver stage (11) and a transformer provided with a primary and secondary windings (12a, 12b) in such a way that output terminals of the driver stage (11) are connected to terminals of the primary winding (12a) of the transformer and terminals of the secondary winding (12b) of the transformer are connected to a transmission line (13), at least one matching resistor (Rm) being connected to the terminals of the primary winding of the line driver circuit. To provide a line driver circuit having a good return loss and a low power consumption, it comprises driver means (51 to 53; 71, 72; 81, Q1, Q2) connected to said at least one matching resistor and responsive to an output signal of the driver stage (11) for disconnecting the matching resistor (Rm; Rm1, Rm2) for the time of pulses transmitted by the driver stage.

Description

Line driver circuit

The invention relates to a line driver circuit according to the preamble of the attached claim 1. The line driver circuit according to the invention is intended to provide desired signal and impedance lev¬ els for a digital connection.

When matching the output of a line driver cir¬ cuit into a transmission line connected thereto, the output of the line driver circuit shall meet a plura¬ lity of various requirements. One such requirement is to keep interferences caused by reflections low enough, which means that the output port shall have a sufficient return loss as to prevent a reflected sig- nal, being summed to an outgoing signal, from causing any significant distortion of the outgoing signal.

A drawback of line driver circuits having a reasonable return loss (e.g. of the order 14 dB) is, however, their high power consumption (low efficien- cy). These known circuits are described in greater detail below with reference to figures.

The object of the present invention is to get rid of the above drawback and to provide a line driv¬ er circuit having a relatively good return loss and a low power consumption. This is achieved by means of the line driver circuit according to the invention, which is characterized in what is set forth in the characterizing portion of the attached claim 1.

The inventive idea is to start from a line driver circuit, known per se and provided with a matching resistor of a zero state, and to provide it with driver means responsive to a driver stage, which means disconnect the matching resistor of the zero state from the electric circuit for the time of pulses to be transmitted. In addition, the circuit according to the in¬ vention has a simple structure, and a further advan¬ tage of the solution is that existing driver stages using transistor switches can still be utilized. In the following, the invention will be ex¬ plained in more detail by referring to examples ac¬ cording to the attached drawings, in which

Figure 1 shows a known line driver circuit,

Figure 2 shows an impedance visible from a transmission line as a function of time when the line driver circuit according to Figure 1 is used,

Figure 3 shows another known line driver cir¬ cuit,

Figure 4 shows the impedance visible from the transmission line as a function of time when the line driver circuit according to Figure 3 is used,

Figure 5 shows the principle of a line driver circuit according to the invention,

Figure 6 shows the impedance visible from the transmission line as a function of time when the line driver circuit according to the invention is used,

Figure 7 shows a preferred embodiment of the line driver circuit according to the invention, and

Figure 8 shows another preferred embodiment of the line driver circuit according to the invention.

Figure 1 shows a line driver circuit according to prior art, in which a driver stage 11 applies an output signal via a transformer coupling 12 to a transmission line 13, which is connected to terminals of a secondary winding 12b of the transformer. The object of the driver stage is to provide desired sig¬ nal and impedance levels for the transmission line 13 in question, each output terminal of the driver stage being connected via a separate resistor Rl and R2, respectively, to a respective terminal of a primary winding 12a. The driver stage typically comprises two transistors Trl and Tr2, one of which is conductive during a positive pulse and the other one during a negative pulse (cf. Figure 3). The primary winding 12a of the transformer comprises a tapping connected to the operating voltage.

The driver stage may be e.g. a commercially available XR-T5675 manufactured by Exar, which cir¬ cuit is intended to drive PCM lines up to a 10 Mbit/s rate.

Figure 2 shows an impedance visible from the transmission line 13 as a function of time when a line driver circuit according to Figure 1 is used. A respective output signal P_out (conforming for example to a HDB3 line code known per se) applied by the driver stage 11 is drawn above an impedance curve 21 as a reference. The impedance visible from the trans¬ mission line rises very high (practically infinitely) in those time slots Tl in which the driver stage does not transmit pulses to the transformer output. Be¬ sides, a very high impedance of a "zero state" (time slots Tl ) means a very low return loss in practice.

Figure 3 shows another known line driver cir¬ cuit, which conforms to the connection according to Figure 1, except that a matching resistor Rm has now been added between the terminals of the primary wind¬ ing 12a of the transformer. The transistors Trl and Tr2 of the driver stage 11 are presented in this fig¬ ure as switches SI and S2 (constituted by the tran- sistors) describing the operation of the transistors. The figure shows both switches in an open position, which corresponds to the above-mentioned "zero state" (time slots Tl) .

Figure 4 shows the impedance visible from the transmission line 13 as a function of time when a line driver circuit according to Figure 3 provided with a matching resistor is used. In those time slots Tl in which the driver stage does not transmit pulses to the transformer output (switches SI and S2 off), the impedance seen from the transmission line is de¬ termined mainly in accordance with the matching re¬ sistor Rm (reduced by the transformation ratio of the transformer). On the other hand, during pulses (one of the switches on) the impedance seen from the transmission line is determined mainly in accordance with the resistors Rl and R2 (reduced by the trans¬ formation ratio of the transformer). By a suitable selection of resistor values, a fairly even impedance curve 21 may be provided. However, a drawback of the circuit shown in

Figure 3 is its high power consumption (during pulses), which is due to an extra current path caused by the matching resistor in the driver circuit.

Figure 5 shows a solution according to the in- vention, which corresponds to the solution of Figure 3, except that driver means responsive to the driver stage 11 are now connected to the matching resistor Rm, which means disconnect the matching resistor for the time of the pulses transmitted by the driver cir- cuit. In the example of the figure, the driver means comprise a separate driver circuit 51, each input of which is connected to the respective output terminal of the driver stage 11 and the output of which is connected to a relay 52. The relay drives a switch 53 positioned between one terminal of the matching re¬ sistor Rm and one terminal of the primary winding 12a in such a way that the matching resistor is discon¬ nected from the electric circuit when pulses are transmitted by the driver circuit 11 (switch SI or S2 being turned on). By disconnecting the matching re- sistor from the electric circuit, the power consump¬ tion of the line driver circuit can be kept low also during the pulses. At the same time, the return loss of the circuit can be rendered good, too. Figure 6 shows the impedance visible from the transmission line 13 as a function of time, when the solution of the invention is used. When no pulses are transmitted by the driver stage, the impedance is de¬ termined in the manner described above by means of the matching resistor. When pulses are transmitted by the driver stage, the matching resistor is discon¬ nected from the electric circuit, whereby the impe¬ dance is determined according to the output resistor Rl or R2. The resistors can be selected in such a way that the line impedance remains unchanged all the time, except for small peaks 61 during the connec¬ tion. In Figure 6 are indicated those resistors which determine the impedance of the line driver circuit each time. During pulses the matching is attended to by resistors Rl (positive pulse) and R2 (negative pulse) and between the pulses (time slots Tl ) by the matching resistor Rm.

Figure 7 shows a preferred embodiment of the general solution shown in Figure 5, which embodiment suits better for operational frequencies occurring in practice. The driver circuit is in this case consti¬ tuted by an AND gate 71 and the switch driving the matching resistor is in this case constituted by a FET transistor 72, to a gate of which the output of the AND gate is connected. Further, the driver stage 11 is similar to that shown in Figures 1 and 3. Ac¬ cordingly, an additional advantage of the invention is that the existing known driver stage can be uti¬ lized therein. In the "zero state", the transistors of the driver stage are in a non-conducting state and a voltage (+ 5 V) is present across them. When this voltage is present across each transistor, the output voltage of the AND gate changes into a logic level "one". Then the transistor 72 is driven and it begins to conduct and connects the matching resistor to the electric circuit. When the other transistor of the driver stage is conducting (during pulses), the out¬ put voltage of the AND gate changes into a logic zero level and the transistor 72 disconnects the matching resistor from the electric circuit.

The AND gate described above may be implemented in many ways, e.g. by means of a diode-resistor logic (cf. Figure 8), transistors, operational amplifiers or by means of commercially available logic circuits. The switching part (switch 72) may, in turn, be real¬ ized either by FETs or bipolar transistors.

Figure 8 shows a practical solution, in which the AND gate is implemented in a manner known per se by means of diodes Dl and D2 and a resistor R3. (The terminal common to the anodes of said diodes and one terminal of the resistor R3 constitutes the output of the AND gate, the cathode of each diode is connected to the respective output terminal of the driver stage and the other end of the resistor R3 is connected to the operating voltage). The advantage of such a diode-resistor solution is its speed and simplicity. In this case there are two matching resistors (Rml and Rm2) of the "zero state" as well as switches (Ql and Q2), which drive them. By means of diodes D3 and D4, the level of a control signal to be received from the AND gate is reduced to match the FET switches Ql and Q2. Capacitors Cl and C2 positioned between the terminal of the primary winding and the corresponding matching resistor prevent a passage of direct current through the matching circuit of the "zero state". The advantage of the solution shown in Figure 8 is that it makes it possible to guarantee with a greater cer¬ tainty that the switching transistors Ql and Q2 are driven conductive in the "zero state" (drain and source of the FETs are at different potentials).

Even if the invention has been described above with reference to the examples of the attached draw¬ ings, it is clear that the invention is not restrict¬ ed to that, but it may be modified within the scope of the inventive idea presented above and in the at¬ tached claims. So it is possible for one skilled in the art to modify details of the driver means cir¬ cuit, for instance, without deviating from the scope of the invention anyway. Details of the driver stage may also vary. The essential fact for the invention is only that the driver stage operates like a switch, which means that the driver stage represents an impe¬ dance which is high when the switch (transistor) is non-conducting and an impedance which is low when the switch (transistor) is conducting. The idea of the invention can be applied also without resistors Rl and R2 in principle, but in practice it is not rea¬ sonable, as matching during pulses is then impaired.

Claims

Claims:

1. A line driver circuit, comprising a driver stage (11) and a transformer provided with primary and secondary windings (12a, 12b) in such a way that output terminals of the driver stage (11) are con¬ nected to terminals of the primary winding (12a) of the transformer and terminals of the secondary wind¬ ing (12b) of the transformer are connected to a transmission line (13), at least one matching resis¬ tor (Rm) being connnected to the terminals of the primary winding of the line driver circuit, c h a r¬ a c t e r i z e d in that it comprises driver means (51 to 53; 71, 72; 81, Ql, Q2) connected to said at least one matching resistor and responsive to an out¬ put signal of the driver stage (11) for disconnecting the matching resistor (Rm; Rml, Rm2) for the time of pulses transmitted by the driver stage.

2. A line driver circuit according to claim 1, c h a r a c t e r i z e d in that the driver means comprise an AND gate (71; 81), each input of which is connected to respective output terminal of the driver stage.

3. A line driver circuit according to claim 2, c h a r a c t e r i z e d in that the AND gate is implemented by means of a diode-resistor logic (Dl, D2, R3).

4. A line driver circuit according to claim 2, c h a r a c t e r i z e d in that the driver means comprise a transistor switch (72; Ql, Q2) connected to one terminal of the matching resistor and driven by the AND gate (71; 81).

5. A line driver circuit according to claim 4, c h a r a c t e r i z e d in that it comprises two matching resistors (Rml, Rm2), each of them connect- ing the respective terminal of the primary winding (12a) to earth via said transistor switch (Ql or Q2, respectively).