WO1994008330A1 - Liquid-crystal display device - Google Patents
Liquid-crystal display device Download PDFInfo
- Publication number
- WO1994008330A1 WO1994008330A1 PCT/JP1993/001403 JP9301403W WO9408330A1 WO 1994008330 A1 WO1994008330 A1 WO 1994008330A1 JP 9301403 W JP9301403 W JP 9301403W WO 9408330 A1 WO9408330 A1 WO 9408330A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- line
- voltage
- display device
- column
- value
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3622—Control of matrices with row and column drivers using a passive matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
Definitions
- TECHNICAL FIELD This invention relates to a reduction of vertical "cross-talk" in dot-matrix liquid-crystal display devices, and achievement of grey levels with the aid of pulse-height modulation.
- the present invention relates to a display device, comprising a liquid-crystal material between two support plates held at a defined spacing from one another and having surfaces facing one another, a pattern of N line electrodes being provided on one surface and a pattern of column electrodes on the other surface, which line electrodes cross the column electrodes and the crossover points therefore form a matrix of display elements.
- the device comprises, inter alia, a control circuit for presenting data signals to the column electrodes and a line-scanning circuit for periodically scanning the line electrodes and presenting suitable line selection voltages.
- Such display devices are known and are normally operated with multiplex addressing in accordance with the so-called RMS mode.
- the picture elements are switched from a first state to a second state which is optically different therefrom with the aid of the line-scanning circuit which periodically scans the line electrodes with a line-selection pulse of magnitude V s and with the aid of the control circuit for presenting data signals to the column electrodes, which control circuit feeds data voltages of magnitude +/- V d to the column electrodes for the time in which a line electrode is scanned, in such a way that the optical state which is achieved in a display element is determined by the so- called root-mean-square (RMS) voltage value across the element concerned.
- the RMS voltage value V 2 for the selected display elements, i.e., the display elements in the on state is given by:
- V 2 2 (V. + V d ) 2 /N + (N - 1) * V d 2 /N (1)
- Figure 2 diagrammatically shows a transmission-voltage characteristic of a picture cell belonging to this display device.
- Figure 1 diagrammatically shows a portion of a matrix-oriented display device 1 having N ⁇ ,. selection lines (row electrodes) 2 and describes the operating principle of the abovementioned RMS multiplex address method.
- This address method is generally referred to as "line-at-a-time" RMS multiplex addressing.
- the information to be displayed is presented on the data lines (column electrodes) 3.
- the picture information (data voltage +/- V d ) is supplied synchronously with the selection of the lines or row electrodes with the aid of the line-selection voltage V s .
- the line 2 is selected for a period tj (also referred to as line time), which line, together with the information then present on the data lines 3 a , 3 b , 3 C (i.e. +/- V d ) determines the optical state of the picture elements 4 aa ,
- the display element responds to the cumulative effect of a number of address pulses (or selection pulses).
- a liquid-crystal display element responds in the same way as if it has been addressed by a sinusoidal or square-wave signal having the same RMS voltage value as that of the 'on' and 'off voltages V 2 and Vi given by the expressions (1) and (2).
- the maximum number of selection lines N ⁇ .. is related to the value of the ratio V 2 /V (threshold steepness).
- FRAME RESPONSE This multi-line addressing is used to reduce or to eliminate the so-called "FRAME RESPONSE” behavior.
- "FRAME RESPONSE” behavior results in loss of contrast and brightness.
- N ⁇ is in turn determined in accordance with expression (3) derived for RMS behavior occurring.
- the actual RMS voltage value for an "on" element (or selected display element) in a column in which all the picture elements are in the "on” state may differ from the RMS voltage value for a selected display element in a column in which the picture elements are, for example, alternately "on” and "off".
- crosstalk or “ghost” phenomena
- This method makes use of a special polarity change sequence in which the polarities of the address-voltage signals always change in sign after scanning 2 lines during the raster scan. The start position of these polarity changes is also changed or shifted for successive frames.
- the object of the invention which will be described in this patent application is to provide a display device in which the abovementioned crosstalk effect is reduced as much as possible without making use of special polarity-change sequences .
- said display device has, according to the invention, the characteristic that a column control circuit is used with which data voltages having mutually different amplitude can be presented to the separate column electrodes.
- the different data signals are chosen in accordance with the number of "on"-"off" transitions in the columns concerned.
- the control circuit should comprise a "counter unit” which registers the number of "on"-"off" transitions in each column of the matrix of the display device.
- Figure 1 shows a portion of a matrix-oriented display device
- Figure 2 shows a transmission characteristic of so-called negative-contrast display device
- Figure 3 shows a relationship between the voltage V LC across an LC element and time elapsed
- Figures 4A and 4B show waveforms of voltages across an element A and B, respectively.
- FIG. 3 diagrammatically shows the way in which the voltage V lc across an LC element (represented as a capacitor C) increases with time on presenting a voltage jump of V in in the presence of a resistor R.
- the RMS voltage value follows from:
- V RMS 2 (V ln 2 /T)/? (1 - exp(-t/ ⁇ )) 2 dt (7)
- V RMS 2 1 - ⁇ /2T * (exp(-2T/ ⁇ ) - 1) + 2 ⁇ /T
- the effective (RMS) voltage is determined by the number of square-wave voltages and therefore, in reality, by the number of passages through zero.
- Figure 4B diagrammatically shows the voltage across element B with the assumption that only one "on"-"off" transition occurs in column j .
- the height of the data-voltage levels for compensating for V ⁇ *- losses can, however, also be determined experimentally by means of transmission (or brightness) measurement of an "on" element as a function of the number of "on"-"off" transitions.
- a procedure to be followed may be as follows:
- Compensation for V ⁇ s losses as a consequence of "on"-"off" transitions can also be achieved by using the same V d value during the scanning of the N-line matrix for columns having different X au values and by presenting a voltage pulse whose amplitude V j (X au ) is dependent on the X au value in the column concerned simultaneously to the separate columns j after every frame scan for a certain time interval t x (for example, equal to the line time tj).
- t x for example, equal to the line time tj.
- the height of the voltage pulse to be supplied V j (X au ) can be determined relatively simply experimentally with the aid of transmission measurements according to a procedure such as is described for the determination of the different column voltages V d (X au ) which are used in the first- mentioned compensation method.
- the polarities of both the data signals and of the line-select signals should change in sign, for example after every raster time; this is done in order to prevent the occurrence of direct-voltage components. In practice, this polarity change is often used after a certain number of line times, the number being less than N.
- FM frame modulation
- PWM pulse-width modulation
- a disadvantage of FM is the occurrence of "flicker" in fast-switching liquid-crystal display devices.
- PWM is described, inter alia, in SID Digest of Technical Papers XI, pages 28-29, 1980.
- PWM has, inter alia, the disadvantage that high- frequency signals are necessary for a large number of grey levels .
- a third method of achieving grey levels makes use of pulse-height modulation (PHM) and is essentially used in display devices in which each picture element is provided with an active electronic switch such as, for example, a thin-film transistor.
- PPM pulse-height modulation
- a grey level is in fact achieved for a picture element by supplying the element concerned with a voltage having a certain amplitude.
- This method cannot, however, readily be used in the matrix display devices which are described in this patent application and which are addressed by the line-at-a-time or multi-line RMS addressing.
- V on 2 (V s + V d ) 2 /N + (N - 2)*V d 2 /N + (f*V d ) 2 /N
- the loss in RMS voltage can be compensated for by supplying a voltage pulse to the column concerned after each frame scan (for, for example, a line time tj).
- a voltage pulse for, for example, a line time tj.
- the height of this voltage pulse is dependent on the number of elements in the column concerned having a particular grey level, expressed, for example, in the value of the factor f, in which case completely "on” and completely “off” may also be regarded as grey levels.
- the height of the voltage pulse can in principle be determined (or calculated) by deriving expressions under these circumstances for, for example, the RMS voltage of an "on” and an “off” element and equating the RMS voltage values calculated in this way to those according to expressions (1) and (2).
- the following example serves to illustrate the procedure which can be followed in this case. In this example, it is assumed that the compensation pulse V c is supplied for a line time t x .
- EXAMPLE 4-line matrix, in which one "on” element and three picture elements having different grey levels (or f values) occur in a particular column.
- V on 2 (S 4 + D ⁇ ) 2 /4 + 3*D, 2 /4 (12)
- V off 2 (S 4 - D 4 ) 2 /4 + 3*D 4 2 /4 , (13)
- S 4 D A * SQRT(4)
- S 4 line-select voltage
- D 4 data voltage
- a 5th line is, as it were, added to the 4-line matrix. This line does not actually need to be present: it is a virtual line.
- V on 2 (S 5 + D 5 ) 2 /5 + (f 1 *D 5 ) 2 /5 + (f 2 *D 5 ) 2 /5 + (f 3 *D 5 ) 2 /5
- V c 2 /5 (14) where: f ⁇ *D 5 is the amplitude of the data voltage which is supplied to the element i concerned having a grey value with parameter value f L .
- the contribution V c 2 /5 arises because, during selection of the 5th (virtual) line, a certain voltage is presented to the column.
- S 5 S 4 * SQRT(5/4)
- D 5 D 4 * SQRT(5/4)
- V c is chosen in accordance with expression (19)
- the resulting V on 2 will be identical to that according to expression (12). If we had considered an "off” element instead of an "on” element, the result would have been identical.
- the procurRMS voltage V fl of this element is given by:
- V f i 2 (S 5 + f ! *D 5 ) 2 /5 + D 5 2 /5 + (f 2 *D 5 ) 2 /5 + (f 3 *D 5 ) 2 /5 + V c 2 /5 (20)
- V fl 2 (S 4 + f,*D «) /4 + (4/4)*D 4 2 - (l/4)*(f ! *D 4 ) 2
- V f i 2 ⁇ 8 + 2*SQRT(4)*fi ⁇ * D 4 2 /4 (22)
- V on 2 ⁇ 8 + 2*SQRT(4) ⁇ * D 4 2 /4 (23)
- the device comprises an electronic circuit unit which registers the accosicated value of the parameter X au (j), which is defined in the above mentioned description, for each column j of the matrix of display element s and for each raster scan.
- the display device of the present invention is further characterized in that during the raster scan, the amplitude V d of the data voltage +/- V d (which is across a picture element during the non-select period in the case of the given description of the line-at-a-time addressing) is different for columns having a different X au value.
- multi-line addressing there is no question of a bi-level data voltage +/- V d , but multi ⁇ level data voltages are ures; for example, for 3-line addressing, 4 voltage levels will be used with 2 different amplitudes; +/- V 3 and +/- V 3 /3.
- V 3 the value of V 3 will be chosen as different, as mentioned above.
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69323059T DE69323059T2 (de) | 1992-09-30 | 1993-09-30 | Flüssigkristallanseigevorrichtung |
KR1019940701820A KR100343381B1 (ko) | 1992-09-30 | 1993-09-30 | 액정 표시 장치 |
JP6508900A JPH07501636A (ja) | 1992-09-30 | 1993-09-30 | 液晶表示装置 |
EP93921094A EP0614563B1 (de) | 1992-09-30 | 1993-09-30 | Flüssigkristallanseigevorrichtung |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL9201692 | 1992-09-30 | ||
NL9201692A NL9201692A (nl) | 1992-09-30 | 1992-09-30 | Reduktie van Vertikale "Cross-talk" in Dot-Matrix Vloeibaar-Kristal Weergeefinrichtingen, en Realisatie van Grijs-niveau's met behulp van Puls-Hoogte-Modulatie. |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1994008330A1 true WO1994008330A1 (en) | 1994-04-14 |
Family
ID=19861323
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1993/001403 WO1994008330A1 (en) | 1992-09-30 | 1993-09-30 | Liquid-crystal display device |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP0614563B1 (de) |
JP (1) | JPH07501636A (de) |
KR (1) | KR100343381B1 (de) |
DE (1) | DE69323059T2 (de) |
NL (1) | NL9201692A (de) |
WO (1) | WO1994008330A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002095484A2 (en) * | 2001-05-21 | 2002-11-28 | Three-Five Systems, Inc. | Asymmetric liquid crystal actuation system and method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2020875A (en) * | 1978-05-03 | 1979-11-21 | Marconi Co Ltd | Improvements in or Relating to Addressable Matrices |
EP0345399A2 (de) * | 1988-06-07 | 1989-12-13 | Sharp Kabushiki Kaisha | Verfahren und Einrichtung zum Steuern eines kapazitiven Anzeigegeräts |
US5151690A (en) * | 1987-08-13 | 1992-09-29 | Seiko Epson Corporation | Method and apparatus for driving a liquid crystal display panel |
-
1992
- 1992-09-30 NL NL9201692A patent/NL9201692A/nl not_active Application Discontinuation
-
1993
- 1993-09-30 EP EP93921094A patent/EP0614563B1/de not_active Expired - Lifetime
- 1993-09-30 JP JP6508900A patent/JPH07501636A/ja active Pending
- 1993-09-30 WO PCT/JP1993/001403 patent/WO1994008330A1/en active IP Right Grant
- 1993-09-30 KR KR1019940701820A patent/KR100343381B1/ko not_active IP Right Cessation
- 1993-09-30 DE DE69323059T patent/DE69323059T2/de not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2020875A (en) * | 1978-05-03 | 1979-11-21 | Marconi Co Ltd | Improvements in or Relating to Addressable Matrices |
US5151690A (en) * | 1987-08-13 | 1992-09-29 | Seiko Epson Corporation | Method and apparatus for driving a liquid crystal display panel |
EP0345399A2 (de) * | 1988-06-07 | 1989-12-13 | Sharp Kabushiki Kaisha | Verfahren und Einrichtung zum Steuern eines kapazitiven Anzeigegeräts |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002095484A2 (en) * | 2001-05-21 | 2002-11-28 | Three-Five Systems, Inc. | Asymmetric liquid crystal actuation system and method |
WO2002095484A3 (en) * | 2001-05-21 | 2004-01-08 | Three Five Systems Inc | Asymmetric liquid crystal actuation system and method |
Also Published As
Publication number | Publication date |
---|---|
KR100343381B1 (ko) | 2002-11-30 |
DE69323059D1 (de) | 1999-02-25 |
JPH07501636A (ja) | 1995-02-16 |
EP0614563A1 (de) | 1994-09-14 |
NL9201692A (nl) | 1994-04-18 |
EP0614563B1 (de) | 1999-01-13 |
DE69323059T2 (de) | 1999-07-15 |
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