WO1994000935A1 - Procedes de prise d'une decision de justification dans un n×ud d'un systeme de telecommunications numerique - Google Patents

Procedes de prise d'une decision de justification dans un n×ud d'un systeme de telecommunications numerique Download PDF

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Publication number
WO1994000935A1
WO1994000935A1 PCT/FI1993/000270 FI9300270W WO9400935A1 WO 1994000935 A1 WO1994000935 A1 WO 1994000935A1 FI 9300270 W FI9300270 W FI 9300270W WO 9400935 A1 WO9400935 A1 WO 9400935A1
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WO
WIPO (PCT)
Prior art keywords
frame
justification
decision
node
fill rate
Prior art date
Application number
PCT/FI1993/000270
Other languages
English (en)
Inventor
Harri Lahti
Erkki LESKELÄ
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Publication of WO1994000935A1 publication Critical patent/WO1994000935A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/073—Bit stuffing, e.g. PDH

Definitions

  • the invention relates to methods according to the preamble portions of the attached claims 1 and 3 for making a justification decision in a node of a digital telecommunication system.
  • the nodes of a digital transmission network part of the transmission capacity is branched to a specific station while the rest of the capacity passes to the next transmission path.
  • the channels of the transmission frame are disassembled in the node to the level of the branched capacity, and the branching and the through-connection are typically implemented by cabling desired channels in parallel form from one transmission equipment to another.
  • each channel thus has its own interface (typically G.703 compatible) in each transmission equipment.
  • the nodes comprise a great number of interfaces and cables, which increases the cost of the solution.
  • FI Patent Application 904833 this problem is avoided by using a repeater station where unbranched channels are not disassembled into parallel form but they are passed in serial form from one transmission equipment to another over a repeater bus.
  • the present invention can be advantageously applied in the last-mentioned repeater station, although it is also applicable in the first-mentioned repeater station, where both the branching and the through-connection are performed in parallel form, and in any other node where justifica ⁇ tions are made by buffering data into a buffer memory.
  • the repeating transmission equipment of the repeater station locks itself to a frame received over the transmission path and disassembles the channels into elastic buffer memories, the number of which is equal to that of the channels contained in the trans ⁇ mission frame. Data is read from the elastic buffer memories in synchronization with the transmission-side frame counter, and then multiplexed into a new trans ⁇ mission frame.
  • justification bits As the frame received over the transmission path contains not only actual data but also other bits (called frame bits), such as frame alignment signal and service signal bits, writing into or reading from the elastic buffer memories does not take place at an even rate, but the frame bits cause "gaps" of variable length to occur in the time raster in the data writing or reading.
  • the different rates of the channels of a bit stream to and a bit stream from the buffer memory are matched with each other by so-called justification.
  • the justification method may be positive or negative. (In the text below, positive justification is used as an example, if not mentioned otherwise). If the read rate from the buffer memory is higher than the rate of the incoming channel, additional bits containing no information, called justification bits, are added to the outgoing signal to eliminate the difference (positive justification).
  • justification bit which is normally empty
  • justification is usually performed once in each frame, and the use of justification is indicated by justi ⁇ fication service bits. Positive justification will be used as an example below.
  • the need for justification is determined on the basis of the fill rate of the buffer memory by comparing the fill rate with a fixed justification decision limit.
  • both bit streams contain gaps, and therefore the fixed justification decision limit causes large sudden variations in the fill rate of the buffer, and such variations cause timing jitter when the bit stream is disassembled into channels.
  • the problem can be alleviated by using a signal with no gaps in reading from or writing into the buffer memory. In such a case, however, the gaps caused by the frame bits of the bit stream have to be removed by reading from the buffer memory by a clock formed by a phase-locked oscillator and controlled by a phase detector which compares the phases of the read and write counters of the buffer memory.
  • the object of the present invention is to provide a method in which the problems caused by timing jitter are minimized without the use of the above-described phase-locked loops. This is achieved by a method according to the invention, the first embodiment of which is characterized by what is dis ⁇ closed in the characterizing portion of the attached claim 1 and the second embodiment of which is charac ⁇ terized by what is disclosed in the characterizing portion of the attached claim 3.
  • the basic idea of the invention is that the jus ⁇ tification decision is made on the basis of the fill rate of the buffer as previously whereas the values to be compared with each other for making the justifica- tion decision (the justification decision limit or the fill rate value) are changed so that the average phase margin (i.e. fill rate) of the buffer memory remains as constant as possible.
  • the justifica ⁇ tion decisions will be made as evenly as possible, so that the jitter caused by justification occurs at such a high frequency that the loop filter of the elastic buffer will cause it to be filtered off when the chan ⁇ nel is being disassembled.
  • Figure 1 illustrates a repeater station in a digital transmission network, in which repeater sta ⁇ tion the method according to the invention can be applied;
  • Figure 2 illustrates a solution according to the first embodiment of the invention in the repeater sta ⁇ tion shown in Figure 1;
  • Figure 3 illustrates a frame structure used in the transmission equipment of the repeater station
  • Figure 4 illustrates the phase behaviour of an elastic buffer memory when a prior art fixed justi ⁇ fication decision limit is used and the frames in the transmitting and receiving direction are in phase
  • Figure 5 illustrates the phase behaviour of an elastic buffer memory when a prior art fixed justi ⁇ fication decision limit is used and the frames in the transmitting and receiving direction are out of phase
  • Figure 6 illustrates the determination of justi- fication decision limits and the phase behaviour of the elastic buffer memory when a dynamic justification decision limit according to the invention is used and the frames in the transmitting and receiving direction are in phase
  • Figure 7 illustrates the phase behaviour of the elastic buffer memory when a dynamic justification decision limit according to the invention is used and the frames in the transmitting and receiving direction are out of phase
  • Figure 8 illustrates a solution according to the second embodiment of the invention in a repeater sta ⁇ tion shown in Figure 1.
  • Figure 1 shows a repeater station acting as a node in a digital telecommunication system, the method according to the invention being applied at the repeater station.
  • the repeater station comprises transmission equipments 11 and 12, in this specific case radio links, between two transmission paths, in this case radio paths A and B.
  • the antennas of the radio links are indicated by the references 11a and 12a, respectively.
  • the repeater station receives e.g. TDMA (Time Division Multiple Access) channels from the transmission paths A and B, and channels C branched from the TDMA channels are deframed by demultiplexing them to the hierarchical level of the branched chan ⁇ nels.
  • the branched channels C are then wired e.g.
  • TDMA Time Division Multiple Access
  • Unbranched channels i.e. channels passing directly from the transmission path A to the trans ⁇ mission path B (or vice versa) are guided from the transmission equipment 11 (or the transmission equip ⁇ ment 12, respectively) in serial form to the trans- mission equipment 12 (or the transmission equipment 11, respectively) over a repeater bus 13.
  • the repeater station acting as a node in a di ⁇ gital transmission network is described in the above- mentioned FI Patent Application 904833, which is referred to for a more detailed description.
  • Figure 2 illustrates the implementation of the first embodiment of the method according to the in ⁇ vention at the repeater station shown in Figure 1, where the transmission frame is passed as such in serial form from the transmission equipment 11 to the transmission equipment 12 over the repeater bus 13.
  • a frame controller unit 18 provided at the input of the transmission equipment 12 and common to all channels locks itself to an incoming frame, removes justi ⁇ fication, and disassembles the channels of the frame into elastic buffer memories 20 provided in channel- specific buffer units 17.
  • the buffer units are thus equal in number to the channels on the transmission connection. Channels from the transmission path A need not be synchronous, but they may be plesiochronous.
  • each buffer unit comprises an associated write counter 19, which controls writing into the buffer memory, and a read counter 22, which controls reading from the buffer memory.
  • a bit in a specific channel is next in the frame, it is written into the elastic buffer memory 20 in the buffer unit of this channel at a position indicated by the write counter 19, and the write counter is incremented by one.
  • data is read from the elastic buffer memory 20 from a position indicated by the read counter 22 in syn- chronization with the transmission-side frame counter 26.
  • the counts of the read and write counters of the channel are selected by a multiplexer 21 to a summer 23, which calculates a difference E between the write counter and the read counter, i.e.
  • phase margin E is compared by a comparator 24 with a predetermined justification decision limit L, which is obtained from a justi ⁇ fication decision limit memory 25.
  • the result from the comparison is fed to the frame and set counter 26, which controls the frame multiplexer 27 on the basis of the comparison. For instance, if the phase margin E is smaller than the justification decision limit, a justification decision is made, i.e. no bit is read from the buffer memory 20 to the frame multiplexer 27 at the next justification bit of the channel, so that the phase margin increases by one bit (positive justi ⁇ fication). It is not necessary to make a justification decision each time data is read from the buffer memory.
  • the write and read counters reset themselves on reaching the end of the elastic buffer memory.
  • the frames of the frame counters 19 and 26 need not be identical, but the capacity may change at the repeater station.
  • the frame to be transmitted over the trans- mission path B is assembled in the frame multiplexer 27, to the inputs of which data is read from the channel-specific buffer memories 20.
  • Figure 2 will further be referred to after the description of Figure 6.
  • Figure 3 shows the structure of a specific transmission frame, i.e. a frame used in a trans ⁇ mission equipment (radio lin ) having a capacity of 2*2 Mbit/s.
  • Channel data is indicated by numerals (1 or 2) and frame bits by the reference K.
  • the channel data is consecutive so that the data indicated by one belongs to the first 2 Mbit/s system (the first channel) , and the data indicated by two belongs to the second 2 Mbit/s system (the second channel ) .
  • Each set comprises an equal number of data bits, whereas the number of the frame bits K at the beginning of the set varies from zero to eight.
  • Figure 4 illustrates the phase margin, i.e. fill rate of the elastic buffer memory for one frame in a known case in which both writing into the buffer memory and reading from the memory take place by a gapped clock and the justification decision limit is fixed, i.e. 5 bits.
  • Figures 4 to 7 have been drawn by using the frame shown in Figure 3 as an example; they apply for both of the two channels of the frame.
  • the horizontal axis represents time so that one scale interval corresponds to one set.
  • the numbers of the sets in the frame shown in Figure 3 are indicated on the horizontal axis.
  • the vertical axis represents the. phase margin E so that one scale interval corresponds to one bit.
  • the upper curve WR repres ⁇ ents writing into the buffer memory, and the lower curve RD reading from the buffer memory.
  • the area remaining between the curves, indicated by the arrows F, stands for the phase margin of the buffer at a specific time.
  • Figure 4 starts from a situation when the transmitting-direction and receiving-direction frames are in phase and the phase margin E of the buffer is 5 bits. As the frames are in phase, the gaps always coincide in reading and writing and the phase margin is 5 bits all the time. As is to be seen from Figures 3 and 4, the phase changes at each frame bit. For instance, there are three frame bits for each channel in the set zero, and four frame bits in the set three ( Figure 3) , which involves a corresponding change in phase ( Figure 4) .
  • the frame counters on the transmission and reception side operate by different clocks, which need not be mutually synchronous.
  • the transmitting- direction and receiving-direction frames therefore slide with respect to each other.
  • Figure 5 shows a situation in which the justification decision limit is still fixed, i.e. 5 bits, whereas the frames have slid slightly with respect to each other.
  • the justification system ensures that the phase margin will not be smaller than 5 bits.
  • the average phase margin of the buffer has increased considerably, and there are also several successive justifications.
  • the average phase margin of the buffer varies considerably, and the justification decisions are not made evenly; sometimes there are several justifications in succession while at other times justifications occur seldom.
  • Figure 6 shows a corresponding situation when using the dynamic justification decision limit accord- ing to the invention.
  • the justification decision limit is varied in accordance with the phase of the frame to be sent over the transmission path by observing which one of the sets of the frame is to be transmitted next.
  • the justification decision limit of the set zero is 5 bits
  • the justification decision limit of the set one is 4 bits
  • the justi ⁇ fication decision limit of the set two is 3 bits
  • the justification decision limit of the set three is 6 hits
  • the justification decision limit of the set four is 5 bits
  • the justification decision limit of the set five is 4 bits
  • the justification decision limit of the set six is 4 bits
  • the justification decision limit of the set seven is 3 bits.
  • the justification decision limits have been obtained by adding a fixed additional margin of 2 bits to the phase margin measured from a line 60 drawn through the end points of the phase curve RD representing reading form the buffer memory, and rounding up the result.
  • the phase margin of the set three, for instance will be (3.5 + 2) bits, which is rounded up to 6 bits.
  • the set count of the frame and set counter 26 acts as an address for the justification limit memory 25.
  • the justification decision limits L can be determined for any transmission frame in the same way. As the positions of the frame bits in the frame are known, the phase behaviour of the respective read counter, i.e. the curve RD, can be determined. The justification decision limits can then be determined accordingly.
  • the situation illustrated in Figure 7 is similar to that shown in Figure 6 except that the transmission and reception frames now slide with respect to each other. Even in this case the dynamic justification decision limit ensures that the average phase margin remains constant so that the justification decisions will be made evenly.
  • phase margin E Whenever reading data from the buffer memory 20, the current phase margin E is known. This phase margin is summed with the preceding phase margin in the cal ⁇ culator 28 and the average phase margin of the entire frame is calculated from the sum obtained over the entire frame. The average value is compared with a predetermined justification decision limit the value of which depends on the structure of the transmission frame used, that is, on the number of frame bits and the way they are positioned within the frame.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Procédé de prise d'une décision de justification dans un n÷ud d'un système de télécommunications numérique, selon lequel on stocke des données dans au moins une mémoire tampon (20) dont on contrôle le taux de remplissage, et on décide de faire une justification en fonction du taux de remplissage (E), par la comparaison (24) dudit taux avec une limite (L) de décision de justification. Afin de minimiser les problèmes dus aux gigues de rythme, on fait varier la limite (L) de décision de justification en fonction de la phase de la trame du signal à transférer, ou on utilise, comme valeur de taux de remplissage, une moyenne de temps calculée pendant un intervalle de temps prédéterminé.
PCT/FI1993/000270 1992-06-26 1993-06-23 Procedes de prise d'une decision de justification dans un n×ud d'un systeme de telecommunications numerique WO1994000935A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI922992 1992-06-26
FI922992A FI91696C (fi) 1992-06-26 1992-06-26 Menetelmä tasauspäätöksen aikaansaamiseksi digitaalisen tietoliikennejärjestelmän solmupisteessä

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WO1994000935A1 true WO1994000935A1 (fr) 1994-01-06

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0944195A2 (fr) * 1998-03-18 1999-09-22 Fujitsu Limited Sytème de requête de modifications relatives à la charge utile et système de transmission comprenant ce dernier
US6308228B1 (en) * 1998-11-23 2001-10-23 Duke University System and method of adaptive message pipelining

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0248551A2 (fr) * 1986-05-29 1987-12-09 Nortel Networks Corporation Synchronisation de signaux de données asynchrones
US4791652A (en) * 1987-06-04 1988-12-13 Northern Telecom Limited Synchronization of asynchronous data signals
US4928275A (en) * 1989-05-26 1990-05-22 Northern Telecom Limited Synchronization of asynchronous data signals

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0248551A2 (fr) * 1986-05-29 1987-12-09 Nortel Networks Corporation Synchronisation de signaux de données asynchrones
US4791652A (en) * 1987-06-04 1988-12-13 Northern Telecom Limited Synchronization of asynchronous data signals
US4928275A (en) * 1989-05-26 1990-05-22 Northern Telecom Limited Synchronization of asynchronous data signals

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0944195A2 (fr) * 1998-03-18 1999-09-22 Fujitsu Limited Sytème de requête de modifications relatives à la charge utile et système de transmission comprenant ce dernier
EP0944195A3 (fr) * 1998-03-18 2002-12-18 Fujitsu Limited Sytème de requête de modifications relatives à la charge utile et système de transmission comprenant ce dernier
US6308228B1 (en) * 1998-11-23 2001-10-23 Duke University System and method of adaptive message pipelining

Also Published As

Publication number Publication date
FI91696B (fi) 1994-04-15
FI91696C (fi) 1994-07-25
FI922992A (fi) 1993-12-27
FI922992A0 (fi) 1992-06-26

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