WO1994000843A1 - Systeme et procede alternatifs a la detection de viterbi - Google Patents

Systeme et procede alternatifs a la detection de viterbi Download PDF

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Publication number
WO1994000843A1
WO1994000843A1 PCT/US1993/005098 US9305098W WO9400843A1 WO 1994000843 A1 WO1994000843 A1 WO 1994000843A1 US 9305098 W US9305098 W US 9305098W WO 9400843 A1 WO9400843 A1 WO 9400843A1
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WO
WIPO (PCT)
Prior art keywords
digital data
term
maximum likelihood
channel
sequence type
Prior art date
Application number
PCT/US1993/005098
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English (en)
Inventor
Charles M. Riggle
Nersi Nazari
Original Assignee
Digital Equipment Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Digital Equipment Corporation filed Critical Digital Equipment Corporation
Publication of WO1994000843A1 publication Critical patent/WO1994000843A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes

Definitions

  • the present invention is generally related to data detection in the presence of intersymbol interference. More specifically, this invention relates to arrangements and methods for detecting data in the presence of intersymbol interference in communication systems, such as digital recording implementations, etc.
  • VD Viterbi detector
  • a pipeline of three processing units is typical and includes a transition metric unit for computing a metric corresponding to each possible transition from one state to another in the trellis, an ACS unit for carrying out the ACS recursion process, and a survivor memory unit for selecting the appropriate output bits.
  • a transition metric unit for computing a metric corresponding to each possible transition from one state to another in the trellis
  • an ACS unit for carrying out the ACS recursion process
  • survivor memory unit for selecting the appropriate output bits.
  • the ACS unit typically comprises the processing bottleneck in high data rate implementations because of the non-linear feedback loop used for realizing the add and compare operations necessary prior to selection of a specific path.
  • PRS Partial Response Signaling
  • a PRS is characterized by a polynomial of the form (1-D) (1 + D) n where "n" is selected according to the normalized density of the channel.
  • “n” is large and, consequently, the hardware required to process this information is significant. Even if "n” is small, the amount of hardware required is usually of serious concern.
  • the (1-D) term together with its associated precoder, basically denotes the polarity changes in subsequent pulses; i.e., succeeding l's are recorded as +1, -1, +1, -1, ... (with zeros unchanged) . Therefore, one can find an exact solution that keeps track of polarity of l's for each path. This exact solution, however, leads to polarity bits and a significant complexity increase in metric computation.
  • an improved system for implementing data detection, in the presence of intersymbol interference is realized by taking, for each path, the noise free amplitude that is closest to the input of the detector.
  • the present invention eliminates the (1-D) term altogether an ⁇ f hence reduces the hardware complexity by a factor of 2.
  • this inventive strategy which is referred to as "closest metric maximum likelihood detector” (CMMLD)
  • CMMLD metric is exactly the same as the Viterbi detection metric when input and noise free values have the same polarity and the CMMLD metric has a smaller value than the one of Viterbi detection when noise free and input values differ in polarity.
  • Fig. 1 is a ' block diagram of a traditional data processing strategy of coded user data through a magnetic channel followed by an equalizer, from which Viterbi detection begins;
  • Fig. 2 is a block diagram of a data processing strategy of coded user data, in accordance with the present invention.
  • Fig. 3 is a block diagram of a traditional data processing strategy of uncoded user data
  • Fig. 4 is a block diagram of a data processing strategy of uncoded user data, in accordance with the present invention.
  • Fig. 5 is a block diagram of a traditional hardware implementation for data processing
  • Fig. 6 is a block diagram of a hardware implementation for data processing, in accordance with the present invention.
  • Fig. 7 is a flow chart illustrating the sequential flow of operations involved in the novel data processing implementation, in accordance with the system of the present invention.
  • the enhanced data detection implementation described and claimed herein has been found to be useful with digital data detection applications wherein decoding is based on the application of the well-known Viterbi algorithm to the problem of eliminating inter-symbol interference in baseband communication systems and the like.
  • the Viterbi algorithm and a variety of applications thereof to Viterbi detectors or decoders are well known to those skilled in the art and are, accordingly, not described in detail herein.
  • the present invention is discussed in the context of an exemplary application thereof — for magnetic recording channels in which the so-called Partial Response Signaling (PRS) equalization is followed by Viterbi detection of the equalized signal. While the implementation disclosed herein is particularly applicable for magnetic recording channels, any software or hardware implementation adaptable for PRS equation followed by Viterbi detection would benefit from the present invention.
  • PRS Partial Response Signaling
  • Fig. 1 illustrates a prior art implementation, in block diagram form, of a magnetic channel 10 (represented by the two term polynomial (1/ ( 1 ⁇ D) ) (1 - D) ) and an equalizer 12 (represented by the term (1 + D) 2 ) processing coded data from a magnetic channel 14, such as a magnetic tape or disc, in order to feed a Viterbi detector 16.
  • a "coded channel” is referred to as one that has some coding constraint that needs to be preserved by the channel; for example, a run-length-limited constraint such as a (1,7) code widely used in today's magnetic recording channels.
  • the symbol ⁇ denotes exclusive-or operation.
  • the lead 18 emanating from between the two terms in the magnetic channel 10 corresponds to the reference signal for the detection channel.
  • This reference signal represents the actual data in the magnetic channel 10 before Partial Response Signaling (PRS) equalization, which is characterized by a polynomial including the terms (1-D) (1 + D) n .
  • PRS Partial Response Signaling
  • a PRS system with n equal to 2 is considered in all cases. Because Fig. 1 depicts this case for n, the polynomial (1-D) (1 + D) n , is obtained from the (1-D) term in the magnetic channel 10 and the (1 + D) 2 term in the equalizer 12.
  • the improved system of Fig. 2 which is in accordance with the present invention, realizes the same data detection results (with less processing) as the above implementation by taking, for each path, the noise free amplitude that is closest to the input of the detector.
  • the noise free amplitude is taken from the input to the magnetic channel 10. Consequently, the Viterbi detector 16 from Fig. 1 is modified (depicted as Viterbi detector 16' in Fig. 2) to compensate for this change.
  • CMMLD closest metric maximum likelihood detector
  • Figs. 3 and 4 correspond to Figs. 1 and 2, respectively, with the exception that the user data received by the arrangement of Figs. 3 and 4 is not coded. Therefore, a precoder 22 (represented by 1/ (1 ⁇ D 2 ) ) Is arranged between the user data and the magnetic channel 10. It should be noted that, in this situation, the noise free amplitude is still taken from the input to the magnetic channel 10. Accordingly, the traditional Viterbi detection strategy of Figs. 1 and 3 takes as its channel the (1 - D) part of the magnetic channel and combines it with (1 + D) 2 term due to the equalizer of the PRS channel. The resulting channel as far as the detector is concerned is, therefore, (1-D) (1 + D) 2 .
  • the CMMLD detector uses the fact that the entire magnetic channel can be viewed as one that alternates polarities of succeeding l's (leaving 0' s intact) . It basically detects the (1 + D) 2 channel, a channel with half as much complexity of the traditional Viterbi detection.
  • a typical detector consists of three parts: a branch metric unit 30, an add-compare-select (ACS) unit 32 and a path memory unit 34.
  • ACS add-compare-select
  • the implementation of such units in a Viterbi decoder is well known in the relevant art.
  • A.J. Viterbi Error Bounds for Convolutional Codes and Asymptotically Optimal Decoding Algorithm, IEEE Transactions on Information Theory, Vol. IT-13, pp. 260-269, April 1967; A.J.
  • Fig. 6 the arrangement is modified to accommodate the step of computing the noise free amplitudes as positive. This step is accomplished using an absolute value circuit 36 at the input of the branch metric unit 30' .
  • This arrangement clearly shows that each of the units 30, 32 and 34 of Fig. 5 requires twice as much processing to implement the corresponding functions, as depicted in units 30', 32' and 34' of Fig. 6.
  • the only additional complexity in the CMMLD detector of Fig. 6 is the absolute value circuit 36, which can be realized with minimal hardware.
  • Fig. 7 the implementation depicted in each of Figs. 2, 4 and 6 is described in conjunction with a flow chart illustrating a sequence of operations which may be used by a microcomputer to practice the present invention.
  • the sequence of operations immediately flows from the start block 40 to step 42 for system initialization. This includes hardware initialization and initialization of the various linking registers used in connection with the branch metric unit 30', the ACS unit 32' and the path memory unit 34' .
  • step 44 the next piece of data is retrieved to begin the CMMLD strategy.
  • the absolute value of this data is taken at step 46, and then a counter ("i") is set to one at step 48 to indicate that the CMMLD strategy is handling the first state.
  • the two path metrics for state i are computed. This involves calculating an ideal expected value for positive values from the term including (1 + D) n , subtracting the absolute value for the data therefrom and then squaring that difference to calculate a resultant set of branch metric values.
  • Step 50 flow proceeds to steps 52, 54 and 56 where the ACS operations are performed.
  • step 58 the counter ("i") is incremented for the next state.
  • Step 60 entails determining whether all of the states have been processed. Thus, if the value of i is not greater than 2 n , then flow returns to step 50; flow proceeds to step 62.
  • the computer ascertains the smallest of the metric values and provides a decision bit corresponding thereto .
  • step 64 flow proceeds to step 64 where a decision is made as to whether there is additional data to process, in which case flow proceeds to step 66 where the add-compare-select operations in the path memory for the term including (1 + D) n are tracked and recorded. From step 66, flow returns to step 44 for the next piece of data. If there is no additional data to process, flow stops at block 68.
  • the present invention can be readily implemented in software by modifying existing programs.
  • the traditional program is similar to the operation of Fig. 7 with differences including: the addition of step 46, the calculations of step 50 and the additional processing (twice as much) which would be reflected in step 60.
  • the CMMLD metric is exactly the same as the Viterbi detection metric; and when noise free and input values differ in polarity, the CMMLD metric has a smaller value than the one of Viterbi detection.
  • This implementation does not cause any significant degradation in performance of CMMLD as compared to traditional Viterbi detection for systems of reasonable performance. This has been verified by extensive computer simulations for error rates of lxlO -4 or better. The reason being that the closest sequences that cause errors are not affected by this strategy; they are already ones that cause small metrics. The end result is that the above-identified novel CMMLD implementation realizes approximately the same performance as that provided by traditional Viterbi detection, with half the processing hardware. In applications in which CMMLD is implemented in software, this equates to an effective compression of the computation time by almost a factor of two compared to the traditional Viterbi detection strategy.

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Error Detection And Correction (AREA)

Abstract

Un système amélioré appelé 'détection de vraisemblance maximum métrique la plus proche (CMMLD)' met en application la détection de données en présence d'une interférence entre symboles. Le système consiste en un égaliseur de signalisation à réponse partielle ('PRS') (12) suivi d'un détecteur de Viterbi (16'). Le signal d'entrée, d'amplitude exempte de bruit, injecté dans le détecteur est prélevé à proximité de l'entrée du détecteur plutôt qu'au milieu du canal de PRS comme dans les systèmes conventionnels. Le système comprend également un ensemble (36) servant à calculer la valeur absolue du signal de données avant qu'il ne pénètre dans le détecteur, ce qui réduit la charge de calcul s'exerçant sur ce dernier. On peut éventuellement utiliser un précodeur de données (22) avec les données d'utilisateur non codées.
PCT/US1993/005098 1992-06-26 1993-06-01 Systeme et procede alternatifs a la detection de viterbi WO1994000843A1 (fr)

Applications Claiming Priority (2)

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US90574992A 1992-06-26 1992-06-26
US07/905,749 1992-06-26

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996033491A1 (fr) * 1995-04-20 1996-10-24 Seagate Technology, Inc. Compensation metrique des branches pour une detection de sequences numeriques
US6393598B1 (en) 1995-04-20 2002-05-21 Seagate Technology Llc Branch metric compensation for digital sequence detection

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4614933A (en) * 1984-02-20 1986-09-30 Fujitsu Limited Viterbi decoder with the pipeline processing function
CA2058102A1 (fr) * 1990-12-20 1992-06-21 Takao Sugawara Decodeur viterbi a egaliseur adaptatif

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4614933A (en) * 1984-02-20 1986-09-30 Fujitsu Limited Viterbi decoder with the pipeline processing function
CA2058102A1 (fr) * 1990-12-20 1992-06-21 Takao Sugawara Decodeur viterbi a egaliseur adaptatif

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE vol. 3, November 1989, DALLAS, TEXAS, US pages 1714 - 1718 , XP000144866 HIROYUKI YASHIMA ET AL. 'A new type of Viterbi decoding with path reeduction' *
IEEE JOURNAL OF SOLID-STATE CIRCUITS vol. 26, no. 12, December 1991, pages 1981 - 1987 , XP000272859 C.B. SHUNG ET AL. 'A 30Mhz Trellis Codec Chip for Partial Response Channels' *
IEEE TRANSACTIONS ON INFORMATION THEORY vol. 35, no. 2, March 1989, NEW YORK, NY, US pages 419 - 427 , XP000048392 LINEU C. BARBOSA 'Maximum Likelihood Sequence Estimators: A Geometric View' *
INTERNATIONAL CONFERENCE ON COMMUNICATIONS - ICC 91 vol. 2, June 1991, DENVER, US pages 820 - 824 , XP000269604 K.J. KNUDSON 'Producing soft-decision information at the output of a class IV Partial Response Viterbi detector' *
NHK TECHNICAL MONOGRAPH no. 31, March 1982, pages 3 - 26 K. YOKOYAMA ET AL. 'Digital videotape recprder' *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996033491A1 (fr) * 1995-04-20 1996-10-24 Seagate Technology, Inc. Compensation metrique des branches pour une detection de sequences numeriques
US6393598B1 (en) 1995-04-20 2002-05-21 Seagate Technology Llc Branch metric compensation for digital sequence detection

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