WO1993025957A1

WO1993025957A1 - Information processing apparatus and additional control device used therefor, and information processing method therefor

Info

Publication number: WO1993025957A1
Application number: PCT/JP1992/000781
Authority: WO
Inventors: Ken-Ichi Wakabayashi; Chitoshi Takayama; Tadashi Shiozaki
Original assignee: Seiko Epson Corporation
Priority date: 1992-06-18
Filing date: 1992-06-18
Publication date: 1993-12-23

Abstract

Conventionally, information is processed by an additional controller added to an electronic device, which receives external data, unlike this processing method, an additional control device is provided with a configuration capable of communicating, and the additional control device receives the data from the outside, the data is processed through a processor in the additional control device, and thereafter, the processed data is sent out to the electronic apparatus. An electronic apparatus for processing data, e.g., an electronic controller in the body of a printer receives ordinarily the data to be printed through the data input port. However, in the present apparatus, a cartridge (503) has a communication control section (604), and receives the data to be printed which is described by a page description language from the outside, and further, develops this data as a picture data by the processing of a microprocessor (601). Thereafter, the microprocessor (601), via a double bank control circuit (624), outputs this picture data to the electronic control apparatus of a laser printer, and makes the laser printer print the data.

Description

TECHNICAL FIELD An information processing apparatus, an additional control apparatus used for the same, and an information processing method.

The present invention relates to an information processing device including various electronic devices and an additional control device mounted thereon, an additional control device used in the information processing device, and an information processing method thereof. Regarding the configuration to receive well and how to process the received information.

[Background Art]

In recent years, electronic devices based on digital operations such as personal computers, word processors, workstations, etc., or printers, facsimiles, electronic notebooks incorporating microprocessors, Electronic musical instruments, electronic cookers, and electronic cameras are used in a wide range of society. Also, automobiles, robots, machine tools, and various electric appliances that use microprocessors are widely used in practice.

Devices based on such digital logical operations are not only capable of more flexible control and data processing than simple feedback control and the like realized only with a window, but also have a soft There is an advantage that the substantial function can be changed by changing the key. Therefore, even in the same door, simply changing the contents of R0M that stores the processing procedure or loading a new program from the external device such as a flexible disk into the main memory can be performed. However, it is possible to realize completely different control. Furthermore, there is an advantage that the purge of functions can be performed only by changing the software.

However, the ability of the processor to actually perform the processing is ultimately determined by the hardware, for example, the number of processings per time, the number of bits that can be handled at one time, and the bus width for transferring data. However, what is improved by the software version up is only limited to the improvement of usability at most, The ability of existing electronic devices could not be significantly improved. Also, purging up due to software changes often requires ROM replacement if the software is burned to R0M, which is often difficult in practice. . For this reason,

Purging software is difficult except for the model whose ROM is scheduled to be replaced from the beginning of the design, except that the software is supplied on a replaceable medium such as a flexible disk. Was.

Originally, there are so-called accelerators that try to improve the functions of the entire computer by completely replacing microprocessors in personal computers, etc., but there are CPUs on the motherboard. It was not something that anyone could easily do, such as having to exchange it. Electronic devices, such as personal computers, may be provided with connectors that require the installation of ROM card-on cartridges and the like. If an additional control device can be mounted on such a connector, the functions of the electronic device can be improved, added, or changed. However, considering the configuration of the data transfer path of such a connector, the internal of

In many cases, it is a read-only signal line from the viewpoint of the processor. In this case, data cannot be received from the processor on the electronic device side. Therefore, it is necessary to attach an accelerator to this connector. And could not.

On the other hand, consumer electronic devices such as printers, facsimiles, electronic notebooks, electronic musical instruments, electronic cookers, and electronic cameras that incorporate microprocessors, or automotive electrical components, robots, and machine tools In industrial electronic devices such as machinery, and various electric appliances, such improvements and changes in functions are not considered at all, and even if an extension connector 4 is provided, only data is read. It is common to provide a connector that is limited to the functions described above. This problem will be explained in detail using a page printer as an example.

In recent years, the spread of page printers such as laser printers has been remarkable, and they are about to become the mainstream of high-speed output devices for data from computers. In the case of a laser printer, a printer having a resolution of about 240 to 800 DPI and a printing capability of several pages per minute has been developed. Such a printer uses a zero graph unit using a photosensitive drum as an engine for printing, and is used for charging, Since the processes of exposure, toner application, and transfer are performed continuously in synchronization with the rotation of the photosensitive drum, one page of image is stored in memory and the printing process is started.

Therefore, the memory for image expansion provided in the page printer needs a capacity to store at least one page of images in the memory, and if image data is not compressed. However, the capacity is determined by the resolution and the size of paper that can be processed. For example, if the resolution is 300 DPI and the paper size is 8 inches wide and 10 inches high, a total of 8 X 10 X 3 0 X 3 00 = 7, 2 This means that pixels of 0,000 dots will be handled, and at least 0.9 megabytes of memory will be prepared.

Printers that receive information such as character codes and line and column pitch as print data and develop them as images, or receive programs written in page description language The printer that interprets and expands the image requires processing to calculate and generate bit images based on the print data, which greatly reduces the overall processing speed compared to simple bit image transfer. There was a problem. That is, the processing speed of the printer is mainly determined by the processing capability of the processor and the access time of the memory, etc., greatly increasing the printing capability of the zero graph unit itself. It is below.

For example, if you consider a page printer that can print 10 pages per minute, the time allowed to prepare image data for a single print is only 6 seconds. To expand all 0.9 megabytes of data per second, the processing time allowed per byte is only 6.67 microseconds (6 seconds / 0.9 megabytes). G). This processing speed is only feasible with the high-speed RISC evening processor currently on the market. On the other hand, a zero-graph unit often already has a printing capacity of about 10 sheets Z. Therefore, at present, the processing capacity of the control unit that processes print data is the key to improving the overall printing speed.

For this reason, in conventional laser printers, etc., the image development ability may be less than the capability of the zero graph unit, and with the improvement of microprocessor technology, processors with high image development ability may be used. Enhance functionality later as they become available I couldn't do that. Some page printers have an expansion slot prepared in advance, and the functions are to be expanded by installing a font or cartridge with a built-in font here. With a certain force, the data bus structure of the slot connector is read-only from the cartridge side, so data can be transferred to the cartridge side for processing. Did not.

Furthermore, when examining the method of communication between the printer and the computer, it is found that, for example, a computer having an interface compliant with the Centronics standard, for example, has a computer side. Even if a high-speed interface such as an Ethernet is prepared, the printer cannot accept it and can only perform low-speed data transfer, so this is the system bottleneck. It was thought that it would be a hike.

The additional control device, the information processing device, and the information processing method of the present invention are intended to solve such a problem and to improve, change, and add the overall capability of the electronic device.

DISCLOSURE OF THE INVENTION

The present invention relates to a configuration in which an additional control device mounted on an electronic device receives data directly from the outside through communication and performs processing, and an information processing device including the electronic device with the additional control device mounted thereon In this case, there is an effect that the data can be processed on the additional control device side. As a whole, the additional control device can directly receive and process data that was conventionally processed by the electronic device, and the functions of the electronic device could be improved or added. Or can be changed.

(1) Invention as an information processing device

This invention made as an information processing device,

A first processor capable of performing a logical operation, first storage means for storing processing executed by the processor, and a signal line capable of exchanging data with the first processor. An electronic device having a connector;

An additional control device connected to the connector of the electronic device;

An information processing apparatus comprising:

In the additional control device, A communication means for receiving data from an external device;

A second processor that performs processing different from that of the first processor, and at least a processing procedure that the second processor executes on data received via the communication means. Second memorized storage means,

Data output means for outputting the data processed by the second processor to the electronic device;

The gist is to have

In this information processing device, the additional control device receives data from an external device through the communication means, and the second processor performs the first processing in accordance with the processing procedure stored in the second storage means. Performs processing different from that of the processor and outputs it to the electronic device. Therefore, the information processing device in which the additional control device is added to the electronic device can realize processing different from that of the electronic device. It can also receive and process data that the electronic device could not receive.

Here, it is assumed that the data received from the outside by the communication means includes data having a property different from the data that can be processed by the first processor of the electronic device, and the second storage means has the property It is also preferable to store a procedure for processing data having different numbers. In this case, data that could not be handled by the electronic device can be processed as an information processing device. For example, when the electronic device is a printer, even if the printer itself cannot handle the program described by the page description language, the second storage means in the additional control device stores the information for the page description language. Storing the interpreter makes it possible to handle it.

Further, the additional control device may include processing information output means for outputting information on the processing of the data to the electronic device while the second processor is performing the processing on the data. . The processing information output means may output at least one of the amount of processed data, the name of the data being processed, and the remaining processing time as information relating to the data processing. In addition, the electronic device can know information on the processing of the additional control device. In addition, the electronic device may include a console panel for displaying predetermined information, and the information output by the processing information output means of the additional control device may be displayed on the console panel of the electronic device. If The user can easily know the information on the processing of the additional control device.

Conversely, it is also preferable to adopt a configuration in which information on the electronic device side is output to the additional control device. Such information may include, for example, operation information of a console panel provided in the electronic device and color information of the electronic device.

The signal line connected to the connector of the electronic device includes at least a part of the address signal line of the first processor, and the data bus connected to the connector is the first. If it is configured to be read-only from the perspective of the processor, it is difficult to send data from the electronic device to the additional control device as it is, but the electronic device sends information to be output. It is assumed that the address to be accessed is reflected, the read processing is performed on the address, and in response to the read processing, the additional control device extracts the information contained in the address. For example, data can be sent to the additional control device using a read-only bus.

The additional control device includes a RAM for storing the program, program expansion means for expanding the data received by the communication unit into the RAM as a program, and a predetermined address of the expanded program. A control transfer means for transferring control of the second processor can be provided, and a program sent from outside through communication can be executed by the additional control device.

Such programs include a program for debugging the additional control device, a program for modifying the processing procedure for data processing stored in the second storage means, and a program for processing higher than the processing procedure for data processing. A program that implements the processing procedure of a function can be considered. Further, the additional control device has a connector capable of adding memory, and the connector has a ROM or a data storing a processing procedure to be executed on the data received through the communication means. It is also preferable to install a memory card provided with a RAM capable of storing evenings.

In addition, the additional control device is provided with third storage means for storing the processing executed by the first processor of the electronic device, and the electronic device is provided with the third storage means in the additional control device. It is conceivable to provide a means for transferring the control of the first processor to the stored processing at a predetermined timing. In this case, the processing performed by the electronic device can also be prepared on the additional control device side. Can be realized.

(2) Invention as additional control device

This invention made as an additional control device,

A first processor capable of performing a logical operation, an additional control connected via a connector provided in the electronic device to an electronic device including first storage means storing processing executed by the processor; A device,

A communication means for receiving data from an external device;

A second processor that performs processing different from that of the first processor, and at least a processing procedure that the second processor executes on data received via the communication unit is stored. A second storage means,

The gist is to have

The additional control device receives data from an external device through communication means, and the second processor performs processing different from that of the first processor according to the processing procedure stored in the second storage means. This is output to the electronic device. Therefore, when this additional control device is added to the electronic device, it is possible to realize a process different from the process realized by the electronic device itself as a whole.

The additional control device can have various configurations as described in the section of (1) Invention as information processing device.

(3) Invention as an information processing method

The invention made as the information processing method,

A first processor capable of performing a logical operation, an electronic device including first storage means for storing processing executed by the processor, and a first processor connected to the electronic device via a connector; An information processing method performed in cooperation with an additional control device having a second processor that performs processing different from that of the first processor.

In the additional control device, Receives data directly from external devices by communication,

The second processor performs a process on the data received by the communication according to a processing procedure stored in a second storage means readable from the second 'processor. Do,

Outputting the data processed by the second processor to the electronic device;

This is the gist.

In this information processing method, the additional control device directly receives data from an external device through communication, so that data that cannot be received by the electronic device can be processed.

This information processing method can also have the various configurations described in the section “(1) Invention as information processing device”.

(4) Invention applied to the printer

The information processing device, additional control device, and information processing method described above can be applied to various devices.

For example, as an information processing device,

The electronic device is a printer that expands print data received from the outside and prints the data.

The additional control device is a cartridge mounted on the connector of the printer, and the second storage means interprets the print data received via the communication means and expands the image data. A configuration for storing an interpreter in a page description language is possible.

In this case, it is possible to easily add a processing function to the printer that could not process the page description language, and to easily change or improve the processing capability of the page description language. ,

It is attached to the connector of the electronic device, which is a printer that expands the print data received from the outside and prints it, in the form of a force trigger,

The second storage means interprets the print data received via the communication means and interprets the image data. A configuration is possible in which an interpreter in a page description language that develops overnight is stored. Furthermore, as an information processing method,

An additional control device mounted in the form of a cartridge on the connector of the electronic device interprets print data received directly from the outside through communication using a page description language interpreter stored internally, and stores image data. And expand

The electronic device can be configured to receive image data and perform printing.

The present invention can be applied to equipment other than a printer. For example, by applying to a facsimile, a communication means for digital communication is provided on the additional control device side, and up to the G3 standard. For example, the facsimile that can only be processed by the G4 is compatible with the G4, and it is applied to the electronic musical instrument. It is possible to apply to other devices.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a printer device according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of the electronic control unit 10 built in the printer main body 1 of the embodiment.

FIG. 3 is a perspective view showing an external shape of the cartridge 3 and a state of attachment to the printer main body 1.

FIG. 4 is a block diagram schematically showing the internal configuration of the cartridge 3.

FIG. 5 is a flowchart showing the processing on the cartridge 3 side.

FIG. 6 is a block diagram showing another configuration for performing communication.

FIG. 7 is a block diagram showing still another configuration.

FIG. 8 is a block diagram showing a modification of the first embodiment.

FIG. 9 is a perspective view showing the appearance of the laser printer 500 of the second embodiment. FIG. 10 is a perspective view showing the shape of another laser printer 500.

FIG. 11 is a block diagram showing the overall configuration of the second embodiment.

FIG. 12 is a perspective view showing the outer shape of a cartridge 503 in the second embodiment. FIG. 13 is an exploded perspective view showing the structure of the cartridge 503. FIG.

FIG. 14 is a perspective view showing an array of elements of the cartridge 503 on the substrate. FIG. 15 is an explanatory diagram showing a configuration of a signal line in the connector CN 11. FIG. 16 is an explanatory diagram showing an address map of the cartridge 503 viewed from the electronic control device 501 side.

FIG. 17 is an explanatory diagram showing an address map of the cartridge 503 as viewed from the microprocessor 601 side.

FIG. 18 is a block diagram showing the internal configuration of the cartridge 503.

FIG. 19 is a block diagram illustrating the configuration of the communication control unit 604.

FIG. 20 is a circuit diagram showing a configuration example of the interrupt request register 640.

FIG. 21 is a circuit diagram showing a configuration example of the polling command register 643.

FIG. 22 is an explanatory diagram showing the contents of the status register 645.

FIG. 23 is a circuit diagram showing a configuration example of the read control circuit 620.

FIG. 24 shows an electronic control unit for realizing data transfer using the read control circuit 620.

50 This is a flowchart showing the processing on the 1 side.

FIG. 25 shows a cartridge for realizing data transfer using the read control circuit 620.

This is a flowchart showing the processing on the 503 side.

FIG. 26 is a flowchart showing processing on the electronic control device 501 that realizes data transfer using the FIFO control circuit 623.

FIG. 27 is a flowchart showing processing on the cartridge 503 side for realizing data transfer using the FIFO control circuit 623.

FIG. 28 is a circuit diagram showing a configuration example of the double bank control circuit 624. FIG. 29 is a flowchart showing a process for starting data transfer using the double bank control circuit 624.

FIG. 30 is a flowchart showing the response processing on the electronic control device 501 side.

FIG. 31 is a flowchart showing a process on the electronic control device 501 that realizes data transfer using the double bank control circuit 624. FIG. 32 is a flowchart showing processing on the cartridge 503 side for realizing data transfer using the double bank control circuit 624.

FIG. 33 is a timing chart showing the timing of printing image data performed by controlling the laser engine 505.

FIG. 34 is a flowchart showing a processing routine for changing the set value stored in the EEPROM. -

[Explanation of symbols]

1 Printer body

3 Cartridge

5 Computer

1 0 Electronic control unit

1 1 Connector

1 2 Semiconductor laser device

1 5 Zero Graph Unit

3 1 C PU

32 A Dress Bath

34 Data bus

36 Control signal bus

4 1 Address decoder

43 R OM

45 D RAM

7 1 C PU

73 R OM

75 RAM

77 Gate Array

95 RAM

500 laser printer

50 1 Electronic control unit 503 Cartridge

505 Laser engine

507 Workstation

5 1 0 C PU

5 1 4 Data input port

5 1 7 Register

5 1 8 Console panel

5 1 9 Console panel I / F

520 Double buffer circuit

550 printed circuit board

60 1 Micro processor

602 Memory section

603 Data transfer control unit

604 Communication control unit

620 Read control circuit

62 1 F I F O Memory

623 F I F O control circuit

624 Double buffer control circuit

635 Bus control unit

640 Interrupt request register

643 Command register

645 Status register

647 Transfer flag register

649 P ROM control register

650 Control Register Evening

653 F I F O write register

655 F I F O read register

670 EE PR0M [Best Mode for Carrying Out the Invention]

Hereinafter, the embodiment will be described. However, since the description is diversified, the description is divided into the following sections.

[i] First embodiment

A. Overall configuration of hardware

B. Configuration and function of electronic control unit 10

C. Configuration of Cartridge 3

D. Data transfer and expansion from connector 7

E. Operation of electronic control unit 10

F. Effects of the first embodiment

G. Modified Example of First Embodiment Part 1

H. Modification Example 1 of First Embodiment Part 2

[ii] Second Embodiment

A. Description of overall configuration

B. Cartridge structure

C. Cartridge address space

D. Schematic configuration inside the cartridge and configuration of the communication controller

E. Explanation of data transfer control unit 603

F. Description of each register

G. Configuration and Function of Readout Control Circuit 620

Configuration and function of H.FIFO control circuit 623

I. Configuration and Function of Double Bank Control Circuit 624

J. Printing image data

K. Effect of the second embodiment

L. Other examples

[i] First embodiment.

A. Overall configuration of hardware Preferred embodiments of the present invention will be described below to further clarify the configuration and operation of the present invention described above. First, an embodiment in which the present invention is applied to a printer will be described. FIG. 1 is a block diagram showing a schematic configuration of a printer main body 1 of the present embodiment and a cartridge 3 mounted on the printer main body. As shown in the figure, the printer main body 1 has a connector 6 for connecting to a computer 5, and normally receives data for printing from the connector 6. On the other hand, the cartridge 3 is provided with a connector 7 for a high-speed oral communication network (LAN), and is connected to a LAN cable 8. As the local area network, Ethernet (trademark of Xerox Corporation) or the like is used. A work station 9 is connected to the local area network, and the cartridge 3 can receive data directly from the work station 9. The communication between the cartridge 3 and the workstation 9 will be described later.

As shown in the figure, the printer main body 1 is a so-called page printer of a zero graph method, and forms an image on a sheet of paper P by a zero graph method based on print data. The electronic control unit 10 that inputs print data and develops images inside the printer body 1, the connector 11 to which the address bus and data bus of the electronic control unit 10 are connected, and the electronic control unit 10. Semiconductor laser device 12 driven by controller 10, zero graph unit 15 composed mainly of photosensitive drum 14, paper cassette 17 for storing paper P, photosensitive drum 1 for paper P A transport mechanism 19 that transports the paper so that it contacts the peripheral surface of 4, a heat fixing roller 21 that heats the toner-transferred paper P to fix the toner 21 and a tray where the printed paper P is discharged 2 and 3 are provided.

The Xerographic unit 15 is a charging unit 25 that charges the surface of the photosensitive drum 14 and the toner that has been charged by the laser beam from the semiconductor laser device 12 is coated with the toner itself. Yes Toner unit 27, composed of toner removal unit 29 for removing toner remaining on photosensitive drum 14 after transfer to paper P. The electronic control device 10 drives the semiconductor laser device 12 in synchronization with the rotation of the photosensitive drum 14 and irradiates a portion corresponding to an image to be printed with laser light to form a latent image. Since the charge at the portion irradiated with the laser beam is lost, the toner charged to the same sign as the photosensitive drum 14 is transferred only to the portion where the charge is lost. One sheet of paper P is pulled out of the paper cassette 17 in synchronization with the rotation of the photosensitive drum 14, and is sent to the photosensitive drum 14 by the transport mechanism 19. Since the paper P is conveyed while being sandwiched between the photosensitive drum 14 and the transfer roller 30, most of the toner on the photosensitive drum 14 is transferred onto the paper P. The paper P is sent to the heat fixing roller 21 while holding the toner on the surface, where it is heated to melt the toner and fixed on the paper P. Although the printing process in the printer main body 1 has been briefly described above, the present invention is not limited to the laser printer. For example, an LED is used for exposing the photosensitive drum 14. The present invention can be applied to various printers, such as those used and those employing an ink jet method for printing.

B. Configuration and function of electronic control unit 10

Next, as shown in _c Figure 2 illustrating a configuration of the electronic control unit 1 0 built in printer main body 1, the electronic control unit 1 0 is known C PU 3 is a process Tsu service that performs overall process It is configured as an arithmetic and logic operation circuit centered on 1 and has a configuration in which the following elements are mutually connected by an address bus 32, a data path 34, a control signal bus 36, and the like. Connected to these paths are the address decoder 41, ROM43, dynamic RAM (hereinafter referred to as DRAM) 45, and memory control unit (hereinafter referred to as MCU). 47, IZO port 49, laser IZF 51, connector 11 and so on. Each element is connected to each bus in a readable and writable manner. However, only the connector 11 has a bus driver 52 provided between it and the data bus 34, and when viewed from the CPU 31, Force trigger 3 connected to connector 11 is a read-only device.

The address decoder 41 decodes an address signal generated by the CPU 31. When a certain address is designated, the ROM decoder 43 decodes the ROM 43, according to the allocation to the memory space. Select signals are output to DRAM 45, I / O port 49, and laser I / F 51. The ROM 43 has a built-in processing program, and the CPU 31 normally operates according to the program stored in the ROM 43. The DRAM 45 is for expanding image data, and since it is necessary to store at least one page of image data, the DRAM 45 has a capacity of 2 megabytes in this embodiment. The MCU 47 analyzes the control signal output from the CPU 31 and outputs a control signal such as R0M43, DRAM45, etc., and reads the memory and I / O port read / write signal. Output and determine the refresh timing of DRAM45. The MCU 47 is connected to a refresh timer 53, which receives a signal from the refresh timer 53 and uses a refreshable timing. If it is determined that there is, the MCU 47 outputs a refresh address and outputs the refresh address to the DRAM 45 via the multiplexer 55. The I / O port 49 receives print data from an external computer 5 and interfaces with a motor (not shown) of the zero graph unit 15. The laser I / F 51 is connected to a cartridge 3 that drives the semiconductor laser device 12 and controls an interface with the semiconductor laser device 12. The electronic control unit 10 further includes a timer 57, which is connected to the connector 11 and the CPU 31.

The basic functions of the printer body 1 equipped with the electronic control unit 10 are the print data (pre-developed in the bit image) received from the external computer 5 via the IZO port 49. The data) into the internal DRAM 45, and when the data for one page has been prepared, control the zero graph unit 15 and drive the semiconductor laser device 12 so that the image data remains as it is. It is to be printed. In addition to this basic function, the printer body 1 of the present embodiment uses the cartridge connected to the connector 11 as an extended function to perform higher-level printing. be able to. In the case of the printer main body 1, a font cartridge, in which fonts are stored, is described in an existing cartridge, such as one in which a program for interpreting a page description language is stored. In addition, a cartridge 3 with a built-in processor described later can be connected.

C. Configuration of Cartridge 3

FIG. 3 shows the external shape of the cartridge 3 of this embodiment. As shown in the figure, the cartridge 3 is to be mounted on a connector mounting portion 61 provided on the printer body 1, and its appearance is inserted into the connector mounting portion 61. The side of the printer body 1 has a rectangular parallelepiped shape, while the part of the printer body 1 Has become. When the cartridge 3 is inserted into the connector mounting part 61 and pushed in, the connector at the rear end of the cartridge 3 fits into the connector 11 and both are electrically connected. Is done. In this state, the step of the cartridge 3 is in a position almost in contact with the housing of the printer body 1. The front part of the cartridge 3 that protrudes out of the housing of the printer body 1 has an inclined upper surface, so that other articles cannot be inadvertently placed on it.

Next, the internal configuration of the cartridge 3 will be described. Figure 4 shows the internal configuration of the cartridge 3 as a block diagram. The cartridge 3 includes therein a CPU 71 which is a different processor from the CPU 31 of the electronic control unit 10 of the printer body 1. This CPU 71 is of a RISS type suitable for processing of a page description language and the like. The CPU 71 address bus CAD and control signal bus CCT switch the ROM 73 with a built-in page language processing program, the RAM 75 for storing data, etc., and the address path of the CPU 71. It is connected to a gate array 77, a serial I / O port (SIO) 78 for controlling communication, and a latch 79 for latching data. The output of the latch 79 is connected to the data input D of the first unidirectional buffer 87.

The S1078 is connected to the LAN connector 7 via the communication receiver 82 and the driver 84, and is exchanged by the control signal line directly connected to the connector 7. The control data is used to receive data for printing from another device connected to the local area network, for example, the workstation 9.

On the other hand, when the cartridge 3 is attached to the connector 11 of the printer body 1, the address bus P of the electronic control unit 10 is attached to the connector 90 of the cartridge 3. AD, read-only data bus PD, interrupt signal line IA, and signal line TB of timer 57 are connected. The address bus PAD is connected to the address decoder 80 and R0M86, and the data bus PD is connected to the first and second unidirectional buses and the data output side of the software 87 and 88. It is connected to the. The output of the first and second buffers 87 and 88 is controlled by a control signal from the address decoder 80. That is, if the address decoder 80 analyzes the address from the CPU 31 of the electronic control unit 10 and judges that the access is to the ROM 86, the address of the buffer 88 is determined. Navel edge The control signal is output to the child 0 E to enable the output of the buffer 88, while if it is determined that the access is to the latch 79, the control signal is output to the enable terminal 0 E of the buffer 87. To make the output valid. Therefore, either the contents of the ROM 86 or the data held in the latch 79 are output to the data path PD by the access from the CPU 31 of the electronic control unit 10.

As described above, since the contents of the ROM 86 can be read directly from the CPU 31, the cartridge 3 stores the control of the CPU 31 of the electronic control unit 10 in the ROM 86. Can be transferred to a program. Moreover, by executing the program, the CPU 31 in the cartridge 3 can directly read the data prepared in the RAM 75 by the CPU 31. This point will be further described.

D. Data transfer and expansion from connector 7

When the cartridge 3 is mounted on the printer body 1 and the power is turned on, the electronic control unit 10 performs a predetermined initialization process, and then performs a predetermined initialization process. Performs processing to read address data. This address is the address that was harmed to the cartridge slot, and if a cartridge is installed, the installed cartridge is The prepared data is read out according to the type (font cartridge or program cartridge). In the case of a program cartridge as in the case of the cartridge 3, the CPU 31 of the electronic control unit 10 recognizes this and controls the R on the cartridge 3 side. 0 Μ Move to 86. Specifically, it jumps to a specific address in the address area allocated to R0Μ86, and executes the program stored at the address and below.

On the other hand, after the power is turned on, the CPU 71 of the cartridge 3 receives data from the local area network by the interrupt processing based on the request from the SI 078 together with the processing shown in FIG. Processing is always being executed. The received data is sequentially stored in a predetermined area of the RAM 75, and is repeatedly executed until data indicating completion of a series of data transfer is received. Here, the data that the cartridge 3 receives from the workstation 9 or the like via the local area network is written in a page description language, for example, a postscript (by Adobe). Trademark) (Script). Completion of data transfer is defined as a command specific to these page description languages (for example, "SH0WPAGE" in postscript).

When detecting the completion of the data transfer, the CPU 71 activates the processing routine shown in FIG. 5, first stores predetermined data in the latch 79, and outputs an interrupt signal IA to perform electronic control. The device 10 is notified that there is data to be transferred (step S91). Electronic control device 10? 31 executes a program stored in the ROM 86, so that an interrupt processing program corresponding to the interrupt signal IA is supplied together with the cartridge 3. In the interrupt processing, an address corresponding to the latch 79 is accessed, and the data prepared by the CPU 71 is read. By analyzing this data, the CPU 31 of the electronic control unit 10 can know that the cartridge 3 is currently developing data in a page description language.

The CPU 71 interprets the script stored in the RAM 75 by using a page description language interpreting program (page description language interpreter) stored in the ROM 73, and generates an image image. A generation process is performed (step S92). The developed image image is stored in a predetermined area of the RAM 75. When the development of the image image is completed, the CPU 71 sets the predetermined data on the latch 79 again, outputs an interrupt signal IA, and outputs the CPU signal of the CPU 10 of the electronic control unit 10 again. 31 notifies the completion of the image image development (step S93). Subsequently, the process of transferring the image image to the electronic control unit 10 is started, and is continued until the transfer of all the image data is completed (steps S94 and S95). The transfer of image data is performed sequentially by setting the data in the latch 79 and outputting the interrupt signal IA.

When the transfer of all the image data is completed, the CPU 71 sets the data indicating the completion of the transfer of the image data to the latch 79 again and outputs the interrupt signal IA (step S96). N EXT ”to end this routine.

E. Function of electronic control unit 10

In response to the processing of the cartridge 3 described above, the electronic control unit 10 accesses the predetermined address every time it receives the interrupt signal IA, and the image held in the latch 79 is The image data is received one byte at a time, and this data is sequentially stored in a predetermined area of the DRAM 45. When the notification of completion of transfer of all the image data is received from the cartridge 3, the image data developed by the cartridge 3 is stored in the DRAM 45 of the electronic control unit 10. ing. Therefore, the electronic control unit 10 drives the zero graph 15 according to the image data, and performs a process of printing an image on the paper P. In this state, since the CPU 31 of the electronic control unit 10 is executing the program stored in the ROM 86 in the cartridge 3, the printer 1 is connected to the connector Normal processing for receiving data from the computer 5 via the printer 6 and performing printing cannot be performed.

F. Effects of the first embodiment

As described above, according to the printer main body 1 and the cartridge 3 of the present embodiment, the connector 11 provided in the electronic control unit 10 includes a processor suitable for image processing. the carts wearing the re Tsu di 3 having, moreover other equipment this carts Li Tsu di 3 connected to Rokarue Li Ane Tsu preparative work, workstation shea _s emissions 9 Karabe over di described in here It can receive scripts written in a language and print on paper P. Therefore, the following effects can be obtained.

(1) The cartridge 3 is provided with a CPU 71, and the CPU 71 interprets data received via the local area network to develop an image. Therefore, the processing capability of the page description language is significantly improved compared to the case where the processing program of the page description language is simply supplied by the cartridge 3. It is also possible to supply a higher-level page processing language in cartridge 3.

(2) Since the communication function is provided on the cartridge 3 side, it is possible to support communication protocols that the printer body 1 does not have. In this embodiment, the printer main body 1 can be used by connecting to an Ethernet which is not originally provided.

(3) The print trigger 3 directly receives the print data from the workstation 9, so there is no need to transfer the data from the printer body 1 to the cartridge 3. It can be used with existing printers that are not going to be equipped with a cartridge with a sensor. Facilities, including the ability to support new communication protocols Can be used effectively.

Normally, as the functions of the computer improve, the printer becomes the bottleneck of the system, so it is necessary to replace the entire printer with the improvement of the functions of the computer. In many cases, according to the present embodiment, in this case, it is only necessary to attach a cartridge having a high-performance processor to the printer main body 1, which is extremely advantageous in terms of cost. .

G. Modified Example of First Embodiment Part 1

In the above-described embodiment, communication with the local area network is performed by the ordinary S1078. However, a high-speed local area network or an interface that conforms to Centrox is used. If the data transfer becomes faster as in the case of parallel transfer, etc., the communication speed under management by the CPU 71 may not be able to catch up. FIG. 6 is a block diagram showing the configuration of the communication unit 200 that can also handle high-speed communication.

The configuration shown is for the Centronics-compliant interface X—the connector 210 has eight bits of data D1 through D8 and a strobe as input signals. The signal STB is connected to the busy signal BUSY and the error signals Err and Ρ as output signals.

The communication unit 200 includes a latch 211 holding data D1 to D8, and a FIF 0 memory 211 and FIF 0 for storing / reading data in a fast-in / fast-out order. A 16-bit 3-state buffer 217 with the 8-bit output of memory 2 15 connected to the lower 8 bits, and a link to these latches 21 2 It has a gate array 220 that outputs the read signals FR and FW to the touch signals LA and FIF 0 memory 2 15 and the control signal RB to the 3-state buffer 21 < The gate array 220 also outputs an output signal BUSY to the connector 210. From the FIF 0 memory 215, the signal FF indicating that the FIF 0 memory 215 is full is sent to the gate array 220, while the FIFO memory 215 is empty. The indicated signal FE is output to a predetermined upper bit of the 3-state buffer 217, respectively. The read side of FIF 0 memory 2 15 The CPU 71 outputs a predetermined address signal via the address bus PAD, so that data is read out and the 3-state buffer 21 7 Output is enabled. Therefore, the CPU 71 can read the data and the signal FE output from the FIF 0 memory 2 15 via the data bus CD.

The operation of the communication unit 200 will be described. The data sending side refers to the busy signal BUSY of the connector 7, stops the busy signal becoming inactive, outputs the data to be transferred, and outputs the timing when the data is established. To activate the strobe signal STB. When the stop signal STB input from the connector 7 is activated, the gate array 220 activates the latch signal LA and latches the data D1 to D8. After the latch signal LA is activated, a predetermined time after the latch signal LA is activated, the FIFO write signal FW is activated, and this data is stored in the FIFO memory 215. Write. When the writing of data to the FIFO memory 215 is completed in this way, the gate array 220 outputs a busy signal unless the FIFO memory 215 is full, that is, unless the signal FF is active. BUSY is inactive. In this way, data is transferred from the external device one after another.

On the other hand, the CPU 71 accesses the address assigned for reading the FIF0 memory 215 at a predetermined timing. Gate array 220 receives the address signal and activates FIFO read signal FR and buffer control signal RB. As a result, if data remains in the FIF 0 memory 2 15, it is read out and the output of the 3-state buffer 2 17 is enabled. At this time, via the data bus CD, the CPU 71 sets the data in the FIF 0 memory 215 to the lower 8 bits and sets the signal FE to the upper predetermined bit. Since data can be read, if data remains in FIF 0 memory 215, this is determined and the lower 8 bits may be stored in RAM 75 as data. The error signals E rr, PE, etc., which are the outputs of the gate array 220, are also assigned predetermined addresses as viewed from the CPU 71, so that these signals can be controlled as necessary. It is. According to the communication unit 200 described above, data transferred from an external device can be received at high speed. Moreover, since the FIFO memory 215 is used for data transfer, data transfer between the external device and the CPU 71 can be completely cut off. For example, the CPU 71 It is easy to perform complex processing such as receiving the next image script while developing. Note that if the operation of the FIFO memory 2 15 is sufficiently fast, the latch 2 12 can be omitted.

In this example, the communication unit 200 is realized by wire logic. However, as shown in FIG. 7, the communication unit 200 may be realized by using a one-chip micro computer 310 with a built-in ROM, RAM, and the like. Easy. In this case, the address signal PAD output from the CPU 71 is analyzed by the address decoder 312, and one of the outputs of the address decoder 312 is The other terminal is connected to the enable terminal of the data buffer 315, and the others are connected to the input terminals of the three sets of R / S flip-flops 317, 318, 319. The RZS flip-flops 317 to 319 are used for controlling the busy signal BUSY and the error signals Err and PE, respectively.

In this configuration, one chip microprocessor 310 combines the functions of the gate array 220, the latch 212, and the FIF 0 memory 215 of the communication unit 200 shown in FIG. It takes in the signal from the connector 330 connected to its input port, and converts this data into a 3-state data according to the address signal PAD and control signal CCT given by the CPU 71. The data is output to the data bus CD via the file 315. The signal FE indicating that the communication data is valid is output to a specific upper bit of the data output to the data bus CD, and the lower 8 bits at that time are valid data as shown in FIG. The configuration is the same. It should be noted that a configuration may be adopted in which 2-byte data is synthesized inside the one-chip micro-channel opening sensor and output as one-word data.

H. Modification Example 1 of First Embodiment Part 2

Next, another modified example of the present embodiment will be described. In this example, in addition to the configurations shown in FIGS. 1 to 4, the display configuration (display section 400) shown in FIG. It incorporates The display section 400 includes a dual-port memory 410, a display control device 420, and a liquid crystal display 430. The dual-port memory 410 replaces part or all of the RAM 75 in the configuration of FIG. 6, and is used for storing image memory. The CPU 71 interprets the image data generated and interpreted according to the page description language interface, and outputs necessary signals via an address bus CAD, a data bus CD, and a control signal bus CCT to form a dual port. Store in a predetermined area of memory 410.

The display control device 420 outputs an address signal IA for reading data serially from the dual port memory 410, and outputs serial data output from the dual port memory 410. The ID is input, converted to a video signal VD, and output to the liquid crystal display 430 together with the synchronization signal SYF. Instead of the liquid crystal display 430, various types of display devices such as an EL panel, a plasma display, and a small CRT can be used.

In this configuration, the cartridge 3 is provided with the liquid crystal display 430 so that the image data generated by the CPU 71 can be checked before printing using the printer body 1. Therefore, before printing on paper P, it is possible to check the image to be printed from now on, and if it is possible to cancel the printing at that point in time, if there is a wasteful mistake due to the description mistake of the page description language, etc. Printing of images can be prevented. Note that a small thermal transfer printer or the like can be used as the display device. In this case, it is possible to obtain an overview of the image by printing at a high density at a high speed before printing the fine image by the printer body 1.

Since a display device for displaying a video signal is widely used in the world, it is preferable to adopt a configuration including a connector for outputting a video signal to the outside. In this case, the display of the cartridge 3 can be omitted. Further, it is conceivable that the image data read by the display control device 420 from the memory 410 is output to an external computer using a communication line or directly, and is displayed on the display device.

[ii] Second embodiment A. Description of overall configuration

Next, a second embodiment of the present invention will be described. In this embodiment, a laser printer 500 as an electronic device is combined with a cartridge 503 as an additional control device. FIGS. 9 and 10 are perspective views respectively showing a state where the cartridge 503 is inserted into the first and second types of printer main bodies 500a and 500b. In the following description, the printer body is simply referred to as a laser printer 500. The cartridge 503 is provided with a connector 508, and print data from an external workstation 507 is directly input to the cartridge 503. The laser printer 500 uses a zero graph unit similarly to the printer main body of the first embodiment. As shown in FIG. 11, a portion where printing is performed using a photosensitive drum is a laser engine 505. And independent. The electronic control unit 501, which controls the entire laser printer 500, sends commands to the laser engine 505 via the connector CN10 and transfers image data to a predetermined buffer to perform printing. You can do it.

As shown in the figure, a well-known CPU (MC 68000 manufactured by Motorola in the present embodiment) 510 and a ROM 501 storing programs to be executed by the CPU 501 are provided inside the electronic control unit 501 as shown in the figure. 1, RAM 5 12 for storing print data and image data after expansion, and data input port 5 14 for receiving print data from external equipment in the configuration without cartridge 503, cartridge 5 Register for exchanging command and status information with the line buffer 515 interposed on the bus line 516 for exchanging data with the 503 and the laser engine 505 517, Console panel for laser printer 500 Console panel for controlling interface with 518 IZF 519, Double buffer circuit for storing image data to be transferred to laser engine 505 520. Since the configuration of the bus line and the configuration of the control line are the same as those of the first embodiment, they are simply illustrated.

The console panel 518 has six operation switches 518a operated by the user and a liquid crystal display 518b capable of displaying 16 characters (8 characters x 2 lines). It is provided.

The double buffer circuit 520 has eight lines for printing by the laser engine 505, In other words, two RAMs 520 A and 520 B having a storage capacity of 4 Kbytes are provided, and image data is alternately sent from the CPU 510 through the memory writing controller 520 C. Write. On the other hand, the laser engine 505 alternately reads out the two RAMs 520A and 520B via the memory readout controller 520D, so that the image data is video-synchronized with the rotation of the photosensitive drum. It can be converted to signals and printed. The reason why the two RAMs 520A and 520B are provided to write and read data alternately is that access from the CPU 510 and access from the laser engine 505 side must be performed independently.

After writing data to one RAM, the CPU 510 flags a predetermined bit of the register 517. In response, the laser engine 505 checks this flag and reads out the image data stored in the RAM on which the data is written. During a read, another bit is set in register 517 to inform CPU 510 which RAM is being read. At this time, since the other RAM is not accessed from the laser engine 505, the CPU 510 writes the next eight lines of image data into the other RAM during this time. When reading from one of the RAMs is completed, the laser engine 505 resets the flag and switches to reading from the other RAM. The speed at which data is written from the CPU 510 is faster than the speed at which data is read from the laser engine 505, ie, the speed at which printing is performed. The transfer of image data for the page and evening is reliably and easily realized.

A cartridge 503 is mounted on the connector CN 11 of the electronic control device 501. The relationship between the laser printer 500 and the cartridge 503 mounted thereon is the same as in the first embodiment. It is determined whether or not it is mounted on connector CN11, and if it is determined that it is mounted, reset the inside of electronic control unit 501, etc. Jump to a predetermined address of the ROM (described later) prepared in the 503, and thereafter execute the processes prepared in the cartridge 503 in order. The cartridge 503 interprets the program written in the page description language output from the workstation 507, converts the program into image data, transfers the image data to the electronic control unit 501, and transmits the image data to the laser engine. The point that printing is performed by 505 is the same as in the first embodiment. B. Cartridge structure

FIG. 12 is a perspective view showing the structure of a printer cartridge according to one embodiment of the present invention, and FIG. 13 is an exploded perspective view thereof. The cartridge 503 is designed as a cartridge to be inserted into the font cartridge insertion slot of the printer body. However, the cartridge 503 is provided with a connector 508 on the side opposite to the side where the cartridge is inserted into the cartridge insertion slot, and print data is directly transmitted from the workstation 507 connected to the connector 508. It has a function of receiving print data and expanding the received print data into image data.

The cartridge 503 is a multilayer printed circuit board 550 (hereinafter simply referred to as a “printed board”) between an upper case 100 having a concave interior and a lower case 120 having a plate shape. The lower cap 140 and the upper cap 150 are attached to the connector side of the cartridge 503. The upper case 100, the upper cap 140 and the lower cap 150 are made of ABS resin, and the lower case 120 is made of aluminum. A conductive layer is formed on the inner surface of upper case 100, and forms a frame ground together with lower case 120. The conductive layer on the inner surface of the upper case 100 is formed by electroless copper / metal plating. The conductive layer may be formed by using other well-known methods such as coating of a conductive paint and vacuum deposition of aluminum. Also, the upper case 100 may be manufactured by molding a conductive plastic.

In the following, the side with the caps 140 and 150 is called the front of the cartridge, and the side with the microprocessor 601 is called the back of the cartridge.

A plug portion 551 is formed in front of the printed circuit board 550, and a circuit element such as a microprocessor 601 is mounted behind. Four ground panel members 104 are fixed to the periphery of the printed circuit board 550, two of which are located at the center of the cartridge in the insertion direction, and the other two are attached to the cartridge. It is provided behind the lid. Panel member 104 has a role of electrically connecting the ground wiring of print substrate 550 to the conductive layer on the inner surface of upper case 100. On the front side of the lower case 120, two earth panel members 122 for securing an earth connection with the printer body are fixed. The grounding panel member 122 has a shape in which a bird spreads its wings, and the first bent portion 122a corresponding to the left and right wing portions is bent upward and corresponds to a bird leg portion. The second bent portion is bent downward in a semi-arc shape. The first bent portion 122a has a role of electrically connecting the lower case 120 and the ground wiring of the printed board 550. The second bent portion projects out of the cartridge 503 from the opening 132 provided in the lower case 120, and electrically connects the ground portion of the printer body to the lower case 120. Has the role of

A fitting portion 124 having a wall shape protruding from the flat plate portion 121 is provided on a peripheral edge of the lower case 120. The fitting portion 124 is fitted to the side surface of the upper case 100 to form a main structure of a substantially rectangular parallelepiped housing.

Behind the lower case 120, a cylindrical pressing silicone rubber 126 for pressing the printed circuit board 550 upward is fitted into a rubber holding portion 128 on the inner surface of the lower case. The pressing silicone rubber 126 has a role of pressing the print substrate 550 directly below the microprocessor 601 upward. Between the upper surface of the microprocessor 60 1 and the inner surface of the upper case 100, a sheet-like heat-dissipating silicone rubber 102 is inserted to improve the adhesion and thermal conductivity. Be mounted. Further, an aluminum heat sink 110 is fixed to the lower case 120 with screws so as to cover the upper part of the micro processor 601. When the pressing silicone rubber 126 presses the printed circuit board 550 upward, the micro processor 601 is also pressed upward, and the micro processor 601 and the heat radiating silicone are pressed. The adhesiveness between the corn rubber 102 and the radiating silicon rubber 102 and the radiating plate 110 is increased. As a result, the heat generated in the micro-channel sensor 601 is conducted to the lower case 120 via the heat sink 110, and is radiated to the outside from the lower case 120.

At the time of assembly, first, two ground panel members 122 are fixed to the lower case 120, and then the pressing silicone rubber 126 is fitted into the rubber holding portion 128. On the other hand, various circuit elements are mounted on the printed circuit board 550, and four grounding panel members 104 are inserted into predetermined holes of the printed circuit board 550, and each of them is soldered. Fix with. Next, the printed circuit board 550 is placed on the lower case 120, and the rear side (micro Secure the corners of processor 60 1) with screws. Then, the heat sink 110 is fixed to the # 1 surface of the fitting portion 124 of the lower case 120 with a screw. Then, the upper case 100 is fitted to the lower case 120, and the lower cap 140 is inserted. At this time, the through holes 1 41 of the two screws provided in the lower cap 140 are inserted under the corresponding portions of the upper case 100, and the through holes 1 of the lower cap 140 are inserted. The plug portion 55 1 penetrates through 42. The upper case 100 is fixed with screws at three places on the front side. Finally, by inserting the upper cap 150 into the upper case 100, a cartridge 503 as shown in FIG. 1 is completed.

In addition, on both sides of the upper cap 150 are provided button openings 154 each containing a spring 152 therein. The button lock 154 is urged outward by the panel 154.When the two button locks 154 are pressed inward, the button lock 154 engages with the upper case When the button lock 154 is released, it engages with the engaging part.

Figure 13 also shows the IC card 502. The IC card 502 is an extension memory having a large number of dynamic RAMs, and can be inserted into the cartridge 503 as needed. When inserting the IC card 502, first remove the upper cap 150, and insert the IC card 502 into the expansion memory slot 106 provided in the upper case 100. As a result, the IC card 502 is inserted into the IC card connector 210 in the print substrate 550. When the upper cap 150 is attached, it returns to the original shape shown in FIG. In this embodiment, since the removable upper cap 150 is removed so that the IC card 502 can be inserted, the memory can be easily expanded. Also, by providing the upper cap 150 in front of the cartridge 503, the IC card 502 cannot be inserted when the cartridge 503 is inserted into the laser printer body. It is ingenious.

FIG. 14 is a perspective view showing the print substrate 550 in an enlarged manner. As shown in the figure, a connector 508 is attached to the rear end of the upper surface of the printed circuit board 550 so as to be adjacent to the micro processor 601, and the other end is connected to the connector of the printer main body. An insertion plug portion 551 for connection is formed. Around the microprocessor 601, four ROMs 606 to 609, which store control programs for the microprocessor 601, etc., four address buffers 61, 17, and a clock Oscillators 66 1 and 665 are arranged respectively. Further, an IC card connector 502a is provided slightly forward from the center of the print substrate 550. On the back side of the printed circuit board 550, an ASIC (application-specific LSI) including a control circuit and a register, and an R0M (process memory) that stores the processing program for the processor in the print body Hereafter, various circuit elements are mounted. Note that, for convenience of illustration, the wiring pattern formed on the surface of the print substrate 550 is omitted.

The microprocessor 601 is a device of the type of a pin grid array (PGA), and the others are devices of the SOJ type, the SOP type or the QFP type. As the microphone opening processor 601, for example, Am 29030 (clock frequency 25 MHz) manufactured by AMD, which is a RISC processor, is used.

As described above, the cartridge 503 is inserted into the font cartridge insertion slot of the printer body. A normal font cartridge is simply a type that contains a ROM that stores font data. On the other hand, the cartridge 503 of this embodiment includes a microprocessor 601 and ROMs 606 to 609 storing a processing program of the microprocessor 601. It is characterized by having a ROM for the printer body, a control circuit including an AS IC, and a communication circuit. Details of the communication circuit will be described later.

The connector on the printer main body side into which the cartridge 503 is inserted is configured to be connected to the font cartridge, so data is stored in the cartridge. A read-only line is provided to read data from the printer to the printer main unit, but there is no signal line for transferring data from the printer to the cartridge. On the other hand, in the cartridge 503 of this embodiment, the print data is received from the external workstation 507 via the connector 508, and the print data is received by the microprocessor 601. The data is expanded to data and transferred to the electronic control unit 501 of the printer main unit, but has a function of receiving some data from the electronic control unit 501 as well. At this time, specific data is printed using the read-only line of the connector. It is necessary to transfer the data from the main unit to the cartridge. For this reason, special processing is performed by the micro processor of the main unit as shown below.

If the cartridge 503 is inserted into the printer, the processor inside the printer will start the printer when the printer starts up, and the identification data stored in the printer ROM in the cartridge 503. The CPU 510 in the printer main body performs processing according to the processing program in the printer main body ROM 606 to 609 in accordance with the identification data.

The CPU 510 in the main body of the printer executes a special process according to the processing program in the ROM 606 to 609 for the main body of the printer. This special processing is to generate an address that substantially contains data for one hundred and one address, put this address on the address path, and print the cartridge from the printer body. This is the process of notifying the 503. The power ASIC receives the address and decodes it to extract one word of data contained in the address. In the specified RAM (described later). The microprocessor 601 can know various information of the electronic control device 501 based on the data stored in the RAM. For example, the operation information of the console panel 518 needs to be known by the microprocessor 601 of the cartridge 503, and by receiving such data, the cartridge 503 becomes necessary. Processing can be performed. As the microprocessor 601, it is preferable to use a processor that is faster than the printer itself. In this way, the image processing to be executed by the printer main body is performed by the high-speed micro processor 601, so that the processing speed of the printer can be substantially improved. The circuit in the cartridge 503 and details of its operation will be further described later.

As described above, the cartridge of this embodiment has the following measures against electromagnetic noise.

(1) A conductive layer was formed on the inner surface of the upper case 100 made of plastic, and the lower case 120 was made of aluminum. As a result, a conductive layer is formed over the entire inner surface of the housing of the cartridge, and electromagnetic noise is blocked.

(2) A wall-shaped fitting portion 124 is provided on the periphery of the lower case 120, and the upper case 100 Was fitted. As a result, the outer peripheral surface of the fitting portion 124 and the conductive layer on the inner surface of the upper case 100 were overlapped to prevent electromagnetic noise.

(3) The signal ground and the frame ground were grounded at multiple points, the impedance between them was reduced, and the generation of high-frequency current was suppressed.

において Near the through hole 142 for the plug 551, the signal ground and frame ground are connected at both ends and the center of the plug 551, and are emitted from the through hole 142. The wavelength of the electromagnetic noise was reduced (the frequency was increased). This has reduced electromagnetic noise in harmful wavelength ranges that are subject to regulation.

The cartridge 503 also uses the following general measures against electromagnetic noise.

(4) A decoupling capacitor was installed near the GND pin and power supply pin of each circuit element.

コモン A common mode choke coil was installed in the power supply wiring of the micro processor 601. Finally, the connection structure between the plug 551 and the connector CN 11 is shown as the structure of the cartridge. The plug portion 551 has 25 terminals formed on two surfaces (surfaces A and B) of the double-sided printed circuit board, respectively. FIG. 15 shows signal names corresponding to each terminal of the plug section 55 1. Note that the symbol r / j added before the signal name indicates that the signal is low-active. The meaning of each signal is as follows.

Signal / AS B: Address strobe signal output from CPU 510 (MC 68000 manufactured by Motorola).

Signal ZUDS: Upper data strobe signal output by CPU510.

Signal ZLDS: Lower data strobe signal output by CPU510.

Signal ZAD S: Address strobe signal / AS in electronic control unit 501

Address strobe auxiliary signal generated based on B. The address strobe auxiliary signal ZADS behaves differently for different types of printers when the printer is started (initialized). Signal ZOD TAC K: An output signal for transferring data from the cartridge 503 to the electronic control unit 501 side.

Signal / CTR GSEL: The cartridge selection when the CPU 510 selects the cartridge 503 and accesses the ROM 56, register, etc. allocated to the internal address space. Signal.

Signals A1 to A20: Address signals output by CPU510.

Signals D1 to D15: Output signals from the cartridge 503 side.

Signal RZW: Read / write signal output by CPU510.

Signal SCLK: Clock signal output from an oscillator (not shown) built into laser printer 500.

Note that the signal / CTRGS applied to the laser printer 500 is lowered to the L level when the cartridge 503 is inserted, and the CPU 510 causes the cartridge 503 to Detects that it is inserted into connector CN11.

The CPU 510 specifies the word address using the 23-bit address signals A1 to A23, and uses the signals / UDS and / LDS to specify the upper byte and lower byte of each word. Specify the As a result, the CPU 510 can handle a 16-Mbyte address space from OOOOOOOH to FFFFFFh. Here, the symbol "h" added after the address indicates that the value is represented in hexadecimal.

C. Cartridge address space

The cartridge 503 is allocated to a part of an address space handled by the CPU 510 of the electronic control device 501. The CPU 510 is capable of handling a 16 Mbyte address space from OOOOO Oh to FFFFF Fh; a part of it is allocated for ROM cartridges. The space allocated to the cartridge 503 depends on the model of the laser printer, but it does not depend on the laser printer. In the case of a laser printer manufactured by Auckard Co., Ltd., as shown in the left column of FIG. 16, a 2 MB space such as 200,000h to 3FFFF Fh or 40,000 Oh to 5FFFFFh is usually used. The microprocessor 601 installed inside the example power trigger 503 is AMD 29030—25 MHz manufactured by AMD, and the addressable The space is 4G bytes from OOOOOOO Oh to FFFFFFF Fh. In this address space, not only R0M and RAM but also various registers and the like used for exchanging data with the electronic control device 501 on the printer side are allocated. This is shown in Figure 16. Hereinafter, the electrical configuration inside the cartridge 503 will be described together with the allocation of the address space for both microprocessors.

Fig. 18 shows the internal configuration of the cartridge 503. As shown in the figure, the cartridge 503 is mainly composed of a micro processor 601 which controls the entire system, and is roughly divided into a memory section 602 comprising ROM, RAM and its peripheral circuits. A data transfer control unit 603 that controls all data exchange with the electronic control unit 501; a communication control unit 604 that performs data communication with an external workstation 507; and other circuits. ing.

The memory unit 602 includes a 2M-Pit ROM 606 to 609 for storing a program to be executed by the micro processor 601 and a selector 6 for using the ROM 606 to 609 for puncturing switching. 10, 2M bytes of RAM 61 1 to 61 4 for storing print data received from the electronic control unit 501 and for storing image data after expansion. RMBs 606 to 609 of 2M bytes are mask ROMs of 16 bits x 256kg = 4M bits each, and are assigned to 001 FFFF Fh from OOOOOOO Oh in the address space as shown in Figure 17 Have been. The ROMs 606 and 607 and the ROMs 608 and 609 each constitute a bank, and one set of two banks constitutes a 32-bit data pass each. The ROMs 606 to 609 and the microprocessor 601 are connected by an address bus AAB and a control signal bus. Further, the data bus IDB of the ROM 606 to 609 is connected to the data bus DB 29 via the data selector 610, through which the microprocessor 601 can read data from the ROM 606 to 609. It can be.

ROM 606 and 607s ROMs 608 and 609 have the least significant three bits (AO, A1, A2) of address bus AAB from microprocessor 601. All address signals except for are input. Since the least significant two bits (A0, A1) are not input, data is read from the microprocessor 601 in units of 1 word = 32 bits (in units of 4 bytes) It depends. In addition, since the address A2 is not assigned, when reading data in a predetermined area, the four ROMs 606 to 609 output data at the same time. The data selector 610 adjusts the data output at the same time. In other words, access to ROM from the microprocessor 601 is often performed at consecutive addresses, so that 32 bits are used as one word and two consecutive words are used once. The data is read from ROMs 606 to 609 at the same time, and if the data is actually read continuously, the bank to which the ROM belongs is sequentially switched by the data selector 610 and the data is read continuously. is there. As a result, data reading for two consecutive words is extremely fast.

On the other hand, RAMs 61 1 to 614 are 16 bits x 256 kilos = 4M bits of DRAM, and as shown in Figure 17, 2M bytes of address space from 20000000h to 201 FFFF Fh Have been assigned. In the cartridge 503, an additional 2 Mbytes of memory can be added, and an extended RAM interface 615 is provided for this purpose. The extended RAM interface 615 is allocated from 20200000h to 203FFFFFFh in the address space. In the extended RAM interface use 6 15, a maximum of 2 Mbytes of IC card type RAM can be installed via the IC card connector 502 a. The data lines of the RAM 61 1 to 61 4 and the extended RAM interface 615 are directly connected to the data bus DB 29 of the microprocessor 601, and the address lines control the data transfer. It is connected to the address bus AAB of the micro processor 601 via the unit 603. The I / O of various registers, etc., described later, is allocated from 80000000h in the address space.

Next, the configuration of the communication control unit 604 will be described.

As shown in FIG. 19, the communication control unit 604 mainly includes a communication control LSI 604a, and is connected between the data bus DB29 and the data terminals D0 to D7 of the communication control LSI 604a. Mounted bi-directional buffer 604b, micro-processor The controller 604c, which controls the timing of data transfer with the server 601, and the line buffers 604e, f, and the 25MHz operation clock connected to the communication input / output of the communication control LSI 604a. From the D-type flip-flop 604 h that generates the operation clock PCLK of the communication control LSI by dividing the clock CLK, and the crystal oscillator 604 i that generates the basic clock RTXCA for communication It is configured.

The communication control LSI 604a is 85C30 manufactured by Zilog. For communication control combined with the line buffer 604e, refer to Zilog ΤΜ 8000ΤΜ Family Data Book Nov. 1 988 ”on page 222 and below, so a detailed description is omitted here. The controller 604c is configured using a programmable logic array, receives a signal from the micro processor 61 as an input signal, and controls the communication control LSI 604a and the bidirectional buffer 604c. The control signal to b is an output signal. The controller 604c receives, as input signals, address signals A11 and A31 from the address bus AAB and a request signal for the memory space to which the communication control unit 604 is assigned. / REQ, read / write signal R / W for instructing read / write to memory, reset signal / RESET for communication control unit 604, operation clock CLK of 25 MHz are input. The output signals include an output direction instruction signal for the bidirectional buffer 604b, an enable signal ZC E for the bidirectional buffer 604b and the communication control LSI 604a, and a communication control LSI 604. A read signal / RD for a, a write signal / WR similarly, and a ready signal RDY to the microprocessor 601 are generated. The ready signal RDY of the communication control unit 604 is logically ORed with the ready signal of another circuit by the NOR gate 6 16, and this is taken as the ready signal ZR DY and the micro processor 60 1 Is output to The ready signal is a signal for notifying the micro processor 601 that the communication control unit 604 has established data on the data bus DB 29 in response to access from the micro processor 601.

Note that the address signal A3 of the address path AAB is used as a signal AZB that specifies the two-channel communication port built in the communication control LSI 604a, and is also used as the address signal A3. The dress A2 is used as a signal C / D indicating whether the data on the data bus is communication data or a command to the 85C30. these As shown in Fig. 17, four addresses are set for every 4 bytes from 80000800h, as shown in Fig.17. Among them, the register SCCCTLB is a control register on the B channel side of the communication control LSI 604a, and the register SCCDABT is a data register for the B channel. The register SCCCT LA is a control register on the A channel side of the communication control LS1604a, and the register SCCDATA is a data register for the B channel. Each of the channels A and B is internally treated as a plurality of registers by the data written in the control registers SCCCT LA and B, and the data registers SCC DATA and B is treated as both an input and output data register according to the value written to the control register.

In the communication control unit 604, one byte of data is output from the microprocessor 601 to the data path DB 29, and when the output port of the channel A is designated and a write operation is performed, the bidirectional communication is performed. This data is received via the buffer 604b, and is output to the outside via the line buffer 604f as serial data. On the other hand, when serial data is received from the outside via the line buffer 604 e, a read operation in which the input port of the A channel is specified from the microprocessor 601 is received. Then, the received data is output as a parallel signal to the data bus DB 29 via the bidirectional buffer 604b.

The print data transferred from the external work station 507 by the communication control block 604 is stored in a predetermined area of the RAM 611 to 614 of the data transfer control unit 603, and is processed by the microprocessor 601. wait. When receiving all print data to be developed from the electronic control unit 501 side, the micro processor 601 starts the program stored in the ROM 606 to 609, and executes a predetermined process in the RAM 611 to 614. The print data stored in the area is processed. The image is developed by such processing, and the developed result is stored as image data in a predetermined area of the RAMs 611 to 614.

Next, the relationship between R 0 M in the cartridge 503 and the electronic control unit 501 will be described. The cartridge 503 of this embodiment is connected to the electronic control unit 50 of the printer 500. When viewed from one side, as shown in the right column of FIG. 16, the first 512 Kbytes are assigned a ROM (ROM6 18 shown in FIG. 18): ^. That is, the cartridge 503 also includes a program executed by the CPU 501 of the electronic control device 501, and the CPU 510 of the electronic control device 501 includes the cartridge 503. If is mounted, after the initialization processing is completed, a jump instruction to a predetermined address of the ROM 618 is executed. Thereafter, the CPU 510 operates according to the processing procedure stored in the ROM 618.

When the CPU 510 accesses the 512 MB space from the beginning of this 2 MB space allocated to the cartridge 503, the cartridge 503's connector evening address bus The ROM 618 is accessed by an address signal output via the address buffer 617 provided in the CAB, and the instructions and data stored in the ROM 618 are transferred to the data bus CDB on the connector side. The data is sent to the CPU 510 of the electronic control unit 501 via the data buffer 610 provided in the CPU. In FIGS. 16 and 17, “X” indicates the value of the four most significant bits of the head address of the allocated space.

E. Explanation of data transfer control unit 603

In the address maps shown in Figs. 16 and 17, addresses other than those to which R0M and RAM are assigned contain various control registers and status registers. I have. Since these registers are realized by the data transfer control unit 603, the data transfer control unit 603 will be described next. Although the explanation of the circuit is the main, refer to the address map (Figs. 16 and 17) as appropriate. The data transfer control unit 603 shown in FIG. 18 is an ASIC realized by a gate array having about 29,000 gates. This device is a gate array of model number SLA929S, manufactured by Seiko Epson, and is a low power consumption device made by the CMOS process. The data transfer control unit 603 was designed using a CAD system ASIC design system “LAD SNET” manufactured by Secepson. This CAD system uses a library of elements such as latches, flip-flops, counters, and programmable logic arrays used in logic circuit design. After the necessary logic circuit is designed using these, patterns for AS IC can be automatically generated.

The data transfer control unit 603 implemented as an AS IC includes a cartridge 503 mounted on the connector CN 11 of the printer 500 and a CPU of the electronic control unit 501 of the printer 500. It controls data exchange between the microprocessor 501 and the microprocessor 601 of the cartridge 503. Data exchange between the two is performed by a read control circuit 620 for transmitting data from the electronic control device 501 to the cartridge 503 via a read-only data bus, as in the FIFO memory. This is realized by a FIFO control circuit 623 that transfers data via the 621 and a double-bank control circuit 624 that enables data prepared by the cartridge 503 to be read from the electronic control device 501 side. Note that the FIF0 memory 621 is a RAM for storing and reading data in a fast-in-first-out procedure, and in this embodiment, HM 63921 manufactured by Hitachi, Ltd. was used. It is also possible to use other FIFO memories such as Mitsubishi Electric M66 252 FP.

The data transfer control unit 603 has an address bus CAB as a signal line with the electronic control unit 501 via an address buffer 6 17, and a data bus CDB with a data buffer. Each is connected via 6 19. The data transfer control unit 603 receives the signal of the address bus CAB and the signal CSEL of the cartridge select, and outputs a selection signal to each unit in the data transfer control unit 603. 631 are configured. Similarly, the address bus AAB and the control signal CCC from the micro processor 601 are also connected to the data transfer control section 603, and the address path is provided in the data transfer control section 603. A second decoder 632 that receives the AAB and outputs a selection signal to each internal circuit is configured. Further, upon receiving the address path AAB and the control signal CCC, the address is transferred to the ROM 606 to 609, the RAM 611 to 614 and the extended RAM interface 615. A bus control unit 635 that outputs signals and control signals is also configured.

In addition to these, various registers are configured in the data transfer control unit 603, and reading and writing to the registers are performed by a special read / write operation in addition to the normal read / write operation. Not a few are automatically written when certain processing is performed. The configuration of these special registers will be described later. In addition, since the cartridge 503 is treated as a read-only device when viewed from the electronic control device 501 side, a register that can be written from the electronic control device 501 side is a predetermined register. The data is written by reading from the address. That is, by specifying a predetermined address, a selection signal is output from the first decoder 631, and data is written to the register by this signal. Reading from the register is performed in a normal read cycle. From the microprocessor 601 side, data read / write is performed by a normal read / write operation. In Figure 18, the registers are depicted connected to a readable bus, and write operations are indicated by simple arrows. Such registers include an interrupt request register 640, a polling and command register (Figure 16, POLL) 643, and a status register (Figure 16). Register ST ATUS) 645, transfer flag register (Figure 17 B Register) 647, PROM control register 649, and control register 650.

Of these registers, the registers except the status register 645 and the transfer flag register 647 are the CPU 510 or the cartridge 503 of the electronic control unit 501. This is a general term for a plurality of registers allocated as memory-mapped I / O to the micro processor 601. Multiple registers are not necessarily assigned to contiguous addresses. The interrupt request register 640 includes the registers AMDINTO, 1,2 and the register AMDCLO, 1,2 shown in FIGS. Further, the polling command register 643 includes a register POLL and a register MCONTCS. To the PROM control register 649, registers EEPSCS, EEPSK, and EEPDI belong.

The control register 650 is a register that does not belong to the read control circuit 620, the FIFO control circuit 623, or the double bank control circuit 624, and all registers not mentioned in the above description belong to the control register 650. These are the registers ADDMUX A, ADDMUXB, CLKDIV, RTCCAL, RTCON, and RTCSEL shown in FIGS. 16 and 17.

In addition, of the memory map shown in Figure 16, the area WR 0 and EWWR 1 are areas used for writing from the electronic control unit 501 side to the first and second word latches 65 1 and 652 of the read control circuit 620, respectively. The registers EWRD O and EWRD 1 shown in the map correspond to the latches 65 1 and 652 as viewed from the side of the micro processor 601 with 1 as each mode. The register FIF OR ST, FIF OWR corresponds to the FIFO register 653 of the FIFO control circuit 623, and the registers FIRC LK, FIF 0 RD correspond to the FIFO read register 655 of the FIF 0 control circuit 623. The FIFO control circuit 623 also includes a latch 657 for holding data to be written to the FIF 0 memory 621.

The area indicated by the symbols D PRAMA and DP RAMB in FIG. 16 is a buffer having a capacity of 256 bytes (128 words), and the first and second buffers of the double bank control circuit 624. The keys 658 and 659 correspond to those viewed from the electronic control unit 501 side. The punctures DPWROA and DPWROB shown in Fig. 17 are seen from the microprocessor 601 side of the buffers 658 and 659. The predetermined bits d1 and d2 of the status register 645 are also used for data exchange via the double bank control circuit 624, the details of which will be described later.

F. Each Regis Evening Explanation

The interrupt request register 640 is a register that generates a request for an interrupt from the electronic control unit 501 to the microprocessor 601, and holds the request. There are three levels of interrupts from the electronic control unit 501 to the microprocessor 601. As shown in Fig. 16, three registers (AMD INT 0, 1, 2) are provided. Yes <By reading any of the interrupt request registers 640 from the electronic control unit 501 side, an interrupt request to the micro processor 601 is generated. The setting of this register is performed by a read operation from the electronic control unit 501, but the data to be read has no meaning and is not related to the generation of the interrupt request.

FIG. 20 shows a specific configuration example of the interrupt request register 640. This register consists of three D-type flip-flops. Each flip-flop is hereinafter referred to as an interrupt request register 640a, b, or c. The output terminals Q of the interrupt request registers 640 a, b, and c are set to the active blow by the signals ZAMD INT 0, 1, and 2 output from the first decoder 631 by the register reading operation. Set and the interrupt signals / INTO, 1, 2 are output. The registers that clear the outputs of these interrupt request registers 640a, b, and c are, as shown in Figure 17, three read-only registers (AMD CLRO, 1, 2). Assigned to a given address. Therefore, when a read operation is performed from the microprocessor 601 to each address to which this register is assigned, the second decoder 632 outputs signals / INTC LR 0, 1, 2 respectively, The flip flops that are activated are preset.

When an interrupt request is issued from the electronic control unit 501, any one of the interrupt request registers 640 may be accessed, and the micro processor 601 determines the priority and determines the interrupt request. Perform processing corresponding to. In this case, the microprocessor 601 clears the corresponding interrupt request register 640a, b, c. Note that a signal starting with the symbol “P UP”, such as the signal P UP 2, is a signal output from the reset signal output circuit 637 and is a signal that goes low at the time of reset or the like. Signal PUP 2 shown in FIG. 18 is a signal for clearing three interrupt requests at once.

The polling command register 643 is a register that transfers a command from the microprocessor 601 to the electronic control unit 501, and is writable from the microprocessor 601 and is an electronic control unit. 50 Register evening that can be read from the 1st side. Figure 21 shows an example of the configuration of this register on the hard disk. As shown, the polling command register 643 comprises two octal D-type flip-flops 643a, b, and 1 that form a 16-bit wide data latch. D-type flip-flops 643c.

The data bus DB 29 (bus width 16 bits) from the micro processor 601 is connected to the data input terminals 1 D to 8 D of the octal D-type flip-flops 643 a and b. The output terminals 1Q to 8Q are connected to a data bus DB 68 (path width 16 bits) from the electronic control unit 501 side. The access to the polling command register 643 from the micro processor 601 side is connected to the clock terminal CK of the D-shaped flip-flop 643 a, b. 1 6, Regis The data output from the second decoder 632 at the time of data transfer (MC ONT CS) is connected, and when this signal becomes active, the data bus DB 29 on the side of the micro processor 60 1 Is latched in the octal D-type flip-flops 643a and 643b. In addition, the output enable terminal OE that enables the output of the octal D-type flip-flop 643 a and b is provided with a polling command register from the electronic control unit 501 side. The signal / P0LL output from the first decoder 631 is connected at the time of accessing 643 (Fig. 16, register POLL), and when this signal becomes low active, an octal D-type signal is output. The data held in the flip-flops 643 a and b are output to the data bus DB 68 of the electronic control unit 501.

The signal / MC 0 NTCS and the signal / P 0 LL are connected to the clock terminal C and the preset terminal PR of the D-type flip-flop 643c, and the output terminal The signal CMD RD from Q is set to a high level when data is latched by octal D-type flip-flops 643 a and b (signal ZMC 0NT CS is low). When this data is read from the electronic control unit 501 (the signal ZPLL is low), it is reset to a low level. CMDRD, which is the output signal of the D-type flip-flop 643c, is a predetermined bit d3 (hereinafter, also referred to as a flag CMDRD) of the status register 645 that can be read from the electronic control unit 501 side. It is. Therefore, by reading the status register 645 from the electronic control unit 501 side, the electronic control unit 501 sets the command to the polling command register 643 from the micro processor 601. I can know that.

When the electronic control unit 501 determines that the command has been set by looking at the flag CMDRD, which is bit d3 of the status register 645, the electronic control unit 501 uses a normal read cycle to set the polling command register. Read the contents of 643, that is, the command sent from the micro processor 601. The contents of the command include an instruction to start transfer of print data to the data transfer control unit 603, an instruction to start printing, and a message to be displayed on the console panel 518. When the electronic control unit 501 reads the contents of the polling command register 643, as shown in FIG. The output signal CMDRD of the D-type flip-flop 643c is inverted to a high level by the signal ZP0LL. Therefore, the my mouth processor 601 monitors the predetermined bit d2 of the transfer flag register 647 to determine whether or not the command output by itself is read by the electronic control device 501. You can know.

The status register 645 is a register that holds the information shown in FIG. 22 in addition to the information indicating whether the command has been set from the microprocessor 601 or not. The contents of each bit will be described. The bit d0 is a signal EWRDY generated in the read control circuit 620 when data is written from the electronic control unit 501 to the first word latch 651 of the read control circuit 620 described later. Is set to low level, and when the data is read by the microprocessor 601 side, it is reset to high level by a signal from the second decoder 632. This bit is called the flag EWRDY 0. The bit d4 is set to a low level by a signal EWRY1 generated in the read control circuit 620 when data is written from the electronic control device 501 to the second lead latch 652. When the data is read by the micro processor 601, it is reset to a high level by a signal from the second decoder 632. This bit is called flag EWRDY 1.

Bits dl and d 2 indicate whether the double bank control circuit 624 is accessible from the electronic control unit 501 side or the micro processor 60 1 side, and the flags ADDMUXA, Called ADDMUXB. The two bits correspond to each of the two transfer banks included in the double bank control circuit 624. These bits d1 and d2 are the bits of the registers AD DMUXA and ADDMUXAB that the microprocessor 601 uses, as shown in FIG. 16, the registers included in the control register 650. Set / reset by writing data to dO. Therefore, the micro processor 601 sets this flag to low level before writing data to one puncture of the double bank control circuit 624, and resets it to high level after writing is completed. If the electronic control unit 501 reads data from the bank on the side where this flag is at a high level, it is necessary to write and read data alternately in the two banks. Microprocessor 60 Data can be continuously transferred from one side to the electronic control unit 50 1 side.

Bit d3 (flag CMDRD) has already been described. Bit d5 is a flag CLKDIV set based on the operation clock of microprocessor 601. The operation clock of the microprocessor 601 uses the clock CLK output from the first oscillator 661 using the external crystal oscillator CRC1, but the microclock is used. When the value 0 is written to the bit dO of the control register 650 from the processor 601 and the control register 650, the operation clock CLK of the microprocessor 601 becomes 25 MHz, Writing a value of 1 to bit dO results in an operating clock of 12.5 MHz. Electronic control unit 50 Status register viewed from the 1st side Flag at 645 CL KD IV is set to low level when this clock CLK is 25 MHz, and is set to high level when 12.5 MHz. Is set to If the electronic control device 501 needs to know the operating clock frequency, that is, the operating speed of the micro-processor 601 in order to match the timing of data transfer, etc. Check this bit of the register 645.

Bit d6 is a flag ADM0N that is set high when microprocessor 601 is operating and is set low when sleep mode is entered. In this embodiment, the microprocessor 601 receives the page description language from the electronic control unit 501 and performs processing for developing the page description language into image data. If a predetermined time has elapsed without sending a page description language, the microprocessor 601 sets the operating frequency to 1/2, that is, 12.5 MHz in order to save power. If more time passes, it stops its operation and enters the so-called sleep mode. At this time, the microprocessor 601 writes the value 0 to the register ADM0N of the control register 650. As a result, when viewed from the electronic control unit 501 side, this bit d6 of the status register 645 becomes a low level, and by checking this bit from the electronic control unit 501 side, the micro processor It is possible to know the 60 operation modes.

Note that a real time clock incorporated in the data transfer control unit 603 is used for such time measurement and the like. Clock RC for this real-time clock As the LK, a clock from a second oscillation circuit 667 configured using an external crystal oscillator 665 is used. The rear time clock is configured in the bus control unit 635, and measures an elapse of a predetermined time in response to an instruction from the micro processor 601. The two sets of crystal oscillators and oscillators are provided so that the operation clock CLK of the microprocessor 601 can be changed independently of the real-time clock operation clock RCLK. That's why.

The real-time clock can specify four types of inter-part timers by setting the dl bit of the registers RT CVAL and RTCSEL belonging to the control register 650 to low or high. The timer can be started by writing a value of 1 to the predetermined bit d0 of the register RTCON. The started timer outputs an interrupt request signal to the micro processor 601 at a predetermined interval until a value of 0 is written to the bit dO of the register RTCON and the timer is stopped. I do. Upon receiving this interrupt request signal, the microprocessor 601 reads the register RTCCLR and clears the interrupt request. The output of these interval timers is used for counting user time in page description language processing.

Next, the configuration of the PROM control register 649 will be described. The PROM control register 649 includes the three registers EEPCS, EEPSK, and EEPD I shown in FIG. 17, and these registers are memories stored in the cartridge 503. This is used for exchanging data with EEPROM 670, which is electrically erasable and rewritable.

The cartridge 503 of this embodiment stores various variables (configuration) necessary for the operation of the laser printer 500 in the EE PROM 670. The EE PROM 670 is of a type in which data is read, erased, and written by serial transfer. In this embodiment, the NM C 93 C 66 X manufactured by National Semiconductor Co., Ltd. You are using 3. The EEPROM 670 has a storage capacity of 16 bits x 256 bits (the number of registers), and can read, erase, and write the contents of any specified register. When the EE PROM 670 is selected by the chip select signal CS, it is sent to the serial data input terminal Din “0”. The data of Γ1 ”is fetched in synchronization with the serial data clock SL, but the first three bits of the data transfer are interpreted as an instruction to EEPR 0 、, and the next eight bits are transferred. Is interpreted as the register number where data is read, erased or written. In the case of writing data, following these instructions and register designation, data to be stored is given to the data input terminal Din in synchronization with the serial data clock SL. Become.

The register EEPCS switches the chip select signal. When the microprocessor 601 writes the value 1 to bit dO of this register, EEPR0M670 is selected. State. The register EEPSK is a register that generates a serial data clock SK. The microprocessor 601 writes the value 0 and the value 1 to this register alternately, Generate serial data clock for EPROM670. The register EEPDI is a register that holds 1-bit data to be written to the EE PROM 670. The micro processor 601 rewrites the register EEPSK and rewrites the serial data clock SK. In synchronization with the generation of the data, the predetermined bit d0 of the register EEPD I is rewritten according to the data to be written. The data output terminal D 0 ut of the EEPROM 670 is the predetermined bit d O of the transfer flag register 647 described above, and the micro processor 601 reads data to the EE PROM 670. After outputting the instruction and the register number to be read, read the bit dO of the transfer flag register 647 in synchronization with the serial data clock SK to read the contents of the specified register. Can be. The data stored in the EE PROM670, because also be saved as the power is turned off immediately after turning on the power to Rezapuri te 500, Read out the contents of the EE PROM670, the co-Nfu I Gureshi ₃ down It can return to the state immediately before the power was turned off.

G. Configuration and Function of Readout Control Circuit 620

Next, a configuration example of the read control circuit 620 and a procedure of data transfer by the read control circuit 620 will be described. The read control circuit 620 includes a first word latch 651, consisting of 8 bits × 2 latches 651a and 651b, and an 8bit × 2 latches 652a, As shown in Figure 23, with a second latch 652 consisting of 652b. Address bus Outputs CAD address signals AC1 to AC8 as 1-byte data Z0 to Z7 to FIFO control circuit 623. 3-state buffer 67 1, 2 2 inputs D-type flip-flops that generate the flags EWRDY O (bit dO) and EWRDY1 (bit d4) of the status gates 672 and 673 and status register 645 674 and 675.

The data input terminals 1D to 8D of the latches 651a, b and the latches 652a, b constituting the first and second word latches 651, 652 are connected to the connector side. 16 bits (AC1 to AC16) of the address line from the address bus CAB are connected, and the output terminals 1Q to 8Q are connected to the data bus DB29. Lines DO or D15 are connected. The output of OR gate 672 is connected to the clock terminals CK of latches 651a and b, and the output of OR gate 673 is connected to the clock terminal CK of latches 652a and b. Each is connected. The outputs of these gates 672 and 673 are also connected to clock terminal C of D-type flip-flops 674 and 675, respectively.

The output enable terminal 0 E of each latch 65 1 a, b has a signal E WR DO, and the output enable terminal 0 E of latches 652 a, b has a signal / E WRD 1 Are connected to each other. These signals ZEWRD 0 and EWRD 1 are connected to the preset terminals PR of the D-type latches 674 and 675. The signal / EWWR 0 and signal ZAD S are connected to each input terminal of the 2-input OR gate 672, and the signal ZEWWR 1 and signal ZAD S are connected to each input terminal of the 2-input OR gate 673, respectively. . The signal / ADS is an address strobe auxiliary signal generated based on the address strobe signal ZASB.

Here, the signal ZEWWR 0 is a signal that goes low when transfer of one word is specified by the read control circuit 620, and the signal ZEWWR 1 is a signal 1 that is different from the one in the previous word. This signal goes low when a code transfer is specified. The signal obtained by ANDing the signal ZEWWR 0 and the signal ZEWWR 1 with the signal / ADS with negative logic is the clock of the first word latch 65 1 and the second word latch 65 2, respectively. Since these signals are activated since they are input to the terminal CK, the address AC1 or AC1 output to the address bus CAD when these signals are activated 6 is retained in the first word latch 651 or the second word latch 652. Moreover, the output of OR gates 672 and 673 is D-type flip-flop 674,

Since the signal is also input to the clock terminal C of the 675, the output Q of the D-type flip-flop 674 or the 675 is set to the low level. The outputs EWRDY 0 and EWRDY 1 are bits dO and d4 of the status register 645 described above, and bits dl and d4 of the transfer flag register 647, ie, the flags EWRDY O and EWRDY 1 Is treated as

When the readout control circuit 620 is viewed from the electronic control unit 501 side, the first and second latches 65 1 and 652 occupy an area of 128 KB each as shown in FIG. It corresponds to two registers E WWR 0 and EWWR 1. Accessing the specified addresses in these areas results in the transfer of 1 word and 16 bits of data, respectively. The first and second word latches 65 1 and 652 correspond to the one-word registers EWRD O and EWRD 1 shown in FIG. 17 when viewed from the microprocessor 601 side. Both the word latches 65 1 and 652 are accessed as one word from both the CPU 510 and the microprocessor 601 via the data bus DB 68 or the data bus DB 290. be able to.

The first word latch 65 1 and the second word latch 652 are treated as the registers EWRD O and EWRD 1 from the microprocessor 601 side, so the first word latch 65 1 and the second word latch 652 are treated as the first word latch 651. When trying to read the data held in switch 651 and second word latch 652, microprocessor 601 performs a read operation on register EWRD0 or EWRD1. At this time, the signal ZEWRD0 or EWRD1 becomes reactive, and this signal is the first or second word latch 651, which is connected to the output enable terminal OE. The previously held address (actually, data) is output to the output side of the 652, that is, the data bus DB 29. These signals ZEWRD O and ZEWRD 1 are D-type flip-flops 674 and 674.

Since it is connected to the 75 preset terminal PR, the data of the first word latch 65 1 and the second word latch 652 are read from the micro processor 60 1 side, and The signal EWR which is the Q output of the type flip-flops 674 and 675 DY 0 and EWRDY 1 are inverted to high level. That is, the bits d0 and d4 of the status register 645 and the flags EWRDY O and EWRDY1 of the bits d1 and d4 of the transfer flag register 647 are set to the value 1. You.

On the premise of such hardware, the electronic control unit 501 and the microprocessor 601 transfer data from the electronic control unit 501 to the microprocessor 61 in the following procedure. In this embodiment, the data transferred from the electronic control unit 50 1 to the -microprocessor 60 1 side is limited information such as operation information of the console panel 518. If a computer different from the workstation 507 is connected to the data input port 5 14 of 1, information such as print data received from this computer can also be provided. In this case, the print data is a program of a page description language, and is processed by the micro processor 601 on the cartridge 503 side. The data transfer by the read control circuit 620 includes a data transfer processing routine to the cartridge (FIG. 24) executed by the CPU 510 of the electronic control device 501 (FIG. 24), and a data transfer processing routine by the cartridge 503. This is performed by the data read interrupt processing routine (FIG. 25) executed by the micro processor 601. In the following, data transfer using the first word latch 65 1 will be described as an example. Data transfer using the second word latch 652 is exactly the same.

If there is data to be transferred to the cartridge 503, the CPU 510 activates the processing shown in the flowchart of FIG. 24, and firstly, the flag EWRD YO ( A process of reading bit dO) is performed (step S700). This flag EWRDYO has a value of 0 when data is set in the first word latch 651 of the read control circuit 620, and has a value of 0 when the data is read by the microprocessor 601. Since the flag is set to 1, it is determined whether or not the flag EWRDYO has a value of 1 (step S705).

Wait until the flag EWRDY reaches the value 1, and when it reaches the value 1, perform the process of reading the address of (start address of area EWWR 0 + data DX 2 to be transferred) (step S710). In this embodiment, the start address of the area E WWR 0 is 500000 h. When the reading process for area EWWR 0 is performed, The address signals AC 1 to AC 16 of the address subjected to the above operation are held in the first word latch 65 1 as data as they are. Since the lower 16 bits are latched except for the address bit LDS corresponding to the least significant bit, if the read processing is performed for an address separated by DX2 from the beginning of the area E WWR 0, Data D is latched to the first word latch 651. After the above processing, the CPU 510 performs processing to set one of the interrupt request registers (in this embodiment, AMDINTO) (step S720).

The CPU 510 continues to repeatedly execute the transfer processing routine shown in FIG. 24. However, when data is held by the first word latch 651, the flag EWRDY is output as shown in FIG. Since O is set to low level, the next data transfer processing is not performed until this flag EWRDY0 becomes high level (value 1) (steps S700, 705).

When the CPU 510 sets the interrupt request register (AMDINT0), the microprocessor 601 receives the interrupt request and sets the data read interrupt shown in FIG. Starts the load processing routine. That is, this interrupt request is treated as a notification of overnight transfer to the cartridge 3. This process is activated immediately after data is held in the first word latch 651 (or the second word latch 652) of the read control circuit 620, and By reading the register EWRD 0 (or EWRD 1), the cyclo processor 601 reads the data of one mode prepared by the electronic control unit 501 side (step P S 730). Thereafter, the microprocessor 601 transfers the read data to a predetermined area of the RAMs 61 1 to 614 (step S735).

According to the processing described above, the electronic control device 501 can transfer data to the cartridge 503 which is merely connected by the data path CDB which is a read-only line. . In addition, immediately after the data is transferred, it is notified that the data has been transferred to the cartridge 3 by an interrupt request, so that the cartridge 3 can efficiently transfer the data from the electronic control device 501. You can receive. Therefore, the microprocessor 601 of the cartridge 3 does not need to continuously monitor the data transfer by the electronic control unit 501, and waits for the next data write by the electronic control unit 501. Never even. Further, in the present embodiment, the fact that the data has been transferred from the electronic control unit 501 is determined by the bit dl or d4 of the transfer flag register 647, that is, by the flag EWRDYO or EWRDYl. , You can know. Therefore, even if multiple conditions are assigned to the interrupt request register AMD INT 0, the micro processor 601 checks the flag EWRDY O or EWRD Y 1 when accepting this interrupt request. This ensures that data transfer requests can be distinguished from other requests.

Also, in this embodiment, when the data set from the CPU 510 is read by the micro processor 601 and the data transfer is completed, the flag E WR DY 0 or E WR DY is set by the hardware. Since 1 is inverted, the electronic control unit 501 can immediately know the completion of the overnight transfer. Therefore, in this embodiment, a plurality of data can be sequentially transferred at high speed. In addition, in the present embodiment, since data is written and read in units of a unit, the microprocessor 601 can efficiently take in data.

Configuration and function of H.FIFO control circuit 623

As shown in FIG. 18, the FIFO control circuit 623 is a latch 657 for latching data to be written to the FIFO memory 621, and controls writing of data to the FIFO memory 621. It has a FIFO write register 653 and a FIF 0 read register 655 that controls reading as well. The FIFO memory 621 can store 1152 bytes of data, and internally has a write address counter and a read counter. The FIFO memory 621 has a reset terminal on the write side, a reset terminal on the read side for resetting these counters, an 8-bit data bus on the write side, and a reset terminal on the read side. A bit data bus, a clock terminal for writing, and a clock terminal for reading are provided. Note that the data to the latch 657 is provided via a trial state * * 671 shown in FIG. The output of the buffer 671 becomes valid when the signal / FIFOWR input to the gate terminals 1G and 2G becomes low level. This signal ZFIF OWR becomes low level when data transfer by the FIFO control circuit 623 is specified. To transfer data from the electronic control unit 501 side to the microphone port processor 601 side using the FIFO memory 621, the CPU 510 of the electronic control unit 501 is shown in FIG. The microprocessor 601 of the cartridge 503 executes the transfer processing routine, and executes the processing routine shown in FIG. 27, respectively. First, the processing routine shown in the flowchart of FIG. 26 will be described. The CPU 510 of the electronic control device 501 can perform a plurality of bytes of data transfer using the FIF 0 control circuit 623 by executing the processing shown in FIG.

When the CPU 510 of the electronic control unit 501 activates the data transfer processing routine shown in FIG. 26, first, a process of reading the register FIF ORST belonging to the FIFO writing circuit 654 of the FIFO control circuit 623 is performed. A process is performed to reset the write and read side address counters (step S750). Subsequently, the variable N is reset to a value of 0 in order to count the number of data to be sent out (step S755). Thereafter, the process of reading the address (the start address of the register FIF OWR + the data to be transferred DX2) is performed (step S760). Note that the start address of the register FIFOWR in this embodiment is 5D00000h as shown in FIG. When this address is read, the address of the read address is output as data as in the case of the read control circuit 620, which is latched via the bus Z0 or Z7 shown in FIG. It is latched to.

When this latch operation is performed, a write clock is output to the clock terminal on the write side of the FIFO memory 621 after a predetermined delay time, and the data held in the latch 657 is output. D is written to the address indicated by the write-side address counter in FIF 0 memory 621. At the same time, the contents of the write address counter in the FIFO memory 621 are incremented by a value of one. When one byte of data is written in this way, the variable N indicating the number of transferred data is incremented by 1 (step S770), and the variable N indicates the total number of bytes to be transferred. Then, it is determined whether or not the number is equal to the number X (step S775). Therefore, the processes in steps S760 to S775 described above are repeated until the number N of bytes of the transferred data matches the total number X of data. '

When the transfer of all data is completed, the CPU 510 sets one of the interrupt request registers (A MDINT 1) is set, and the completion of the data transfer is notified to the micro processor 601 (step S780), and the process exits from "ΓΝ Ε ΓΝ" and ends this processing routine. I do.

On the other hand, the microprocessor 601 receives the interrupt request AMD I I1 and starts a data reception interrupt routine showing a flow chart in FIG. When this routine is started, the microprocessor 601 first performs a process of setting a value 0 to a variable M for counting the number of received data (step S805).

Thereafter, a process of reading the register FIRCLK belonging to the FIFO read register 655 is performed (step S810), and the read data is transferred to a predetermined area of the RAM 611 to 614. Processing is performed (step S815). When register FIRCLK is read, the read clock is output to the read-side clock terminal of FIFO memory 621, and the data D at the address indicated by the read-side address counter at that time is read. At the same time, the content of the read-side address counter in the FIFO memory 621 is incremented by a value of one.

When one byte of data is received, the variable M is incremented by 1 (step S820), and it is determined whether or not this variable M is equal to the total number of bytes X of the data to be transferred. A decision is made (step S825). Therefore, the processing of steps S810 to S825 described above is repeated until the number of bytes M of the received data matches the total number X of data.

When it is determined that the reception of all data has been completed, the microprocessor 601 performs a process of writing a command indicating completion of reading of the data into the polling command register 643 (step S630). . By reading the contents of the polling command register 643, the CPU 510 of the electronic control device 501 can know the completion of data reception by the FIF0 control circuit 623. After that, the microphone processor 601 exits to “RNT” and ends this processing routine. By the processing described above, a large amount of data can be efficiently transferred from the electronic control device 501 to the microprocessor 601. In addition, immediately after the transfer of a plurality of bytes of data, the interrupt request signal AMD INT 1 notifies the cartridge 3 that the data has been transferred to the cartridge 3. Control device 50 While 1 is performing data transfer, the microprocessor 601 of the cartridge 3 does not need to continuously monitor the data transfer by the electronic control unit 501 and performs other processing. This can increase the overall processing efficiency. Originally, there is no need to wait for writing of the next data by the electronic control unit 501.

I. Configuration and operation of double puncture control circuit 624

The print data received from the workstation 507 by the communication control unit 604 is interpreted by the page description language interpreter stored in the ROMs 606 to 609, developed as an image, and temporarily stored in the RAM 61 1 to 6 Stored in 14 predetermined areas. The image data thus obtained is then transferred to the electronic control unit 501 side, stored in its RAM 512, and printed by the laser engine 505 at a predetermined timing. . The double bank control circuit 624 transfers such image data. The double bank control circuit 624 transfers the data from the microprocessor 601 to the electronic control unit 501, and includes two sets of banks for storing 256 bytes of data. These are called A bank and B bank, but both are exactly the same as the hardware, and only the configuration example on the A bank side is shown in Fig. 28.

Each of these banks is configured so that its address and data bus can be switched between the microprocessor 601 side and the electronic control unit 501 side, and as shown in FIG. Select data selectors 681, 682, 683, two sets used to select the data bus (16-bit width), two sets total four octal liners, * ヅ files 684 to 687, It is composed of RAMs 691 and 692 with a storage capacity of 128 bytes, and other configuration gates, or gates 694 and 695 and an inverter 696. In Fig. 28, two memories with 128 bytes of storage capacity are used, but this is realized by switching the upper address of a single memory. No problem.

The data selectors 68 1 and 683 are the lower 7 bits (AC 1 to AC 7) of the address path CAB of the electronic control unit 501 and the lower address bus AAB of the micro processor 601. Select 7 bits (A2 to A8) and output The address bus is selected by the signal ADDMU XA (bit ADO of register ADDMUXA) connected to the select terminal S. The data selector 682 switches the read / write signals of the RAM691 and 692 according to the selection of the address bus. Similarly, the signal ADDMUXA connected to the select terminal S It switches which signal is connected to the chip select terminals CE 1, 2 of the RAM 691, 692 and the input enable terminal OE.

Octal line buffers 684 and 685 are 3-state type buffer interposed in the data bus DB 29. When the gate terminals 1G and 2G are in the mouth level, the My line buffers 684 and 685 Connect the data bus DB 29 of the microprocessor 601 to the data bus of the RAMs 691, 692 to enable the microprocessor 601 to write data to the RAMs 691, 692. The output of the OR gate 694 which receives the signal / DPWR 0A and the signal AD DMUXA is connected to the gate terminals 1G and 2G of the octal line buffers 684 and 685. The signal / DPWR0A is a signal that goes low when the microprocessor 601 attempts to write data to bank A. Therefore, if the bit dO of the register ADDMUXA is set to a low level in advance as the data is written to the bank A, the data is written from the microprocessor 601 side to the bank A. Then, the gates of the octal line buffers 684 and 685 are opened, and the data output to the data bus DB 29 is output to the data buses of the RAM 691 and 692, and is damaged.

On the other hand, the octal line buffers 686 and 687 have the data paths DB 68 and RAM 69 1 and 692 on the electronic control unit 501 side when the gate terminals 1 G and 2 G are at the low level. And the data buses of the RAMs 69 1, 692 can be read out to the electronic control unit 501. The gate terminals 1 G and 2 G of the octal line buffers 686 and 687 are connected to the OR gate 695 which receives the signal ZD P 0 E 1 A and the signal obtained by inverting the signal AD DMU XA by the inverter 696. Output is connected. The signal ZDPOE1A is a signal that goes low when the electronic control device 501 attempts to read A-punk data. Therefore, A bank If the bit dO of the register AD DMUXA is set to a high level in advance for reading data overnight, the readout processing from the electronic control unit 501 to the bank A is performed. The gates of the kutal line buffers 686 and 687 are opened, and the data output to the data paths of the RAMs 691 and 692 is output to the data path DB 68. Assuming this hardware, a description will be given of the image data transfer processing performed by the micro processor 601 and the reception processing performed by the CPU 50 of the electronic control unit 501. FIG. 29 is a flowchart showing the image data transfer start processing routine performed by the micro processor 601. As shown in the figure, the microprocessor 601 sets a transfer start command in the polling command register 643 prior to the transfer of the image data (step S850).

The CPU 510 of the electronic control unit 501 reads the command of the polling command register 643 and executes the response processing routine shown in FIG. That is, the electronic control unit 501 determines whether or not the laser printer 500 is in a printable state (step S860). If the electronic control unit 501 determines that the laser printer 500 is in a printable state, it issues an interrupt request. One of the registers (AMDINT2) is set (step S865), and "Exit to NEXTJ and finish this routine. A process for notifying the microprocessor 601 of the cartridge 503 is performed (step S870). The state in which printing cannot be performed includes, for example, a state in which the laser engine 505 has not been warmed up, a paper jam, and the like. This means that printing cannot be performed even when image data is transferred, such as when the image data has occurred.

Upon receiving an interrupt request signal AMDINT2 from the electronic control unit 501, the microphone opening processor 601 starts an image data transfer interrupt processing routine shown in FIG. When this process is started, the microprocessor 601 first performs a process of writing a value 1 to bit d0 of the register ADDMUX A (Step S900) <bit d0 of this register ADDMUXA. If O has the value 1, the data path of RAMs 69 1 and 692 that make up bank A is connected to the data bus DB 29 of processor 601 as shown in Figure 28. As a result, access from the electronic control unit 501 cannot be performed.

Next, the microprocessor 60 1 is connected to the A bank DPWR 0 A by 128 words. A process of transferring (256 bytes) data is performed (step S902). When data is written to the A bank DPWR OA, the signal / DPWR OA shown in FIG. 28 goes low, and the data is written to the RAMs 691 and 692 via the octal line buffers 684 and 685. . When the data transfer of 128 words is completed, the microprocessor 601 writes the value 1 to the bit dO of the register ADD MUXA (step S904), and the RAM 691, which configures the bank A, 6 Connect the 92 data bus to the data bus DB 68 of the electronic control unit 501.

Thereafter, the microprocessor 601 performs a process of writing command data notifying the completion of the transfer to the A bank to the polling command register 643 (step S906). As described above, the data transfer processing to the A bank is completed, and the micro processor 601 continues to execute the same processing as that described above for the B bank (step S910). When the data transfer to the bank B is completed, the microprocessor 601 writes command data to the polling command register 643 to notify the completion of the data transfer. In this way, the transfer of 256 words (512 bytes) of data from banks A and B of cartridge 503 is completed.

In response to the processing of the microprocessor 601 described above, the CPU 510 of the electronic control unit 501 executes an image data receiving processing routine shown in FIG. That is, the CPU 510 first reads bit d3 of the status register 645, ie, the flag CMDRD (step S920), and determines whether or not this value is 0 (step S920). S 925). When command data is written to the polling command register 643 from the microprocessor 601, the flag CMDRD is set to the value 0. The command data of the command register 643 is read (step S930).

The read command data is checked, and it is determined whether or not the command data indicates that the A puncture data overnight transfer has been completed (step S935). (Step S940). When the command data of the polling and command register 643 indicates the completion of the data transfer of the A bank, the electronic control unit 501 controls the A bank DPRAMA (see Fig. 16). The process reads the 128 words of the memory (step S945), and transfers the read data to the RAM 512 (step S950).

With the above processing, the reading of 128 words of A puncture data is completed, so that the transfer of the next 128 words from the microprocessor 601 should be permitted. Set one in the evening (AMD I NT 2). Subsequently, the processing in steps S920 to S955 described above is executed for the B bank. That is, when it is determined from the command data of the polling command register 643 that the transfer of data from the microprocessor 601 to the bank B has been completed, the 128 words of the bank B DPR AMB are determined. After reading this data and transferring it to RAM 512, one of the interrupt request registers is set and an interrupt request is made to the micro processor 601.

In response to such an interrupt request, the microprocessor 601 executes the interrupt processing routine shown in FIG. 31 again, so that the microprocessor 601 and the CPU 510 are both Execution of the routine (Figs. 31 and 32) completes the transfer of all image data. After the transfer of all image data, if new print data is not received from the electronic control unit 501, the microprocessor 601 stores the new print data in the register C LKD IV of the control register 650 after a predetermined time has elapsed. Write a value of 1 and switch its own operating frequency to half, 12.5 MHz, to reduce the yellowing power and thus the heat generation.

With the above configuration, the cartridge 503 can efficiently transfer the developed image data to the electronic control unit 501 by using the interrupt and the flag CMDRD of the register. . As described below, the image data is simultaneously sent to the laser engine 505 for printing, so that the transfer of the image data from the cartridge 503 is performed efficiently. It is extremely important.

J. Printing of image data

On the other hand, the electronic control device 501 that has received the transfer of all the image data performs printing with the image data while exchanging signals with the laser engine 505 using the double buffer circuit 520 and the register 517 described above. . Electronic control unit 50 1 and laser The exchange of signals with the engine 505 is shown schematically in FIG. The outline of printing will be described with reference to this figure.

Upon receiving the image data after the development from the cartridge 503, the electronic control unit 501 inquires whether or not the laser engine 505 is in a printable state. If it is determined that the printer is in a printable state, a print signal shown in FIG. 33 is output to the laser engine 505 via the register 517. Upon receiving this signal, the laser engine 505 immediately activates the paper transport motor. In synchronization with this, the rotation of the photosensitive drum, the charging process and the like are started.

When the paper to be printed reaches a position separated by a predetermined distance from the photosensitive drum, the laser engine 505 detects the leading edge of the paper and sends a signal VREQ to the electronic control unit 501 via the register 5 17. Output. Upon receiving the signal VR EQ, the electronic control unit 501 waits for a predetermined time, that is, the time required for the photosensitive drum to rotate to a position where the formation of a latent image by the laser beam is started, and then issues the signal VS YNC is output via register 517. Laser engine 505 receives this signal V SYNC and outputs a horizontal synchronizing signal H SYNC of the laser beam via register 517. Since this signal H SYNC is equivalent to a signal instructing the start of reading of one line of image data, the laser engine 505 synchronizes the image data with the RAM 520A of one of the double buffer circuits 520 in synchronization with this signal. Or read from 520B. When forming a top margin, control is performed to ignore signal V SYNC by the number of lines corresponding to the top margin. This control is the same when forming bottom margins.

At the same time, the CPU 510 counts this signal and transfers necessary image data to the RAM 520A or the RAM 520B of the double buffer circuit 520. If a predetermined time has elapsed since the laser engine 505 detected the trailing edge of the paper, or if the count value of the horizontal synchronization signal becomes equal to a value set in advance according to the paper size, C The PU 510 terminates the transfer of the image data to the double buffer circuit 520. Through the above processing, one page of image data is transferred to the laser engine 505, and the image is printed on a sheet. The transfer and printing of the image data are as described above. Lastly, the process of changing the set values stored in the EE PRO M 670 will be described. The CPU 510 of the electronic control unit 501 executes the set value change processing routine shown in FIG. 34 at a predetermined timing, and determines whether or not a request for changing the set value has occurred ( Step S1200). The request for changing the set value is made when it is determined whether or not the cartridge 503 is mounted immediately after the power is turned on, or when the switch 5 18 a of the console panel 5 18 is operated. Alternatively, it occurs when a change is instructed from the workstation 507 via the cartridge 503. It should be noted that a change instruction from the console panel 5 18 or the workstation 507 may be configured to be accepted only when image development is completed, except for communication. It is suitable. This is because, in many cases, it is not possible to change the setting values relating to the image development during the image development according to the predetermined page description language.

If the request for changing the set value has not been issued, this routine ends without performing any processing. If it is determined that the request has been issued, the process for determining the set value is performed (Step S). 1 2 10). Here, the judgment of the set value is performed, for example, according to the operation procedure of the switch 518 a of the console panel 518 or transmitted from the work station 507 via the cartridge 503. It means a process of analyzing the command that has been specified and specifying which item of the communication condition is set to what. When making settings from the console panel 518, in order to make effective use of the limited number of operation buttons, options are displayed on the display display 518b, and one of them is operated by operating the switch 518a. In many cases, an effort to select an item is taken. The method and result of setting value determination are determined according to these specifications.

After determining the set value, the electronic control unit 501 performs a process of transferring the set value to the cartridge 503 via the read control circuit 620 (step S 1220). Upon receiving this data, the data is stored in the EEPROM 670 by the processing described above. After that, the CPU 510 displays on the LCD panel 518b of the console panel 518 that the setting is completed, and ends this routine. Since the EEPROM 670 stores data by serial transfer, when data is transferred from the electronic control unit 2, the R The data expanded in a predetermined area of AM611 is rewritten, and rewritten collectively at a predetermined timing. The data of these setting values may be rewritten each time a predetermined time elapses, or may be rewritten after an instruction from the console panel 518. Furthermore, a battery may be provided on the cartridge 503 side to perform the operation immediately after the power of the laser printer 1 is turned off or immediately after the cartridge 503 is disconnected from the connector CN 11. No problem.

Such a change in the set value may simply involve a change in conditions such as the number of prints, or may involve a complete change in the operation mode of the laser printer 500. In the latter case, for example, the processing by the page description language in the cartridge 503 may be stopped, and the processing may be switched to processing by a control command unique to the laser printer 500, or the reverse may be performed.

According to this configuration, since the set values that determine various conditions for operating the laser printer 500 are stored in the EE PROM 670 of the cartridge 503, the cartridge 503 is attached to the connector CN11. This makes it possible to easily switch the operating conditions of the laser printer 500 to those suitable for developing the image data by the cartridge 503. Moreover, since the contents of the EE PROM 513 of the electronic control unit 501 are not rewritten, when the cartridge 503 is removed, the operating conditions of the laser printer 500 can be immediately returned to the original state. it can. Therefore, even when the force trigger 503 is added to the laser printer 500 to change its function, not only the setup but also the release can be easily performed. Although the number of prints using the laser engine 505 is also normally stored, this means that the data in the EEPROM 513 is rewritten even when printing is performed with the cartridge 503 installed. . Originally, this value may be stored in the EEPROM 670 of the cartridge 503. Also, the number of sheets printed with the cartridge 503 mounted may not be counted.

K, effect of the second embodiment

According to the second embodiment described above, similarly to the first embodiment, by mounting the cartridge 503, the processing program of the page description language is simply provided by the cartridge. It can significantly improve the processing power of the page description language as compared with the case where it is supplied. Also, since the cartridge 503 has a communication function, it can be connected to another workstation 507 without disconnecting the laser printer 500 from the computer. It has become. Further, since the print data from the work station 507 is directly received by the cartridge 503, there is no need to transfer the data from the laser printer 500 to the cartridge 3. Can be used on existing printers where you do not plan to install a cartridge with a processor.Typically, as the capabilities of the computer itself improve, In many cases, the entire printer body is replaced in accordance with improvements in the functions of the computer body, as this would result in a bottleneck in the system. In this case, it is only necessary to mount the cartridge 503 having a highly functional processor to the laser printer 500, and it is extremely advantageous in terms of cost.

In addition, in this embodiment, data can be transferred to the cartridge 503 via the read-only data bus DB 68 when viewed from the electronic control device 501 side. Therefore, information on the printer body 1 such as the operation status of the console panel 5 18 can be notified to the cartridge 503 without delay. At this time, the interrupt is used for the notification of the data transfer, and the process on the cartridge 503 side is activated by the interrupt request. Therefore, the micro processor 601 of the cartridge 503 is There is no need to constantly monitor the operation of the electronic control unit 501, and the microprocessor 601 of the cartridge 503 can be used efficiently. That is, the processing overhead can be reduced, and the overall efficiency can be improved. Further, in this embodiment, since the ASIC is used, the circuit can be reduced in size and simplified. Further, since two systems of data transfer from the electronic control unit 501 to the data transfer control unit 603 are prepared: the read control circuit 620 and the FIFO control circuit 623, these can be used depending on the type of data to be transferred. Data transfer can be performed efficiently. Also, if one system fails, the other system can compensate for it.

L. Other examples

The specific configuration example of the present invention has been described with reference to the two embodiments. Is not limited to these examples.

(1) Configuration to load a new program into cartridge 503

Since the cartridge 503 can receive data from the outside via the communication control unit 604, for example, the communication control unit 604 transmits a new page description language such as an interface. The data can be loaded to a predetermined area of the RAMs 611 to 614 through the RAM. Then, if control is transferred to this program, processing can be performed using a new page description language. Therefore, it is possible to easily update the page description language, perform a purge β upload, and the like.

In addition, if any abnormality occurs in the operation of the cartridge 503, a program for debugging can be loaded and used via the communication control unit 604. Usually, it is difficult to prepare an emergency program for a product to be distributed in advance, so the merit that can be downloaded as needed is extremely large.

(2) Configuration to display on the LCD panel 518b of the console panel 518

By transferring data other than image data from the micro processor 601 to the CPU 510 via the double bank control circuit 624, the desired display can be performed on the console panel 518. Can be. For example, while the data transfer control unit 603 interprets the program of the page description language and develops the image, the printer main body 1 appears to the user as if it were stopped. The LCD panel on the sole panel 518 displays not only `` Data is being developed, '' but also the name of the module currently being deployed, and the percentage of modules that have already been deployed for all modules. When the is displayed as a percentage, a configuration that can be considered.

If an error occurs during the use of the memory on the cartridge 503 or during the development of the page description language, the error code and its contents are displayed on the LCD panel of the console panel 518. It is also suitable to display on a display panel. In addition, the operation mode of the microprocessor 601 of the cartridge 503, such as the operating frequency / sleeving mode, is displayed, and the memo is displayed when the cartridge 503 is attached. When the power capacity is insufficient due to the capacity of the power supply, etc., it is also effective to display the message or the message to instruct to remove the additional memory of the laser printer 500. is there.

The embodiment in which the present invention is applied to a printer has been described above. However, the present invention is not limited to application to a printer. For example, a word processor, a personal computer, or a workstation may be used. It can also be applied to such applications. In recent years, such computer-related equipment has often been equipped with a cartridge-type expansion device such as an IC card, as well as an expansion slot. In a word processor or personal computer equipped with such an extended slot IC card or the like, the additional control device of the present invention is mounted here, and the processing of the processor on the main body side is performed by a monitor command or the like. If the processing is shifted to the processing stored in the memory built in the additional control device and the information is processed together with the processor provided in the additional control device, it is easy to improve, add or change the information processing function. It is. Furthermore, if control is transferred to the additional control device side, the content of the processing can be changed in any way, so the functions of already sold devices can be changed or improved, and software for various dedicated machines such as word processors can be used. Purging up can be realized.

[Industrial applicability]

The present invention relates to an apparatus using a processor, which is an apparatus that receives data and operates externally, such as a printer, an on-board electrical device, a facsimile, a telephone, an electronic notebook, and an electronic musical instrument. The present invention can be applied to any information processing device to which an additional control device can be connected by a connector, such as a translator, a cache dispenser, and a remote control device.

Claims

The scope of the claims

1. A first processor capable of performing a logical operation, first storage means for storing processing executed by the processor, and a signal line capable of exchanging data with the first processor An electronic device having a connector to which is connected,

An information processing apparatus comprising:

In the additional control device,

A communication means for receiving data from an external device;

A second processor that performs processing different from that of the first processor; and at least a processing procedure that the second processor executes on data received via the communication means. A second storage means,

Information processing device provided with.

2. The information processing apparatus according to claim 1, wherein

The data received from the outside by the communication means includes data different in properties from data that can be processed by the first processor of the electronic device,

An information processing apparatus in which a procedure for processing data having different properties is stored in the second storage means.

3. The information processing apparatus according to claim 1, wherein

An information processing apparatus including: a processing information output unit that outputs information related to the processing of the data to the electronic device while the second processor is performing the processing on the data. .

4. The information processing apparatus according to claim 3, wherein

The processing information output means includes information on data processing, An information processing device that outputs at least one of the quantity, the name of the data being processed, the remaining processing time, and error information in the additional control device.

5. The information processing apparatus according to claim 3, wherein

The electronic device includes a display unit that displays predetermined information,

An information processing apparatus comprising: a data display unit that receives information output by the processing information output unit and displays the information on the display unit.

6. The information processing apparatus according to claim 1, wherein

An information processing apparatus, comprising: an information output unit configured to output information of an electronic device to the additional control device.

7. The information processing apparatus according to claim 6, wherein the information output by the information output means includes operation information of an operation unit provided in the electronic device.

8. The information processing apparatus according to claim 6, wherein

A signal line connected to a connector of the electronic device, the signal line including at least a part of an address signal line of the first processor;

The information processing output means is means for reflecting information to be output on an address to be accessed and performing read processing on the address.

An information processing device, comprising: an information extracting unit configured to extract information included in the address in response to the reading process from the first processor.

9. The information processing apparatus according to claim 1, wherein

The additional control device,

R A M that memorizes the program and

Program expansion means for expanding the data received by the communication unit as a program in the RAM;

The control of the second processor is transferred to a predetermined address of the expanded program. Control transfer means to pipe

Information processing device provided with.

10. The program expanded in the RAM is a program for debugging the additional control device, a program for modifying a processing procedure for data processing stored in the second storage means, and a program for modifying the data. 10. The information processing apparatus according to claim 9, wherein at least one of the programs realizes a processing procedure having a higher function than the processing procedure for processing.

1 1. The information processing apparatus according to claim 1, wherein

The additional control device includes a connector capable of adding memory,

The connector is equipped with a ROM storing a processing procedure to be executed on the data received through the communication means or a memory having a RAM capable of storing data, and the like. Information processing device.

1 2. The information processing apparatus according to claim 1, wherein

The additional control device includes third storage means for storing processing executed by a first processor of the electronic device,

The electronic device is provided with means for transferring control of the first processor at a predetermined timing to processing stored in the third storage means in the additional control device.

Information processing device.

13. An electronic device including a first processor capable of performing a logical operation and first storage means for storing processing executed by the processor, via a connector provided in the electronic device. An additional control device to be connected,

A communication means for receiving data from an external device;

A second processor that performs processing different from that of the first processor, and a processing procedure that the second processor executes on data received via the communication unit are reduced. A second storage means that also memorizes, Data output means for outputting the data processed by the second processor to the electronic device;

Additional control device with

14. The additional control device according to claim 13, wherein

The data received from the outside by the communication means includes data different in properties from data that can be processed by a first processor of the electronic device,

The additional control device, wherein a procedure for processing data having different properties is stored in the second storage means.

15. The additional control device according to claim 13, wherein

The additional control device includes a processing information output unit that outputs information on the processing of the data to the electronic device while the second processor is performing the processing on the data. .

16. The additional control device according to claim 15, wherein

The additional control device, wherein the processing information output means outputs at least one of the amount of processed data, the name of the data being processed, and the remaining processing time as information relating to data processing.

17. An electronic device including a first processor capable of performing a logical operation, first storage means for storing processing to be executed by the processor, and an operation unit operated by a user. An additional control device connected via a connector provided in

A communication means for receiving data from an external device;

A second processor that performs processing different from that of the first processor, and at least a processing procedure that the second processor executes on data received via the communication means. A second storage means,

Data output means for outputting the data processed by the second processor to the electronic device; Operation information receiving means for receiving, when the electronic device outputs operation information obtained by operating the operation unit,

Response processing execution means for causing the second processor to execute predetermined processing according to the received information;

Additional control device with

18. First processor capable of logical operation, first storage means for storing processing executed by the processor, and at least a part of an address signal line of the first processor An additional control device connected via the connector to an electronic device having a connector connected to the electronic device;

A communication means for receiving data from an external device;

A second processor that performs processing different from that of the first processor;

A second storage unit that stores at least a processing procedure executed by the second processor for data received via the communication unit;

Information extraction means for extracting information included in the address in response to a read process for the address performed by the electronic device by reflecting information to be output in the address;

An additional control device comprising:

1 9. The additional control device according to claim 13, wherein

R A M, which memorizes programs,

Program development means for developing the data received by the communication unit into the RAM as a program,

Control transfer means for transferring control of the second processor to a predetermined address of the expanded program;

Additional control device with

20. The program expanded in the RAM is a program for debugging the additional control device, a program for modifying a processing procedure for data processing stored in the second storage means, and a data processing. 20. The additional control device according to claim 19, wherein at least one of the programs realizes a processing procedure having a higher function than the processing procedure for use.

2 1. The additional control device according to claim 1, wherein

Equipped with a connector that can add memory,

The connector is equipped with a ROM storing a processing procedure to be executed on data received via the communication means or a memory card having a RAM capable of storing data and the like. Additional control device.

22. The additional control device according to claim 13, wherein

A third storage unit for storing a process executed by a first processor of the electronic device,

Means for transferring control of the first processor at a predetermined timing to processing stored in the third storage means in the additional control device is provided.

Additional control device.

23. A first processor capable of performing a logical operation, an electronic device including first storage means for storing processing executed by the processor, and a first processor connected to the electronic device via a connector; An information processing method performed in cooperation with an additional control device including a second processor that performs processing separately from the first processor,

In the additional control device,

Receives data from external devices via communication,

The second processor performs processing on the data received by the previous communication according to the processing procedure stored in the second storage means readable from the second processor;

An information processing method for outputting data processed by the second processor to the electronic device.

24. The information processing method according to claim 23, wherein

An information processing method, wherein a procedure for processing data having different properties is stored in the second storage means.

25. The information processing method according to claim 23, wherein

An information processing method in which, on the side of the additional control device, information about processing of the data is output to the electronic device while the second processor is processing the data.

26. The information processing method according to claim 25, wherein

The processing information output means outputs at least one of the amount of processed data, the name of the data being processed, the remaining processing time, and the error information in the additional control device as information relating to data processing. Information processing method.

27. An electronic device comprising: a first processor capable of performing a logical operation; first storage means for storing processing executed by the processor; display means capable of displaying predetermined information; An information processing method which is connected to a device via a connector and cooperates with an additional control device including a second processor which performs processing different from the first processor, and

On the additional control device side,

Receives data from external devices via communication,

The second processor performs processing on the data received by the communication according to the processing procedure stored in the second storage means readable from the second processor. ,

Outputting the data processed by the second processor to the electronic device, While the second processor is performing processing on the data, outputting information on the processing of the data to the electronic device;

The electronic device receives the information output by the additional control device, and displays the information on the display unit.

Information processing method.

28. The information processing method according to claim 23, wherein the electronic device outputs information on the electronic device side to the additional control device.

29. A first processor capable of performing a logical operation, first storage means for storing processing to be executed by the processor, an electronic device having an operation unit operated by a user, and a connector connected to the electronic device And an additional control device having a second processor for performing processing separate from the first processor, the information processing method being performed in cooperation with the first processor. Outputting operation information of the operation unit to the additional control device side;

Storing the operation information output by the electronic device,

Receives data from external devices via communication,

The second processor refers to the stored operation information and performs a processing procedure stored in a second storage unit readable from the second processor. Perform processing on the data received by the communication,

30. A first processor capable of performing a logical operation, an electronic device provided with first storage means for storing processing executed by the processor, and a read-only bus from the electronic device side An information processing method that is connected through a connected connector and cooperates with an additional control device including a second processor that performs processing separately from the first processor,

On the electronic device side, an address to access information to be output And perform read processing for the address,

The additional control device extracts information included in the address in response to the reading process from the first processor.

Information processing method.

31. The information processing method according to claim 23, wherein

The additional control device,

The data received by communication is expanded as a program on the RAM that stores the program,

The control of the second processor is transferred to a predetermined address of the expanded program.

Information processing method.

32. The program developed in the RAM is a program for debugging of the additional control device, a program for modifying a processing procedure for data processing stored in the second storage means, and a program for data processing. 31. The information according to claim 31, wherein at least one of the programs realizes a processing procedure having a higher function than the processing procedure for use, and the second processor executes the processing. Processing method.

33. The information processing method according to claim 23, wherein

A memory card is attached to a connector provided in the additional control device, and the data received through communication is stored in accordance with the processing procedure stored in R0M in the memory card. An information processing method for performing processing and expanding data to be processed in RAM in the memory card.

34. The information processing method according to claim 23, wherein

The electronic device transfers control of the first processor to a process stored in third storage means provided in the additional control device at a predetermined timing.

Information processing method.

35. The information processing apparatus according to claim 1, wherein

The electronic device is a printer that expands print data received from outside and performs printing,

The additional control device is a cartridge mounted on the connector of the printer,

An information processing apparatus storing an interpreter of a page description language for interpreting print data received via the communication means and developing image data;

36. The information processing apparatus according to claim 35, wherein

An information processing apparatus, comprising: a video signal output unit that outputs, as a video signal, image data expanded in the second storage unit.

37. The information processing apparatus according to claim 35, wherein

The information processing apparatus, further comprising: a display device for displaying the image data developed in the second storage means on a housing of the additional control device.

38. An additional control device as set forth in Claim 13 wherein:

It is mounted in the form of a cartridge on a connector of an electronic device that is a printer that expands and prints print data received from the outside.

The second storage means includes an additional control device storing a page description language interpreter for interpreting print data received via the communication means and developing image data.

39. The additional control device according to claim 38, wherein

An additional control device comprising video signal output means for outputting the image data developed in the second storage means as a video signal.

40. The additional control device according to claim 38, wherein

An additional control device, comprising: a display device for displaying the image data expanded in the second storage means on a housing thereof.

41. The information processing method according to claim 23, wherein

An additional control device mounted in the form of a cartridge at the connector of the electronic device interprets print data received from the outside by communication using a page description language interpreter stored therein, and outputs an image. Unpack the data,

The electronic device receives the image data and performs printing,

Prior to printing of the image, the image data is displayed at a predetermined resolution on a display provided in a housing of the additional control device.

Information processing method.