WO1993025033A1 - Fsk transmission system - Google Patents
Fsk transmission system Download PDFInfo
- Publication number
- WO1993025033A1 WO1993025033A1 PCT/US1993/004878 US9304878W WO9325033A1 WO 1993025033 A1 WO1993025033 A1 WO 1993025033A1 US 9304878 W US9304878 W US 9304878W WO 9325033 A1 WO9325033 A1 WO 9325033A1
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- WO
- WIPO (PCT)
- Prior art keywords
- digital data
- signal
- transmission medium
- differentiator
- data stream
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
Definitions
- This invention relates to the field digital data communication, and more particularly to a high-speed digital data transmitter/receiver system.
- a digital data communications device receives digital data from a computer and converts the data into an analog form suitable for transmission over standard telephone lines.
- the step of converting the data from digital to analog typically involves using the digital data to modulate some aspect (e.g., amplitude, frequency, phase) of an analog carrier signal.
- a modem must also be capable of receiving an analog signal from a telephone and line and demodulating the signal to extract the digital information therein.
- the term modem will be used to generally denote devices capable of providing an interface between a source of digital data and an analog transmission medium. While the most common example of this is a computer modem, as previously noted, it is to be understood that there are numerous and diverse applications other than computer data transfer which involve the
- Frequency shift keying is one common modulation method used for data communication.
- frequency shift keying which is a type of frequency modulation (FM)
- FM frequency modulation
- two signals, called carriers are used to represent two different digital values, "0" and "1". For example, a "0" bit could be represented by a low-frequency carrier, while a " 1 " bit could be designated by a higher-frequency carrier. From six to ten cycles at a given frequency may be required to represent a given bit.
- FM and FSK modems are used almost exclusively for asynchronous transmission at bit- transfer rates of up to approximately 1800 bits per second (BPS), but are rarely used over 600 BPS.
- FSK modems are among the smallest and least expensive to build, and are not very noise sensitive. Therefore, they are well-suited for all low-speed transmissions, especially for computer terminals or personal-computer oriented applications, where the software has been designed for generating and transmitting asynchronous characters.
- a digital data transmission system including a receiver and transmitter.
- the transmitter is adapted to produce an output pulse stream of substantially square pulses, with l's in the data stream being represented by a single cycle of a square wave having a first frequency F, and O's being represented by two successive cycles of a square wave having a second frequency, 2F, that is twice as fast as the first.
- both O's and l's are transmitted in a time slot or bit cell of duration T.
- the transmitter is further adapted to insert framing bits at regular intervals, for example after every data bit, or after every two data bits; in the disclosed embodiment, framing bits (l's) are inserted after every data bit.
- the sequence of pulses produced by the transmitter is applied to an analog transmission medium, such as a telephone line, down-hole logging cable, or the like, and carried to a receiver in accordance with the present invention.
- an analog transmission medium such as a telephone line, down-hole logging cable, or the like
- the square pulse signal may be severely distorted; nonetheless, the modulation scheme in accordance with the disclosed embodiment of the invention is quite insensitive to such distortion effects, so that even a severely distorted signal can provide the necessary digital information at the receiving end.
- the receiver in accordance with the disclosed embodiment of the invention first filters the transmitted signal, and then applies the signal to two series-connected differentiators. The resulting signal is then applied to a level comparator, with excursions of the filtered and differentiated signal which exceed a predetermined threshold being interpreted as l's.
- the framing bits in the transmitted signal enable the receiver to synchronize itself with the transmission rate of the transmitter. Bit cells in which no excursion over the predetermined threshold occurs are interpreted as O's.
- Figure 1 is a block diagram of a digital data transmitter in accordance with one embodiment of the present invention.
- FIG. 2 is a block diagram of a digital data receiver in accordance with one embodiment of the present invention.
- Figure 3 is a schematic diagram of the transmitter from Figure 1 ;
- Figure 4 is a schematic diagram of the receiver from Figure 2;
- Figure 5 is a diagram showing an output signal from the transmitter of Figures 1 and 3; and Figure 6 is a diagram showing a signal which results from filtering and twice differentiating the signal of Figure 5 after transmission on an analog transmission medium.
- Transmitter 10 of Figure 1 comprises: a parallel-to-serial converter 20, a clock generator 21, a framing bit combiner 22, a one bit generator 24 and zero bit generator 26, a serial data combiner 28, and a line driver 30.
- Parallel-to-serial converter 20 operates to convert a parallel bit stream of, for example, four, eight, or sixteen bits, into a serial data stream.
- Framing bit combiner 22 inserts framing bits into the serial data stream in every second, third, fourth, or fifth bit position.
- clock generator 21 produces two signals, designated IX CLOCK and 2X CLOCK, which are applied to one bit generator 24 and zero bit generator 26.
- the IX CLOCK and 2X CLOCK signals are preferably 256-kHz and 512-kHz clock signals, respectively, and are synchronous with respect to one another.
- One bit generator 24 generates one 256-kHz pulse for each high data bit in the data stream.
- Zero bit generator 26 generates two 512-kHz pulses for each low data bit in the data stream.
- the pulses generated by one bit generator 24 and zero bit generator 26 are combined by serial data combiner 28, and applied to line driver 30.
- Line driver 30 thus produces an output pulse stream on line 3 IT, which may then be coupled to an analog transmission medium, such as a phone line, a down-hole cable or the like.
- Receiver 12 in Figure 2 comprises: a line interface transformer 32, an amplifier 34,- a high-cut filter 36, a low-cut filter 38, a first stage differentiator 40 and a second stage differentiator 42, a level comparator 44, a data stretcher 46, a one bit detector 48, a clock divider 50, a real data clock 52, a serial-to-parallel converter 54, a parallel data latch 56, and a data ready indicator 58.
- An incoming digital data signal is applied to line interface transformer 32 on line 31R.
- Amplifier 34 is a high-speed single or dual stage op-amp based amplifier in standard inverting amplifier configuration (for the single stage version). Amplifier
- High-cut filter 36 is an active filter which, in the presently disclosed embodiment of the invention has a 3-db point at approximately 250-kHz. The roll-off is gradual, so that sufficient signal in the frequencies of interest is available. If an higher-order filter (e.g., eighth) were used, the roll-off "knee" would have to be higher so as not to affect the 250-kHz area.
- Low-cut filter 38 eliminates potential
- filter 38 has a "knee” at approximately 100-kHz.
- Filter 38 is preferably implemented as a higher-order design. A sharper “knee” for filter 38 improves the noise immunity of receiver 12, since the "knee” can be placed closer to the frequency region of interest. Filter 38 also provides a small amount of gain
- First stage differentiator 40 is, in the presently disclosed embodiment of the invention, a simple, classical version. In an alternative embodiment contemplated by the inventor, differentiator 40 may be more elaborate. In accordance with an important aspect of the present invention, differentiator 40 converts the received 0 signal into a -signal corresponding in amplitude to the slope of the received signal. Second stage differentiator 42 equalizes the varying amplitude of the signal presented by differentiator 40. As will be appreciated by one of ordinary skill in the art, phase shifts introduced into the signal by differentiators 40 and 42 are immaterial, since clock information has not yet been extracted from the signal.
- the output from differentiator 42 is a complex, generally oscillatory signal which undergoes substantially higher- magnitude excursions during bit cells containing "1" data and relatively lower- magnitude excursions during bit cells containing "0" data.
- Level comparator 44 operates to distinguish between the larger excursions of the output signal from differentiator 42 associated with “1” data from the smaller excursions of the signal associated with “0” data.
- level comparator 44 defines a voltage threshold which is exceeding only by the larger excursions associated with “ 1 " data and not by the smaller excursions associated with “0” data.
- Data stretcher makes pulses produced at the output of level comparator 44 consistent in length, preferably slightly longer than one-half of a 256-kHz clock cycle.
- a high frequency receiver clock 49 produces a clock signal with a frequency fifty to one-hundred times the frequency of data transmission; for example, clock 49 with a frequency of 12.8-mHz would be suitable where data is transmitted at a 256- kHz rate.
- One's detector 48 is a one-shot which provides a reset pulse to real data clock circuit 52.
- clock divider circuit 50 and real data clock circuit 52 function to provide a clock signal with a jitter component constantly adjusting to the transmitted data stream. This allows receiver 12 to maintain synchronization with transmitter 10.
- Serial to parallel converter 54 uses the real data clock output signal to strobe data bits into a storage register. The width of the parallel output word can be from four to thirty-two bits.
- Parallel data latch 56 strobes the parallel data from converter 54 into a latch on the next clock period after the last bit is loaded into converter 54.
- the data ready indicator circuit 58 indicates, for example to an associated microprocessor or microcontroller (not shown in the figures) that data is ready to be parallel-loaded into memory.
- Data ready indicator circuit 58 asserts its DATA READY output signal for half the length of time required to load the serial to parallel shift register 54.
- DATA READY At 256-kHz, an 8-bit register loads in about 32-mSec; at this rate, the DATA READY signal would be asserted for approximately 16-mSec.
- FIG 3 a schematic diagram of the transmitter 10 from Figure 1 is shown.
- a listing of each of the components of transmitter 10 shown in Figure 3 is provided in the following Table 1. It will be appreciated that the descriptions of components in each of the Tables below are standard parts numbers and the like of commercially- available components readily recognizable to those of ordinary skill in the art.
- FIG. 4 a schematic diagram of receiver 12 from Figure 2 is shown. A listing of each of the components of receiver 12 shown in Figure 4 is provided in the
- transmitter 10 receives a parallel digital data word at the DATA input to parallel to serial converter 20.
- Transmitter 10 functions to produce a square wave output pulse stream on line 3 IT.
- a "1" bit is inserted into the data stream as a "framing bit" for each n data bits transmitted.
- FIG 5 the output pulse stream corresponding to that produced on line 3 IT for the data sequence 0110 is shown.
- the pulse stream of Figure 5 begins with a single 256-kHz pulse, corresponding to a first framing bit (" 1 ”) in bit cell 1, followed by two 512-kHz pulses corresponding to the first data bit ("0") in bit cell 2. Another • 256-kHz framing bit (“ 1 ”) pulse appears in bit cell 3, followed by another 256-kHz pulse corresponding to the second data bit (“1 ”) in bit cell 4.
- Bit cells 5 through 7 each contain single 256-kHz pulses corresponding to a third framing bit (" 1 "), third data bit (“ 1 "), and fourth framing bit (“ 1 "), respectively.
- bit cell 8 two 512-kHz pulses corresponding to the fourth data bit ("0") are contained in bit cell 8. It should be noted with reference to Figure 5 that although the respective 256- kHz and 512-kHz pulses are depicted as having a nearly ideal square shape, a certain 5 amount of rounding of the signal should be expected to exist in an actual system. Moreover, once the signal of Figure 5 has been conducted along an analog transmission medium, it is likely to undergo significant distortion due to the complex impedance of the transmission medium. It has been found by the inventor, however, that the presently disclosed embodiment of the invention is quite insensitive to even
- the signal of Figure 5 after having been subjected to the effects of the transmission medium so as to render it much distorted, is received on line 31R in receiver 12 of Figure 2.
- the signal is then filtered and applied to two stages of differentiation, as previously described with reference to Figure 2. The two stages
- level comparator 44 which defines a positive threshold voltage.
- level comparator 44 defined a threshold at a level corresponding to dashed line 70 in Figure 6, excursions which exceed this threshold level can be interpreted as l's. Since framing bits are provided in regular, periodic
- receiver 12 can synchronize itself to the transmission rate, and can thereby determine when the signal shown in Figure 6 fails to exceed the threshold level 70 for an entire bit cell. This is properly interpreted as a 0 in the transmitted data stream.
- a data transmission system in accordance with the present embodiment of the invention may be utilized in a variety of different applications, including high-speed facsimile (FAX) communication, multiplexing communication on a radio link, high-speed computer modem communication, subsea acoustic range finding, subsea acoustic depth sounding, sea bottom profiling, radio direction finding, radio range finding, and acoustic source and receiver systems for downhole seismic applications.
- FAX facsimile
- multiplexing communication on a radio link high-speed computer modem communication
- subsea acoustic range finding subsea acoustic depth sounding
- sea bottom profiling radio direction finding, radio range finding, and acoustic source and receiver systems for downhole seismic applications.
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Abstract
A high-speed digital data transmission system for transmitting a serial stream of digital data over an analog transmission medium. Binary 1's in the data stream are represented by one cycle of a square wave of frequency F, while binary 0's in the data stream are represented by two cycles of a square wave of frequency 2F. The digital data stream is thus converted into a series of square pulses and applied to the analog transmission medium. At the receiving end, the transmitted signal is first filtered, and then twice differentiated. The twice differentiated signal is then applied to a level comparator, with each excursion of the signal over a predetermined threshold being interpreted as a binary 1. Framing bits are inserted at regular intervals (e.g. after every N bits, where N » 1) into the data stream prior to conversion of the digital data into a stream of square pulses. The framing bits define a time slot comprising one or more bit cell intervals. When no excursion over the predetermined threshold occurs during a particular bit cell interval, this is interpreted by the receiver as a binary zero.
Description
FSK transmi ssion system
This invention relates to the field digital data communication, and more particularly to a high-speed digital data transmitter/receiver system. In the field of digital data communication, there have been shown a wide variety of methods for transmitting digital data at high speeds over an analog transmission medium. One of the more common examples of a digital data communications device is a computer modulator-demodulator (modem), which receives digital data from a computer and converts the data into an analog form suitable for transmission over standard telephone lines. The step of converting the data from digital to analog typically involves using the digital data to modulate some aspect (e.g., amplitude, frequency, phase) of an analog carrier signal. Of course, a modem must also be capable of receiving an analog signal from a telephone and line and demodulating the signal to extract the digital information therein. As used herein, the term modem will be used to generally denote devices capable of providing an interface between a source of digital data and an analog transmission medium. While the most common example of this is a computer modem, as previously noted, it is to be understood that there are numerous and
diverse applications other than computer data transfer which involve the
communication of digital data, including subsea acoustic range finding and depth sounding, sea bottom profiling, radio direction finding and range finding, acoustic downhole seismic applications, and so on. Frequency shift keying (FSK) is one common modulation method used for data communication. In frequency shift keying, which is a type of frequency modulation (FM), two signals, called carriers, are used to represent two different digital values, "0" and "1". For example, a "0" bit could be represented by a low-frequency carrier, while a " 1 " bit could be designated by a higher-frequency carrier. From six to ten cycles at a given frequency may be required to represent a given bit. FM and FSK modems are used almost exclusively for asynchronous transmission at bit- transfer rates of up to approximately 1800 bits per second (BPS), but are rarely used over 600 BPS. FSK modems are among the smallest and least expensive to build, and are not very noise sensitive. Therefore, they are well-suited for all low-speed transmissions, especially for computer terminals or personal-computer oriented applications, where the software has been designed for generating and transmitting asynchronous characters.
In accordance with one embodiment of the invention, a digital data transmission system including a receiver and transmitter is provided. The transmitter is adapted to produce an output pulse stream of substantially square pulses, with l's in the data stream being represented by a single cycle of a square wave having a first frequency F, and O's being represented by two successive cycles of a square wave having a second frequency, 2F, that is twice as fast as the first. The period T= 1/F
of the first frequency defines a time slot or "bit cell" with one bit being transmitted during each bit cell. Since the second frequency is twice the first frequency, and since two cycles at the second frequency are produced to represent a "0" while only one cycle at the first frequency are produced to represent a "1", both O's and l's are transmitted in a time slot or bit cell of duration T. The transmitter is further adapted to insert framing bits at regular intervals, for example after every data bit, or after every two data bits; in the disclosed embodiment, framing bits (l's) are inserted after every data bit.
The sequence of pulses produced by the transmitter is applied to an analog transmission medium, such as a telephone line, down-hole logging cable, or the like, and carried to a receiver in accordance with the present invention. During transmission over the analog medium, the square pulse signal may be severely distorted; nonetheless, the modulation scheme in accordance with the disclosed embodiment of the invention is quite insensitive to such distortion effects, so that even a severely distorted signal can provide the necessary digital information at the receiving end.
The receiver in accordance with the disclosed embodiment of the invention first filters the transmitted signal, and then applies the signal to two series-connected differentiators. The resulting signal is then applied to a level comparator, with excursions of the filtered and differentiated signal which exceed a predetermined threshold being interpreted as l's. The framing bits in the transmitted signal enable the receiver to synchronize itself with the transmission rate of the transmitter. Bit
cells in which no excursion over the predetermined threshold occurs are interpreted as O's.
The foregoing and other aspects of the present invention will be best appreciated with reference to the detailed description of a specific embodiment of the invention, which follows, when read in conjunction with the accompanying drawings, wherein:
Figure 1 is a block diagram of a digital data transmitter in accordance with one embodiment of the present invention;
Figure 2 is a block diagram of a digital data receiver in accordance with one embodiment of the present invention;
Figure 3 is a schematic diagram of the transmitter from Figure 1 ;
Figure 4 is a schematic diagram of the receiver from Figure 2;
Figure 5 is a diagram showing an output signal from the transmitter of Figures 1 and 3; and Figure 6 is a diagram showing a signal which results from filtering and twice differentiating the signal of Figure 5 after transmission on an analog transmission medium.
In Figure 1, there is shown a block diagram of a data transmitter 10 in accordance with one embodiment of the present invention. A block diagram of a corresponding data receiver 12 in accordance with the one embodiment of the invention is shown in Figure 2.
Transmitter 10 of Figure 1 comprises: a parallel-to-serial converter 20, a clock generator 21, a framing bit combiner 22, a one bit generator 24 and zero bit generator 26, a serial data combiner 28, and a line driver 30.
Parallel-to-serial converter 20 operates to convert a parallel bit stream of, for example, four, eight, or sixteen bits, into a serial data stream. Framing bit combiner 22 inserts framing bits into the serial data stream in every second, third, fourth, or fifth bit position. In Figure 1, clock generator 21 produces two signals, designated IX CLOCK and 2X CLOCK, which are applied to one bit generator 24 and zero bit generator 26. In the presently disclosed embodiment of the invention, the IX CLOCK and 2X CLOCK signals are preferably 256-kHz and 512-kHz clock signals, respectively, and are synchronous with respect to one another.
One bit generator 24 generates one 256-kHz pulse for each high data bit in the data stream. Zero bit generator 26 generates two 512-kHz pulses for each low data bit in the data stream. The pulses generated by one bit generator 24 and zero bit generator 26 are combined by serial data combiner 28, and applied to line driver 30. Line driver 30 thus produces an output pulse stream on line 3 IT, which may then be coupled to an analog transmission medium, such as a phone line, a down-hole cable or the like.
Receiver 12 in Figure 2 comprises: a line interface transformer 32, an amplifier 34,- a high-cut filter 36, a low-cut filter 38, a first stage differentiator 40 and a second stage differentiator 42, a level comparator 44, a data stretcher 46, a one bit detector 48, a clock divider 50, a real data clock 52, a serial-to-parallel converter 54, a parallel data latch 56, and a data ready indicator 58.
An incoming digital data signal is applied to line interface transformer 32 on line 31R. Amplifier 34 is a high-speed single or dual stage op-amp based amplifier in standard inverting amplifier configuration (for the single stage version). Amplifier
34 is direct-coupled to the secondary of transformer 32. 5 High-cut filter 36 is an active filter which, in the presently disclosed embodiment of the invention has a 3-db point at approximately 250-kHz. The roll-off is gradual, so that sufficient signal in the frequencies of interest is available. If an higher-order filter (e.g., eighth) were used, the roll-off "knee" would have to be higher so as not to affect the 250-kHz area. Low-cut filter 38 eliminates potential
IX) noise sources on the low end of the frequency spectrum. In the presently disclosed embodiment of the invention, filter 38 has a "knee" at approximately 100-kHz. Filter 38 is preferably implemented as a higher-order design. A sharper "knee" for filter 38 improves the noise immunity of receiver 12, since the "knee" can be placed closer to the frequency region of interest. Filter 38 also provides a small amount of gain
15 which is used to enhance the signal.
First stage differentiator 40 is, in the presently disclosed embodiment of the invention, a simple, classical version. In an alternative embodiment contemplated by the inventor, differentiator 40 may be more elaborate. In accordance with an important aspect of the present invention, differentiator 40 converts the received 0 signal into a -signal corresponding in amplitude to the slope of the received signal. Second stage differentiator 42 equalizes the varying amplitude of the signal presented by differentiator 40. As will be appreciated by one of ordinary skill in the art, phase shifts introduced into the signal by differentiators 40 and 42 are immaterial, since
clock information has not yet been extracted from the signal. In accordance with an improtant aspect of the present invention, and as will be hereinafter described in greater detail with reference to Figures 5 and 6, the output from differentiator 42 is a complex, generally oscillatory signal which undergoes substantially higher- magnitude excursions during bit cells containing "1" data and relatively lower- magnitude excursions during bit cells containing "0" data.
Level comparator 44 operates to distinguish between the larger excursions of the output signal from differentiator 42 associated with "1" data from the smaller excursions of the signal associated with "0" data. In particular, level comparator 44 defines a voltage threshold which is exceeding only by the larger excursions associated with " 1 " data and not by the smaller excursions associated with "0" data. Data stretcher makes pulses produced at the output of level comparator 44 consistent in length, preferably slightly longer than one-half of a 256-kHz clock cycle.
A high frequency receiver clock 49 produces a clock signal with a frequency fifty to one-hundred times the frequency of data transmission; for example, clock 49 with a frequency of 12.8-mHz would be suitable where data is transmitted at a 256- kHz rate.
One's detector 48 is a one-shot which provides a reset pulse to real data clock circuit 52. In accordance with common practice in the data transmission art, clock divider circuit 50 and real data clock circuit 52 function to provide a clock signal with a jitter component constantly adjusting to the transmitted data stream. This allows receiver 12 to maintain synchronization with transmitter 10.
Serial to parallel converter 54 uses the real data clock output signal to strobe data bits into a storage register. The width of the parallel output word can be from four to thirty-two bits. Parallel data latch 56 strobes the parallel data from converter 54 into a latch on the next clock period after the last bit is loaded into converter 54. The data ready indicator circuit 58 indicates, for example to an associated microprocessor or microcontroller (not shown in the figures) that data is ready to be parallel-loaded into memory. Data ready indicator circuit 58 asserts its DATA READY output signal for half the length of time required to load the serial to parallel shift register 54. At 256-kHz, an 8-bit register loads in about 32-mSec; at this rate, the DATA READY signal would be asserted for approximately 16-mSec.
Turning now to Figure 3, a schematic diagram of the transmitter 10 from Figure 1 is shown. A listing of each of the components of transmitter 10 shown in Figure 3 is provided in the following Table 1. It will be appreciated that the descriptions of components in each of the Tables below are standard parts numbers and the like of commercially- available components readily recognizable to those of ordinary skill in the art.
TABLE 1
PART DESCRIPTION IC1T SN74HC244 Octal Buffer / Line Driver
IC3T SN74HC166 Parallel / Serial In - Serial Out Shift Register
IC11TA SN74HC20 Dual 4-input NAND
IC11TB
IC5TA SN74HC74 Dual D-type Flip-Flop IC5TB
IC8TA SN74HC21 Dual 4-input AND
IC8TB
IC9TA SN74HC21 Dual 4-input AND
IC9TB IC4TA SN74HC04 Hex Inverters
IC4TB
IC4TC
IC4TD
IC4TE
IC4TF
IC12TA SN74HC04 Hex Inverters
IC12TB
IC12TC
IC12TD
IC12TE
IC12TF
IC7TA - SN74HC123 Dual Monostable Multivibrators
IC7TB
IC6T SN74HC4040 12-Bit Binary Counter
R5T MEPCO/ELECTRA Film Resistor ~ 61.9-kΩ, 1%
R6T MEPCO/ELECTRA Film Resistor ~ 61.9-kΩ, 1%
C5T Capacitor, 50-V, 100-pF
C6T Capacitor, 50-V, 400-pF
IC10T SN74HC32 Quad 2-input OR
REG1T LM317 Voltage Regulator
IC15T MC14504 Level Converter
R7T MEPCO/ELECTRA Film Resistor ~ 33.2-kΩ, 1%
R8T MEPCO/ELECTRA Film Resistor - 33.2-kΩ, 1%
R9T MEPCO/ELECTRA Film Resistor - 33.2-kΩ, 1%
RIOT MEPCO/ELECTRA Film Resistor - 33.2-kΩ, 1%
RUT MEPCO/ELECTRA Film Resistor - 24.9-Ω, 1%
R12T MEPCO/ELECTRA Film Resistor ~ 24.9-Ω, 1%
R13T MEPCO/ELECTRA Film Resistor ~ 24.9-Ω, 1%
R14T MEPCO/ELECTRA Film Resistor - 24.9-Ω, 1%
C1T Monolithic Capacitor, 15-V, 1-μF
C2T Monolithic Capacitor, 15-V, 1-μF
C3T Monolithic Capacitor, 15-V, 1-μF
C8T Monolithic Capacitor, 15-V, 1-μF
C9T Monolithic Capacitor, 15-V, 1-μF
C4 Monolithic Capacitor, 15-V, 0.1-μF
C7T Monolithic Capacitor, 15-V, 0.1-μF
C10T Monolithic Capacitor, 15-V, 0.1-μF
CUT Monolithic Capacitor, 15-V, 0.1-μF
C12T Monolithic Capacitor, 15-V, 0.1-μF
C13T Monolithic Capacitor, 15-V, 0.1-μF
C14T Monolithic Capacitor, 15-V, 0.1-μF
C15T Monolithic Capacitor, 15-V, 0.1-μF
C16T Monolithic Capacitor, 15-V, 0.1-μF
C17T Monolithic Capacitor, 15-V, 0.1-μF
C18T . Monolithic Capacitor, 15-V, 0.1-μF
C19T Monolithic Capacitor, 15-V, 0.1-μF
C20T Monolithic Capacitor, 15-V, 0.1-μF
C21T Monolithic Capacitor, 15-V, 0.1-μF
C22T Monolithic Capacitor, 15-V, 0.1-μF
C23T Monolithic Capacitor, 15-V, 0.1-μF
C24T Monolithic Capacitor, 15-V, 0.1-μF
C25T Monolithic Capacitor, 15-V, 0.1-μF
C26T Monolithic Capacitor, 15-V, 0.1-μF
Q1TA IRFG6113 HEXFET Array
Q1TB
Q1TC
Q1TD
TFORM1 Transformer
R1T MEPCO/ELECTRA Film Resistor ~ 100-Ω, 10-W, 1%
R2T MEPCO/ELECTRA Film Resistor ~ 3.09-kΩ, 1%
R3T MEPCO/ELECTRA Film Resistor - 249-Ω, 1%
JIT DIL 16-pin Connector 300-MIL Layout
J2T DIL 16-pin Connector 300-MIL Layout
The correspondence between the block diagram of Figure 1 and the schematic diagram of Figure 3 is summarized in the following Table 2:
TABLE 2
COMPONENTS
IC1T, IC3T, IC4TA, IC4TB, IC6T,
IC11TB, IC7T, R5T, C5T, R6T, C6T
IC5TA, IC11TA
IC10TA
IC4TC, IC8TA, IC9TB
IC4TE, IC4TD, IC8TB, IC9TA
IC10TB, IC10TC, IC12TD, IC12TE
Q1TA, Q1TB, Q1TC, Q1TD, R7T, R8T, R9T, RIOT, RUT, R12T, R13T, R14T, TFORM1T
In Figure 4, a schematic diagram of receiver 12 from Figure 2 is shown. A listing of each of the components of receiver 12 shown in Figure 4 is provided in the
following Table 3:
TABLE 3
PART DESCRIPTION
IC2R LT1037AMJ8 Linear Tech High-Speed Op-Amp
IC3R LT1037AMJ8 Linear Tech High-Speed Op-Amp
IC4R LT1037AMJ8 Linear Tech High-Speed Op-Amp
IC5R LT1037AMJ8 Linear Tech High-Speed Op-Amp
IC1R OP37AMJ8 Linear Tech High-Speed Op-Amp
R2R MEPCO/ELECTRA Film Resistor - 10-kΩ, 1%
R14R MEPCO/ELECTRA Film Resistor - 10-kΩ, 1%
R17R MEPCO/ELECTRA Film Resistor - 10-kΩ, 1%
R18R MEPCO/ELECTRA Film Resistor - 10-kΩ, 1%
R19R MEPCO/ELECTRA Film Resistor - 10-kΩ, 1%
R1R MEPCO/ELECTRA Film Resistor ~ 1-kΩ, 1%
R12R MEPCO/ELECTRA Film Resistor - 1-kΩ, 1%
R13R MEPCO/ELECTRA Film Resistor - 10-kΩ, 1%
R15R MEPCO/ELECTRA Film Resistor ~ 10-kΩ, 1%
R4R MEPCO/ELECTRA Film Resistor - 15.8-kΩ, 1%
R3R MEPCO/ELECTRA Film Resistor - 330-kΩ, 1%
C3R 708D1AA030PG800AX MEPCO Polyester Foil Capacitor ~ 80-V
C1R Capacitor - 27-pF, 50-V
C2R Capacitor - 27-pF, 50-V
C5R Capacitor ~ 27-pF, 50-V
R5R MEPCO/ELECTRA Film Resistor ~ 5.95-kΩ, 1%
R6R MEPCO/ELECTRA Film Resistor - 5.95-kΩ, 1%
R16R MEPCO/ELECTRA Film Resistor - 5.95-kΩ, 1%
C4R 708D1AA151PG800AX MEPCO Polyester Foil Capacitor - 50-V
R7R MEPCO/ELECTRA Film Resistor ~ 11.9-kΩ, 1%
C6R Capacitor - 82-pF, 50-V
C7R Capacitor - 82-pF, 50-V
C10R Capacitor - 82-pF, 50-V
CUR Capacitor - 82-pF, 50-V
C12R Capacitor - 82-pF, 50-V
R8R MEPCO/ELECTRA Film Resistor - 7.8-kΩ, 1%
RlβR MEPCO/ELECTRA Film Resistor - 7.8-kΩ, 1%
R9R MEPCO/ELECTRA Film Resistor - 24.5-kΩ, 1%
R11R MEPCO/ELECTRA Film Resistor ~ 24.5-kΩ, 1%
C8R Capacitor ~ 20-pF, 50-V
C9R Capacitor ~ 20-pF, 50-V
R25R Potentiometer — 10-kΩ
Q1R 2N918 Small Signal NPN Transistor
IC7R SN74HC4040 12-Bit Binary Counter
IC14R SN74HC4040 12-Bit Binary Counter
IC17R SN74HC30 8-input NAND
IC18R. SN74HC30 8-input NAND
ICllRA SΝ74HC76 Dual J-K Flip-Flop
IC11RB
IC12RA SN74HC123 Dual Monostable Multivibrators
IC12RB
IC13RA SN74HC123 Dual Monostable Multivibrators
IC13RB
IC24RA SN74HC32 Quad 2-input OR
IC24RB
H1R DIL 16-Pin Connector 300-MIL Layout
H2R DIL 16-Pin Connector 300-MIL Layout
J2R DIL 16-Pin Connector 300-MIL Layout
TFORM1R Transformer
J1R DIL 14-Pin Connector 300-MIL Layout
The correspondence between the block diagram of Figure 2 and the schematic diagram of Figure 4 is summarized in the following Table 4:
Q1RD, R15R, IC12R, R17R, C10R, IC12RD, IC12RE, IC12RF
50 Clock Divider IC7R, IC8RA, IC8RB, IC8RC, IC8RD, IC17R, IC11RA, IC24RA, IC12RA, IC12RB, IC12RC, R18R, CUR
54 Serial to Parallel Converter IC16R 56 Parallel Data Latch IC14R, IC15RA, IC8RF, IC23R 58 Data Ready Indicator IC18R, IC15RB
Operation of transmitter 10 and receiver 12 can now be described with reference to the Figures. As previously noted with reference to Figure 1, transmitter 10 receives a parallel digital data word at the DATA input to parallel to serial converter 20. Transmitter 10 functions to produce a square wave output pulse stream on line 3 IT. In accordance with one aspect of the present invention, a "1" bit is inserted into the data stream as a "framing bit" for each n data bits transmitted. In the presently preferred embodiment of the invention, it is believed that one framing bit should be transmitted for each data bit (i.e., n = 1), although it is contemplated by the inventor that only one framing bit for every two or more data bits (i.e. , n = 2, 3, 4, etc..) may be necessary, depending upon such factors as the lossiness of the transmission medium. For the purposes of the presently disclosed embodiment, it will be assumed that one framing bit is inserted for each data bit (n= l). It is believed by the inventor that it would be a matter of routine for a person of ordinary skill in the design of digital circuits to adapt the disclosed embodiment of the invention to provide different framing bit numbers (n = 2 or more).
In Figure 5, the output pulse stream corresponding to that produced on line 3 IT for the data sequence 0110 is shown. The pulse stream of Figure 5 begins with a single 256-kHz pulse, corresponding to a first framing bit (" 1 ") in bit cell 1, followed by two 512-kHz pulses corresponding to the first data bit ("0") in bit cell 2. Another • 256-kHz framing bit (" 1 ") pulse appears in bit cell 3, followed by another 256-kHz pulse corresponding to the second data bit ("1 ") in bit cell 4. Bit cells 5 through 7 each contain single 256-kHz pulses corresponding to a third framing
bit (" 1 "), third data bit (" 1 "), and fourth framing bit (" 1 "), respectively. Finally, two 512-kHz pulses corresponding to the fourth data bit ("0") are contained in bit cell 8. It should be noted with reference to Figure 5 that although the respective 256- kHz and 512-kHz pulses are depicted as having a nearly ideal square shape, a certain 5 amount of rounding of the signal should be expected to exist in an actual system. Moreover, once the signal of Figure 5 has been conducted along an analog transmission medium, it is likely to undergo significant distortion due to the complex impedance of the transmission medium. It has been found by the inventor, however, that the presently disclosed embodiment of the invention is quite insensitive to even
1O the most severe instances of distortion.
Thus, the signal of Figure 5, after having been subjected to the effects of the transmission medium so as to render it much distorted, is received on line 31R in receiver 12 of Figure 2. The signal is then filtered and applied to two stages of differentiation, as previously described with reference to Figure 2. The two stages
15 of differentiation result in a signal such as is depicted in Figure 6. In particular, where a 256-kHz pulse corresponding to a " 1 " in the data stream is differentiated in receiver 12, a relatively large magnitude positive excursion (such as that shown in bit cell 1 in Figure 6) is produced. On the other hand, where two 512-kHz pulses corresponding to a "0" in the data stream is differentiated, a significantly smaller
-20 magnitude negative excursion (such as is shown in bit cell 2 in Figure 6) is produced.
As would be apparent to one of ordinary skill in the art, distinguishing between O's and l's in the received data stream can be accomplished by simply applying the signal of Figure 6 to level comparator 44, which defines a positive
threshold voltage. In particular, if level comparator 44 defined a threshold at a level corresponding to dashed line 70 in Figure 6, excursions which exceed this threshold level can be interpreted as l's. Since framing bits are provided in regular, periodic
bit cell positions, receiver 12 can synchronize itself to the transmission rate, and can thereby determine when the signal shown in Figure 6 fails to exceed the threshold level 70 for an entire bit cell. This is properly interpreted as a 0 in the transmitted data stream.
From the foregoing detailed description of a particular embodiment of the invention, it should be apparent that a method and apparatus for high-speed digital data communication has been disclosed. It has been the inventors' experience that the embodiment disclosed herein is operable at data transmission rates of at least 256- kBaud. It will be appreciated by those of ordinary skill in the art that higher or lower data transmission rates can be achieved in a data transmission system in accordance with the present invention, depending on the requirements on the system in a given application, and on such factors as the framing bit-to-data bit ratio, the characteristics of the particular analog transmission medium used, and so on. It is contemplated by the inventor that a data transmission system in accordance with the present embodiment of the invention may be utilized in a variety of different applications, including high-speed facsimile (FAX) communication, multiplexing communication on a radio link, high-speed computer modem communication, subsea acoustic range finding, subsea acoustic depth sounding, sea bottom profiling, radio direction finding, radio range finding, and acoustic source and receiver systems for downhole seismic applications.
Although a particular embodiment of the present invention has been disclosed herein in some detail, this has been done for the purposes of illustration only, and it is to be understood that this description is not intended to be limiting with respect to the claims, which follow. It is believed by the inventor that various substitutions, alterations, and modifications to the embodiment of the invention disclosed herein without departing from the spirit and scope of the invention as defined in the appended claims which follow.
Claims
1. A digital data transmission system for communicating a stream of digital data over an analog transmission medium, said transmission system comprising a transmitter and a receiver each coupled to said analog transmission medium, said transmitter comprising:
a modulator, responsive to a "1" in said digital data stream to produce an electrical square pulse of period T and responsive to a "0" in said digital data stream to produce two successive electrical square pulses of period T/2 in response to a "0" in said data stream;
a line driver, coupled to said modulator and to said analog transmission medium, said line driver adapted to transmit said square pulses onto said analog transmission medium;
said receiver comprising:
a line transformer, coupled to said analog transmission medium and adapted • to receive electrical signals from said transmission medium;
a filter circuit, coupled to said line transformer and adapted to bandpass filter said received electrical signals; a first differentiator circuit, having an input terminal and an output terminal, said input terminal coupled to said bandpass filter to receive said bandpass filtered electrical signals, said first differentiator adapted to produce a signal at its output terminal corresponding to a first differentiation of said bandpass filtered electrical signals;
a second differentiator, having an input terminal and an output terminal, said second differentiator input terminal coupled to said first differentiator output terminal, said second differentiator adapted to produce a signal at its output terminal corresponding to a second differentiation of said bandpass filtered electrical signals;
a level comparator, coupled to said second differentiator output terminal and adapted to assert an output signal when said output signal from said second differentiator exceeds a predetermined threshold;
a digital data register defining a plurality of bit positions, said digital data register coupled to said level comparator and responsive to assertion of said level comparator output signal to store a binary "1" in one of said bit positions.
2. A digital data transmission system in accordance with claim 1, further comprising:
a framing bit generator adapted to insert a "1" after every N bits of said digital data stream.
3. A digital data transmission system in accordance with claim 2, wherein N is one.
4. A method for transmitting a serial stream of digital data on an analog transmission medium comprising the steps of:
(a) generating one cycle of a square wave of frequency F in response to a " 1 " in said digital data stream;
(b) generating two cycles of a square wave of frequency 2F in response to a "0" in said digital data stream;
(c) applying said square wave cycles to said analog transmission medium, thereby producing a time- varying electrical signal on said transmission medium; (d) applying said electrical signal on said transmission medium to a bandpass filter circuit to produce a bandpass filtered signal;
(e) differentiating said bandpass filtered signal a first time to produce a once differentiated signal;
(f) differentiating said differentiated signal to produce a twice differentiated signal;
(g) storing a "1" in a data storage register when said twice differentiated signal exceeds a predetermined threshold.
A method in accordance with claim 4, further comprising the steps of:
(h) inserting a "1" after every N bits in said digital data stream.
A method in accordance with claim 5, wherein N is one.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US88732092A | 1992-05-22 | 1992-05-22 | |
| US07/887,320 | 1992-05-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1993025033A1 true WO1993025033A1 (en) | 1993-12-09 |
| WO1993025033A9 WO1993025033A9 (en) | 1994-01-20 |
Family
ID=25390908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1993/004878 WO1993025033A1 (en) | 1992-05-22 | 1993-05-24 | Fsk transmission system |
Country Status (2)
| Country | Link |
|---|---|
| AU (1) | AU4387593A (en) |
| WO (1) | WO1993025033A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6385257B1 (en) * | 1997-01-21 | 2002-05-07 | Sony Corporation | Frequency demodulating circuit, optical disk apparatus thereof and preformating device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3746794A (en) * | 1971-07-07 | 1973-07-17 | Univ Illinois | Modulator-demodulator apparatus for communication of digital data over voise grade telephone lines |
| US3924065A (en) * | 1974-04-05 | 1975-12-02 | Information Identification Inc | Coherent, fixed BAUD rate FSK communication method and apparatus |
| US4569060A (en) * | 1983-08-31 | 1986-02-04 | General Signal Corporation | FSK Coding method and apparatus involving multiples and submultiples of a given frequency |
-
1993
- 1993-05-24 AU AU43875/93A patent/AU4387593A/en not_active Abandoned
- 1993-05-24 WO PCT/US1993/004878 patent/WO1993025033A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3746794A (en) * | 1971-07-07 | 1973-07-17 | Univ Illinois | Modulator-demodulator apparatus for communication of digital data over voise grade telephone lines |
| US3924065A (en) * | 1974-04-05 | 1975-12-02 | Information Identification Inc | Coherent, fixed BAUD rate FSK communication method and apparatus |
| US4569060A (en) * | 1983-08-31 | 1986-02-04 | General Signal Corporation | FSK Coding method and apparatus involving multiples and submultiples of a given frequency |
Non-Patent Citations (1)
| Title |
|---|
| PATENT ABSTRACTS OF JAPAN vol. 9, no. 85 (E-308)(1808) 13 April 1985 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6385257B1 (en) * | 1997-01-21 | 2002-05-07 | Sony Corporation | Frequency demodulating circuit, optical disk apparatus thereof and preformating device |
Also Published As
| Publication number | Publication date |
|---|---|
| AU4387593A (en) | 1993-12-30 |
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