WO1993024997A1 - Digital signal receiver - Google Patents
Digital signal receiver Download PDFInfo
- Publication number
- WO1993024997A1 WO1993024997A1 PCT/JP1993/000682 JP9300682W WO9324997A1 WO 1993024997 A1 WO1993024997 A1 WO 1993024997A1 JP 9300682 W JP9300682 W JP 9300682W WO 9324997 A1 WO9324997 A1 WO 9324997A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- output
- digital signal
- receiving
- delay time
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
Definitions
- the present invention relates to an optical or electric digital signal receiving apparatus, and more particularly to a method for reducing a rise / delay time from input of a received signal to generation of an output signal.
- a digital signal input to the transmitter T shown in FIG. 1A (for example, a Munchister code as shown in row A of FIG. 2) S di is a rising edge of the modulation circuit 11 or a certain time thereafter. It is modulated into a pulse signal S m (B in Fig. 2) generated at a later timing.
- the output S m is input to the drive circuit 12, the output is supplied to the light emitting element 13, and the electric signal is the optical signal S. It is converted to P (B in Fig. 2) and incident on the transmission medium. This optical signal S.
- Figure 3 shows the transmission and reception processes described above using timing charts of signals at each stage, including the delay time of each circuit block.
- the input signal S di is the optical signal S.
- An object of the present invention is to reduce a delay time of a signal receiving device.
- an OR gate is added to the conventional receiving apparatus, an OR of the output of the receiving circuit and the output of the monostable multivibrator is obtained, and the output of the OR gate is used as the output of the receiving apparatus. Things.
- the OR gate has a shorter signal rise delay time than the monostable multivibrator, so the rise delay time of the receiver is reduced by that difference.
- Figure 1A is a block diagram of a conventional transmitter.
- Figure 1B is a block diagram of a conventional receiver.
- FIG. 2 is a waveform diagram of a main part of FIGS. 1A and 1B.
- Fig. 3 shows the timing chart of the signals in Figs. 1A and 1B.
- FIG. 4 is a block diagram of the receiver of the present invention.
- Fig. 5 is a timing chart of the signals in Fig. 1A and Fig. 4.
- FIG. 4 is a circuit block diagram of an embodiment of the digital signal receiving apparatus according to the present invention, and FIG. 5 rows A to E show timing charts of signals in respective units.
- an optical signal receiving apparatus is used, and an optical signal S is transmitted from the transmitter in FIG. 1A. P shall be received.
- the receiving circuit R has the same configuration as that shown in FIG. 1A.
- a pulse signal (such as a Munchister code) having a pulse width Tw shown in row A of FIG. 5 is input. Converted to a mining signal.
- the timing signal is applied to the light emitting element 13 to generate an optical signal S. It is converted to P (Fig. 5, line B) and incident on the transmission medium.
- Optical signal S from input signal S di Let the delay time to P be .
- This optical signal S. P is incident on the light receiving element 1 4 in the receiver of FIG. 4, the output of the amplifier circuit 1 5 through the comparator 1 6, 2 value Di digital signal S d is outputted from the receiving circuit R.
- the delay time from P to the receiving circuit output S d is defined as r 2 without including the delay of the transmission line.
- the receiving circuit output S d is multiplied by the trigger input terminal of the monostable multivibrator 17 and the receiving circuit output S d at the 0 org 18 input to the final OR gate 18.
- Piblator output S d (Fig. 5, line D) is added to the final output signal S. (Fig. 5, line E) Therefore, the rising edge of the output signal S is the two input signals S d and S d of OR gate 18. Ri determined by the earlier ones of, the gate delay becomes r 4.
- the delay of orgate 4 is smaller than the delay of monostable multivibrator 17 and 3; therefore, the total delay time of transmission and reception is ⁇ , ⁇ + r2 + r4, The delay time becomes smaller by 3 - ⁇ 4.
- the rise delay is 23 to 44 nsec.
- the gate delay is 5.5 to 8.5 nsec, so the delay can be reduced by 14.5 to 38.5 nsec. it can.
- the transmission signal of the transmission medium is an optical signal, but it is obvious that the present invention is not limited to the optical signal but may be an electrical signal.
- the output of the receiving circuit is set to the trigger signal.
- the addition of OR gate 18 can reduce the overall delay time r of the received signal.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Optical Communication System (AREA)
- Dc Digital Transmission (AREA)
- Pulse Circuits (AREA)
- Selective Calling Equipment (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP93910380A EP0600091A4 (en) | 1992-05-25 | 1993-05-24 | Digital signal receiver. |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4/132608 | 1992-05-25 | ||
JP4132608A JPH05327433A (en) | 1992-05-25 | 1992-05-25 | Digital signal receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1993024997A1 true WO1993024997A1 (en) | 1993-12-09 |
Family
ID=15085315
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1993/000682 WO1993024997A1 (en) | 1992-05-25 | 1993-05-24 | Digital signal receiver |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPH05327433A (en) |
CA (1) | CA2113898A1 (en) |
WO (1) | WO1993024997A1 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5299750U (en) * | 1976-01-26 | 1977-07-28 | ||
JPS6214467B2 (en) * | 1981-09-18 | 1987-04-02 | Tokyo Shibaura Electric Co | |
JPH0322745B2 (en) * | 1982-03-16 | 1991-03-27 | Hitachi Cable |
-
1992
- 1992-05-25 JP JP4132608A patent/JPH05327433A/en active Pending
-
1993
- 1993-05-24 WO PCT/JP1993/000682 patent/WO1993024997A1/en not_active Application Discontinuation
- 1993-05-24 CA CA002113898A patent/CA2113898A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5299750U (en) * | 1976-01-26 | 1977-07-28 | ||
JPS6214467B2 (en) * | 1981-09-18 | 1987-04-02 | Tokyo Shibaura Electric Co | |
JPH0322745B2 (en) * | 1982-03-16 | 1991-03-27 | Hitachi Cable |
Non-Patent Citations (1)
Title |
---|
See also references of EP0600091A4 * |
Also Published As
Publication number | Publication date |
---|---|
CA2113898A1 (en) | 1993-12-09 |
JPH05327433A (en) | 1993-12-10 |
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