WO1993024889A1 - Dispositif d'attribution de largeur de bande de bus de systeme adaptable - Google Patents

Dispositif d'attribution de largeur de bande de bus de systeme adaptable Download PDF

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Publication number
WO1993024889A1
WO1993024889A1 PCT/JP1993/000672 JP9300672W WO9324889A1 WO 1993024889 A1 WO1993024889 A1 WO 1993024889A1 JP 9300672 W JP9300672 W JP 9300672W WO 9324889 A1 WO9324889 A1 WO 9324889A1
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WIPO (PCT)
Prior art keywords
bus
bus master
coupled
controllers
system bus
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Application number
PCT/JP1993/000672
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English (en)
Inventor
Sameer S. Kanagala
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Publication of WO1993024889A1 publication Critical patent/WO1993024889A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control

Definitions

  • This invention pertains to the field of computing systems, and in particular to techniques for improving the allocation of usage of the available system bus bandwidth.
  • Fig. 1 illustrates the structure of most complex computers today which run multi-user operating systems (like
  • I/O input and output
  • system bus 4 typically comprising a set of parallel data lines and a set of parallel address lines .
  • System bus 4 might have 32 parallel data lines and 32 parallel address lines. Using binary arithmetic, this is enough to address 4 Gigabytes of data at random.
  • the computer system comprises a set of n central processing units (“CPUs”) 1, a set of m memory resources 2 , and a set of p bus masters ("BMs") 3, each of which is coupled to system bus 4.
  • Each BM 3 is associated with one or more system resources 5, which can include input/output controllers that are in turn coupled to input/output devices.
  • Typical system 1 resources 5 include fixed disk drives, fixed disk controllers, floppy disk drives, floppy disk controllers, magnetic tape drives, magnetic tape controllers, random access memory,
  • Each system resource 5 is associated with only one BM 3.
  • System bus 4 is a resource shared by all CPUs 1, memory resources 2 and BMs 3. Each of CPUs 1 and BMs 3 can request use of system bus 4.
  • 5 Process execution consists of CPU 1 execution and BM 3 execution (e.g., data transfer), which alternate.
  • FIG. 2B illustrates a histogram of CPU 1 and BM 3 system bus 4 bursts in a single process.
  • FIG. 2C illustrates a histogram of CPU 1 and BM 3 system bus 4 bursts in a multi-process environment.
  • Conventional multi-processing systems rely mostly on the available system bus 4 bandwidth to accommodate all the activity by the various CPUs 1 and BMs 3.
  • the time allocated to a CPU 1 or BM 3 for use of system bus 4 is proportional to the bandwidth.
  • any fixed scheme of allocating system bus 4 bandwidth results in poor utilization of system bus 4 bandwidth by creating "dead" bandwidth (when that CPU 1 or BM 3 granted use of system bus 4 does not need it, but at least one other CPU 1 or BM 3 does) and bottlenecks (when too many CPUs 1 and/or BMs 3 request system bus 4) .
  • System bus 4 allocation is extremely important because system bus 4 can become a bottleneck if inefficiently allocated.
  • Access to system bus 4 is regulated by system bus arbiter 6, which is coupled to all BMs 3 and CPUs 1.
  • system bus arbiter 6 which is coupled to all BMs 3 and CPUs 1.
  • any given CPU 1 may be given access to system bus 4 by default. That CPU 1 will thus have exclusive use of system bus 4 and all memory resources 2 attached to it.
  • each BM 3 is assigned a priority.
  • Each CPU 1 is also given a priority, which is usually lower than each BM 3 priority.
  • system bus arbiter 6 determines which receives access to system bus 4. Therefore, typically any CPU 1 must give up control of system bus 4 when any BM 3 requests to use system bus 4.
  • CPU 1 surrenders control of system bus 4 after completing the current instruction being executed.
  • CPU 1 can resume only when BM 3 completes its usage of system bus .
  • BMs 3 which are DMA devices or coprocessors typically are not intelligent and hence need a significant amount of programming and supervision by CPUs 1.
  • BMs . 3 when programmed by CPU 1 typically move large amounts of data over system bus 4 and thus take up a significant percentage of the overall system bus 4 bandwidth available.
  • BMs 3 are typically tied to system resources 5 such as input/output
  • I/O systems such as disk controllers and tape controllers.
  • Such system resources 5 are typically much slower than the internal speed of CPU 1.
  • CPU 1 has no control over system bus 4 usage by BMs 3 once they have been programmed. This results in poor system bus 4 bandwidth utilization and denies system bus 4 access to CPU 1, without which CPU 1 cannot schedule multiple
  • BMs 3 in a timely fashion, resulting in poor performance, particularly for I/O systems including disk drives.
  • Fig. 3 illustrates a typical BM 3. All the illustrated components are conventional, except for gas pedal
  • Each BM 3 typically comprises bus arbiter 15, source address pointer 16, destination address pointer 17, and byte counter 18.
  • Bus arbiter 15 is a set of logic that is duplicated in all of the other BMs 3.
  • the typical BM 3 is associated with one or more system resources 5.
  • Bus arbiter 15 stores priority information associated with system resources 5 and indicates to System bus arbiter 6 when BM 3 wishes to activate one of the associated system resources 5.
  • System bus arbiter 6 then determines which of the BMs 3 will be given authorization to 5 become operational, i.e., be given access to system bus 4. Only one BM 3 can be operational at any one time.
  • the way that a CPU 1 communicates with a system resource 5 is for that CPU 1 to place, typically, three pieces of information into the associated bus master 3: the source 10 address (the address for the location where the data comprising the subject of the communication is to be found) is stored in source address pointer 16; the address of the destination (location where the data is to be sent) is stored in address pointer 17; and the number of bytes desired to be moved or ⁇ j 5 otherwise operated upon is stored in byte counter 18. During the operational period, byte counter 18 decrements once during each transfer until the count stored therewithin reaches zero, at which point it is known that all of the data have been moved or operated upon. If CPU 1 wishes to perform operations such as 20 arithmetic, logic, or shift operations on the data in addition to simply moving them, this task can be performed by CPU 1 during the operational cycle, or by an optional logic unit in BM 3.
  • Fig. 2A illustrates a typical usage pattern for system 25 bus 4 over time.
  • System bus 4 is used by, just one CPU 1 or one BM 3 at a time. Also, there are periods when system bus 4 is idle, ie, when no CPU 1 or BM 3 requests access to system bus 4. 1
  • control is transferred to the lowest priority CPU 1.
  • System resource 5 missing a disk rotation, which costs a c relatively large amount of time, due to the slow mechanical rotation of the disk, and thereby slows the throughput of the computer system.
  • the present invention allows software teprogramming of bus masters 3 to enhance throughput of the computer system.
  • the present invention is a computer system comprising at least one central processing unit (CPU) (1) capable of performing operations on data stored within a set of system ⁇ resources (5) .
  • CPUs (1) are all coupled to a single system bus
  • At least one bus master (BM) (3) is also coupled to system bus (4) .
  • Each bus master (3) is coupled to at least one system resource (5) , and via system bus (4) to CPUs (1) .
  • bus arbiter (15) Within each bus master (3) is bus arbiter (15) , at least one address pointer
  • Gas pedal (19) comprises a software programmable register (21) coupled to both a throttle state machine (22) and an idle state machine (23) .
  • Idle state machine (23) is coupled
  • throttle state machine (22) which sends a tired signal (25) .
  • Idle state machine (23) receives a signal from system clock (24) and sends a wakeup signal (26) .
  • the present invention offers the following major advantages over the prior art:
  • System bus (4) can be allocated in a more efficient manner, reducing the amount of idle time.
  • the computer system can more easily adapt to system resources (5) which have differing complexities and/or data transfer rates, because system bus (4) is not hogged by the slowest system resources (5) .
  • bus masters (3) can be programmed to refrain from requesting system bus (4) as conditions warrant.
  • the CPUs (1) are given sufficient time on system bus (4) in order to reschedule bus masters (3) and perform other necessary tasks .
  • Host CPUs (1) dynamically update software programmable registers (21) without any timing restrictions.
  • bandwidth on system bus (4) to perform the cache look-up function, and when not found thereby, by enabling a faster bus master (3) to function between operational periods of a slower bus master (3) .
  • bus masters (3) and/or CPUs (1) compared to conventional systems can be coupled to system bus (4) without degrading performance.
  • Fig. 1 is a block diagram of the conventional prior art technique of communicating among CPUs (1) , bus masters (3) , and system resources (5), using system bus (4) .
  • Fig. 2A is a time-line diagram of typical system bus
  • Fig. 2B is a histogram of typical system bus (4) usage of the conventional prior art in a one-process environment.
  • Fig. 2C is a histogram of typical system bus (4) usage of the conventional prior art in a multi-processor environment.
  • Fig. 3 is a block diagram of a bus master (3) of the present invention.
  • Fig. 4 is a block diagram of gas pedal (19) of the present invention.
  • Fig. 5 is a time-line diagram of typical system bus (4) usage of the present invention.
  • Fig. 6 is a block diagram of a caching SCSI controller
  • Fig. 7 is a block diagram of an embodiment of the present invention in which gas pedal (19) has a scheduling prescaler (28) .
  • Fig. 8 is a block diagram of an embodiment of the present invention which illustrates interaction among software programmable register (21) , throttle state -machine (22) , idle state machine (23) , and scheduling prescaler (28) .
  • Fig. 9 is a block diagram of an embodiment of the present invention in which bus master (3) is a scalable coprocessor (9) .
  • Fig. 3 is a block diagram of a general embodiment of each bus master (BM) 3 which comprises a dynamically programmable means (gas pedal) 19 for determining whether that bus master 3 requests access to system bus 4.
  • BM bus master
  • gas pedal dynamically programmable means
  • Fig. 1 The environment is as in Fig. 1.
  • an adaptive system bus bandwidth allocator the allocation of the available bandwidth on system bus 4 is controlled by one or more CPUs 1 by dynamically (adaptively) programming each bus master 3.
  • Fig. 5 illustrates a typical system bus 4 bandwidth usage patern for bus master 3 using the present invention.
  • System resources 5 are coupled with bus masters 3, which in turn are coupled together via the same system bus 4.
  • System resources 5 comprise, typically, input/output controllers that are in turn coupled to input/output devices
  • Each system resource 5 has an associated sustained data transfer rate (ie. the maximum sustained rate at which data can be transferred by system resource 5 over system bus 4) .
  • One or more memories 2 are coupled together via system bus 4.
  • Each bus master 3 is coupled to the set of CPUs 1 via
  • System bus 4 comprises bus arbiter 15, at least one address pointer (e.g., source address pointer 16 and destination address pointer 17), byte counter 18, and gas pedal 19.
  • Gas pedal 19 comprises software programmable register 21 coupled to both throttle state machine 22 and idle state machine 23 (see Fig.
  • Pointers 16 and 17 are storage devices such as registers or programmable counters.
  • Idle state machine 23 is coupled to r
  • Idle state machine 23 receives a signal from system clock 24 and outputs a wakeup signal 26.
  • Software programmable register 21 is a means for storing information, such as a register or random access memory
  • RAM random access memory
  • Any CPU 1 granted access to the system bus 4 can place data into software programmable register 21 by, for example, means similar to those by which the CPU places data into source address pointer 16,
  • Throttle state machine 22 is programmable to allow the associated bus master 3 to perform only the programmed number of 1 data transfers or other operations on system bus 4 each time said bus master 3 is given access to system bus .
  • Idle state machine 23 is programmable to require the associated bus master c 3 to abstain from requesting use of system bus 4 for at least the programmed number of cycles of--system clock 24.
  • throttle state machine 22 allows each bus master 3 to perform 'a finite number of operations (corresponding 5 to a given finite number of data transfers) per operational authorization. 128 data transfers is a typical number. This may or may not be enough transfers to permit bus master 3 to - complete its assigned tasks. If it is enough, byte counter 18 decrements to 0 and bus arbiter 15 signals the system bus arbiter 6 that bus master 3 has relinquished control of system bus 4.
  • idle state machine 23 associated with that bus master 3 counts the pulses from system clock 24.
  • idle state machine 23 issues a wakeup signal 26 to bus arbiter 15, which in turn signals to system bus arbiter 6 that the associated bus master 3 requests usage of system bus 4.
  • bus master 3 becomes operational.
  • a CPU 1 will be given control of system bus 4. During this period, that CPU 1 can schedule the allocation of system bus 4 among the various bus masters 3 and
  • CPUs 1 which may use system bus .
  • CPU 1 determines how to allocate available system bus 4 bandwidth, and stores that information in software programmable register 21 in each bus master 3.
  • CPU 1 may use various factors in determining the information to be placed into software programmable register 21
  • CPU 1 can place information in software programmable register 21 based on the sustained data transfer rate of system resources 5 associated with bus master 3, the - sustained data transfer rates of system resources 5 associated with each other bus master 3 present in the system, the past contents of dynamically programmable register 21, the current contents of dynamically programmable register 21, the number of requests pending from those CPUs 1 requiring associated bus master 3 to become operational, the number of requests pending from CPUs 1 requiring each other bus master 3 present in the system to become operational, and user requirements and preferences.
  • CPU 1 will give a bus master 3 with relatively more pending requests greater access to system bus .
  • Software programmable register 21 may be logically divided such that one portion of its contents comprises information necessary for throttle state machine 22 (for example, information describing the finite number of operations or transfers which the associated bus master 3 may perform during an operational period) , and another portion of its contents comprises information necessary for idle state machine
  • Fig. 8 illustrates an embodiment of the invention in which software programmable register 21 is divided into data bins 81, each of which contains information for throttle state machine 22, idle state machine 23, or scheduling prescaler 28.
  • said data bins 81 can be of any size that is at least one bit, fig. 8 illustrates data bins 81 having one bit each.
  • throttle state machine 22 receives data only from data bins 81 which have been pre-selected to " contain data associated with that throttle state machine 22; likewise, idle state machine 23 receives data only from data bins 81 which have been pre-selected to contain data associated with that idle state machine 23, and scheduling ⁇ m p Vrescaler 28 receives data only 3 from data bins 81 which have been pre-selected to contain data associated with that scheduling prescaler 28.
  • the data contained in the data bins 81 may be coded. For example, if four data bins 81 are preselected to contain data associated with throttle state machine 23 (e.g., the number of data transfers or operations for which associated bus master 3 is allowed access to system bus 4) and each data bin 81 is one bit, then 0001 may indicate 128 data transfers or operations are to be performed during a throttle period.
  • throttle state machine 23 e.g., the number of data transfers or operations for which associated bus master 3 is allowed access to system bus 4
  • 0001 may indicate 128 data transfers or operations are to be performed during a throttle period.
  • Fig. 6 illustrates a preferred embodiment of the invention used in a SCSI controller 60 with cache memory 2.
  • the caching SCSI controller 60 comprises one CPU 1, two bus masters 3 (one coupled to a buffer 7, which in turn is coupled to an EISA bus 62; the other coupled to an integral number q SCSI devices 8 via a SCSI interface 61), and cache memory 2.
  • CPU 1, bus masters 3, and cache memory 2 are coupled via system bus 4.
  • Each bus master 3 contains a gas pedal 19.
  • the access time for retrieval of data from cache memory 2 is substantially faster than via SCSI interface 61.
  • CPU 1 will be given access to system bus 4 when no bus master 3 requests use of system bus 4.
  • CPU 1 is granted control of system bus 4 periodically, for example every 80 milliseconds. During this period, CPU 1 can re-allocate available system bus 4 bandwidth based upon conditions at that time, reserving to CPU 1 sufficient time to perform the required caching algorithm by, for example, increasing the idle time for one or more bus masters 3.
  • SCSI bus master 3(2) is scheduled allocation to system bus 4 that percentage of the time which corresponds to the percentage of data transfer requests which require data to be found on SCSI devices 8 (rather than in cache memory 2) .
  • Fig. 7 illustrates an embodiment of the invention wherein a scheduling prescaler 28 is used to further regulate system clock 24 signals to idle state machine 23, by e.g., sending one prescaled clock signal 27 for every programmed number of system clock 24 signals received. This enables CPU 1 to give greater access to system bus 4 to a bus master 3 where timing is critical.
  • bus master 3(2) must become active to retrieve the data from SCSI devices 8 and store said data in cache memory 2 via system bus 4. Thereafter, bus master 3(1) must become active to transfer the data thus retrieved from cache memory 2 to EISA bus 62 via system bus 4 and over buffer 7. Because the sustained data transfer rate of SCSI interface 61 is much smaller than the sustained data transfer rate for EISA bus 62, the two operations can be done quicker if CPU 1 can properly schedule the two bus masters 3.
  • CPU 1 may schedule system bus 4 usage such that once bus master 3(2) has transferred 500 Kilobytes of data, bus master 3(1) will be given access to system bus 4 to begin to transfer that data to EISA interface 62. In this manner, the transfer of 1 Megabyte of data using cache memory 2 is completed in almost the same amount of elapsed time as for a SCSI controller 60 without cache memory 2.
  • Fig. 9 illustrates an embodiment of the invention in which at least one bus master 3 is a scalable coprocessor 9, comprising a single register file 10 compartmentalized into at least two bins (channels) , each bin corresponding to a virtual coprocessor channel; and coupled to the register file 10 is a single actual coprocessor 33 for performing operations on the system resources 5, as more fully described in U.S. patent application serial no. 881,299 entitled Scalable Coprocessor, filed May 12, 1992, having the same inventor and assignee as the instant patent application, which patent application is hereby incorporated by reference into the instant application.

Abstract

Dans un système informatique, un dispositif programmable attribue l'utilisation d'un bus de système unique (4) permettant d'améliorer les communications entre un ensemble d'unités centrales de traitement (1) et un ensemble de bus maîtres (3) dont chacun est relié à une ou plusieurs ressources de système (5). Chaque bus maître (3) comprend un dispositif d'attribution programmable, appelé régulateur (19), et un registre programmable par logiciel (21), relié à un automate de régime (22) et à un automate de repos (23). Ce régulateur (19) gère les demandes du bus maître correspondant (3) pour l'utilisation du bus de système (4). Les modes de réalisation visés par la présente invention comprennent un contrôleur SCSI à antémémoire (60), un régulateur (19) comportant un générateur d'échelles d'ordonnancement (28) et un régulateur (19) utilisé dans un coprocesseur évolutif (9).
PCT/JP1993/000672 1992-05-22 1993-05-21 Dispositif d'attribution de largeur de bande de bus de systeme adaptable WO1993024889A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US88777592A 1992-05-22 1992-05-22
US07/887,775 1992-05-22

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WO1993024889A1 true WO1993024889A1 (fr) 1993-12-09

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0378070A2 (fr) * 1989-01-10 1990-07-18 Bull HN Information Systems Inc. Méthode et appareil pour limiter l'utilisation d'un bus asynchrone avec commande d'accès distribuée
US5051946A (en) * 1986-07-03 1991-09-24 Unisys Corporation Integrated scannable rotational priority network apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051946A (en) * 1986-07-03 1991-09-24 Unisys Corporation Integrated scannable rotational priority network apparatus
EP0378070A2 (fr) * 1989-01-10 1990-07-18 Bull HN Information Systems Inc. Méthode et appareil pour limiter l'utilisation d'un bus asynchrone avec commande d'accès distribuée

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN vol. 32, no. 8A, January 1990, NEW YORK, US page 293 'Programmable arbitration time' *
IBM TECHNICAL DISCLOSURE BULLETIN vol. 33, no. 9, February 1991, NEW YORK, US pages 102 - 106 'Mechanism for implementing preemptive priorities in dual bus networks' *

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