WO1993022759A1

WO1993022759A1 - Computer display system

Info

Publication number: WO1993022759A1
Application number: PCT/FI1993/000175
Authority: WO
Inventors: Jarmo Kurikko
Original assignee: Icl Personal Systems Oy
Priority date: 1992-04-24
Filing date: 1993-04-23
Publication date: 1993-11-11
Also published as: GB2281015A; GB2281015B; FI921869A0; FI921869A; FI91924C; AU3955793A; GB9421045D0; FI91924B

Abstract

The invention relates to a display system in a computer, comprising a video display unit and display adapter (19, 19, 21-22) controlled by a processor (1) over an address and data bus thereof. In the invention, a one-way or two-way serial data communication channel is established between the display unit and the display adapter, the data communication channel utilizing at least one standard video signal line. The display adapter (10) comprises a serial communication controller (100) comprising an addressable transmission shift register (101) to which data is written in blocks of at least one byte and from which data is transmitted over the data communication channel in serial form in synchronization with a transmission clock; and/or an addressable reception shift register (102) which receives data from the data communication channel in serial form in synchronization with a reception clock and from which data is read in parallel form in blocks of at least one byte.

Description

Computer display system

Field of the Invention

The invention relates to a computer display 5 system, comprising a video display unit and display adapter means controlling the display unit and con¬ nected to the display unit over at least one signal line intended for controlling the image displayed by the display unit, the display adapter means being 10 controlled by a processor over an address and data bus thereof.

Background of the Invention

The Applicant's co-pending FI Patent Application

15 914435 (unpublished on the priority date of the pre¬ sent patent application) describes a new method for controlling the display unit in a display system. In the method, a one-way or two-way data communication channel is established between the display unit and

20 means controlling it (a microcomputer and its display adapter) so that no separate dedicated signal lines are required for data communication, but the data communication is carried out by existing signals or signal lines, such as those otherwise (besides the

25 data communication mode) used for controlling the displaying of the image on the display unit or for the identification of the display unit, for example. Thus the display unit and the microcomputer are able to communicate with each other while the existing

30 equipment environment can be maintained to a great degree. A major advantage of this method is that i standard solutions can be utilized to a very great

_./ extent so as to minimize any extra costs and to main¬ tain full compatibility with the άe facto standards,

35 such as the VGA display standard. The embodiments

described by way of example in FI Patent Application 914435 require no new device components (changes in circuitry) on the display adapter (microcomputer) side, and, if desired, only a few additional compon- ents with insignificant extra costs are required on the display unit side. On the microcomputer and display adapter side, the establishment of the data communication channel according to the invention requires only a specific communication software by which the microcomputer controls the display adapter. During data communication the communication software ^• employs certain display adapter registers. To change the state of a desired video interface signal, the software writes to the registers, and to determine the state of a desired video interface signal, it reads the registers. The write register is e.g. a colour palette register (RAMDAC register) which changes the state of a certain analog video signal. The read register is e.g. a register indicating the output (0 or 1) of the level indicators of the analog video signal lines. The display unit varies the drive current of the monitored video signal line in accordance with the serial data so that the state of the identification bit of the level indicator register changes in accordance with the state of the data bits transmitted by the display unit. The communication software of the computer reads the state of the identification bit from the register at regular intervals, thus receiving the signal transmitted by the display unit. In the embodiments described by way of example in FI Patent Application 914435, however, the data communication capacity of the data commun- ication channel is limited at higher operating fre¬ quencies. This is mainly due to the fact that the microprocessor of the central unit of the computer is not able to poll the state of the above-mentioned identification bit (video level bit) of the display adapter circuit with a sufficient accuracy in time to enable the transfer of information at a high fre- quency, e.g. in synchronization with the horizontal deflection signal. This problem occurs especially in so-called multi-tasking environments (MS-Windows, OS/2, Unix, etc.), where the application/communication program does not always have free access to the identification bit in the time domain to poll it appropriately. Due to the limited transfer rate, the above-described methods have to use a lower transfer rate, e.g. data communication synchronized with the vertical deflection signal. The data transfer rate would thereby be 60 or 70 bits per second. In order to have a higher transfer rate, the vertical defection frequency can be increased but even so the transfer rate will be only about one tenth of that obtainable with data communication synchronized with the horizontal deflection signal. In addition, the image cannot be displayed on the screen during the data communication as the higher vertical deflection frequency is not suitable for image displaying. The synchronization of the data communication with the horizontal deflection signal requires that the data received from the display unit is read with such a high accuracy that it cannot be achieved in the arrangement described above by way of example.

Disclosure of the Invention

The object of the present invention is to provide a video display system for a computer, which system is capable of using a data communication system and data communication channel of the type described above even at transfer rates considerably higher than previously.

This is achieved by means of a computer video display system of the type described in the intro¬ ductory chapter, which according to the invention is characterized in that a one-way or two-way serial data communication channel is established between the display unit and the display adapter means _r the data communication channel utilizing at least one signal line intended for controlling the displaying of the image on the screen of the display unit, and the display adapter means comprising a serial communica¬ tion controller comprising an addressable transmission shift register to which data is written in blocks of several bits and from which data is transmitted over the data commun¬ ication channel in serial form in synchronization with a transmission clock; and/or an addressable reception shift register which receives data from the data communication channel in serial form in synchronization with a reception clock and from which data is read in parallel form in blocks of several bits.

In the invention, the display adapter means comprise a serial communication controller which controls the data communication carried out by the video interface signals so that transfer rates considerably higher than previously can be used. The serial communication controller comprises an addressable transmission shift register and/or an addressable reception shift register, depending on the direction of transmission and on whether a one-way or two-way transmission path is to be established. A processor (CPU) writes transmission data into the transmission register in blocks consisting of at least one byte. The transmission shift register transfers the data in the register to the data communication channel in serial form and in synchronization with an appropriate transmission clock. The serial communica¬ tion controller further comprises an addressable reception shift register which receives the data transmitted by the display unit in serial form from the data communication channel in synchronization with an appropriate reception clock. The CPU reads the data received at the reception shift register in parallel form in blocks consisting of at least one byte either in response to an interruption generated by the dis¬ play adapter or by regular polling. In the invention, the serial communication controller reads the state of the video interface signal to be monitored, e.g. the state of the above-mentioned identification signal, with a very high accuracy in the time domain, which accuracy is determined by the reception clock used. Instead, the CPU can read the received data at longer intervals than previously at an appropriate time without that the accuracy of reception is decreased. The invention increases the transfer capacity of a data communication channel using the video interface to such an extent that the transfer may also take place in synchronization with the horizontal de- flection signal. The data transfer rate may thereby vary within the entire horizontal deflection frequency range of the display unit, e.g. between 31 kHz and 78 kHz. The serial communication controller may be arranged to perform an asynchronous or a synchronous transfer, to use a higher-level communication protocol, and to packet the transferred data so that it will consist of a number of bytes which also contain information on correcting and/or detecting data transfer errors (parity, checksum, etc.). The invention also enables the establishment of a data communication channel complying with a transmission path standard, such as the I²C bus, by utilizing existing video interface signals.

By means of the invention, the data communica- tion channel according to FI Patent Application 914435 can be utilized for real-time control of the display unit and data communication concurrently with the normal display operation without that any inter¬ ferences appear on the screen. In the preferred embodiment of the invention, the serial communication controller is integrated in the display adapter circuit. In such a case it is possible to use existing signals with insignificant extra costs. A second alternative is to provide a separate serial channel circuit on the display adapter board for data communication. This alternative, how¬ ever, is not advantageous in price. A third altern¬ ative is to separate the interlaced transfer data from the video signals and forward the separated data to the existing data communication channels of the micro¬ computer, e.g. to the keyboard interface, mouse inter¬ face, serial communication port, etc.

Brief Description of the Drawings In the following, the invention will be de¬ scribed in more detail by means of illustrating embodiments with reference to the attached drawings, in which

Figure 1 is a block diagram illustrating a computer system with a display system according to the invention;

Figure 2 is a more detailed view of the inter¬ connection between a VGA display adapter and a colour display unit for realizing data communication accord- ing to the invention; Figure 3 illustrates a serial communication controller according to the invention when integrated in a VGA display adapter circuit;

Figure 4 illustrates the internal configuration of a colour palette circuit;

Figure 5 illustrates an embodiment in which the serial communication controller is a serial communica¬ tion port of the computer;

Figures 6 and 7 are timing diagrams illustrating data communication clocked by a horizontal deflection signal; and

Figure 8 is a timing diagram illustrating the sampling of a received serial signal in the embodiment of Figure 5.

Detailed Description of the Invention

Figure 1 shows a computer system in which a dis¬ play system according to the invention can be applied. The computer system comprises a central processing unit or processor (CPU) 1 to which a keyboard 2, a mouse 3 and a display system with an associated display unit 4 are connected. In addition to the display unit, the display system comprises a video display adapter 5, which is connected via a bus interface 6 to the CPU 1 of the computer. The display adapter comprises an image data memory 7, which contains information about the image to be displayed. The display adapter 5 generates a video signal VIDEO (which may consist of several different physical signals), which is applied to control the display unit 4.

Figure 2 shows in more detail the data trans¬ mission arrangement between a VGA display adapter 5 and a compatible display unit 4. The display adapter 5 is connected by an intermediate cable 9 to the display unit 4. The signals of the display unit interface of the VGA adapter comply with the standards, as de¬ scribed in the above-mentioned FI Patent Application 914435. Figure 2 shows only the signal lines necessary for the understanding of the invention, i.e. control lines 11, 12 and 13 for the red, blue and green colour; signal lines 14 and 15 for the horizontal and vertical deflection signals HSYNC and VSYNC of the display unit; and signal lines 16, 17 and 18 for the identification signals IDO - ID2.

On the side of the display adapter 5, the arrangement shown in Figure 2 corresponds to a typical VGA arrangement, in which the analog signals (R, G, B) used for the transmission of image information are controlled by a VGA adapter circuit 10, the image data memory 7, and the colour palette circuit 19 (a digital-to-analog conversion circuit, RAMDAC, a colour look-up-table, CLUT), as described in FI Patent Appli- cation 914435.

On the side of the display unit 4 (a colour display in this specific example), the arrangement of Figure 2 corresponds to a standard display arrangement except for the following two additional components for establishing the data communication channel according to the invention. First, a signal-level control circuit 23 is connected to the G line 12. The control circuit 23 causes a change in the level of the G sig¬ nal, which change can be detected by a level indicator 21 connected to the G line 12 on the display adapter side. Second, a level indicator 24 is connected to the G line on the display unit side. The level indicator 24 detects signal-level changes caused by the colour palette circuit 19 in the G signal. The output of the level indicator 24 is connected to a serial input 25a of a microcontroller 25 in the display unit, while the signal-level control circuit is controlled via a serial output 25b of the microcontroller.

The basic configuration and basic principles of the data communication connection established between the display unit 4 and the display adapter 5 via the standard video interface are thus such as described in FI 914435, which is referred to for more detailed description. The present invention improves the transfer capacity of the data communication channel of the type described above by improving the data transfer capa¬ city of the display adapter 5. This is achieved by providing the display adapter 5 with a separate serial communication controller designed especially for data communication.

In Figure 3, the serial communication controller 100 is integrated in a standard integrated VGA display adapter circuit 10 (such as Model 28800 of ATI Techno- logies Inc.), which comprises e.g. a conventional CRT adapter 107. The serial communication controller 100 comprises a serial transmission shift register 101, a serial reception shift register 102, a multiplexing means 106, a two-part colour index register 103, and a control logic 104. A combined output 30 of the level indicators 20, 21 and 22 arranged to monitor the level of the video signal lines R, G and B is in a first state when the level of one of the signal lines R, G, B exceeds a predetermined threshold level, and in a second state when the level of one of the signal lines R, G, B is below a predetermined threshold level. The output 30 is connected in a normal way to the input pin of the display adapter circuit 10, from where it is conveyed within the circuit 10 through the multi- plexing means 106 to the reception shift register 102. The data received from the display unit and contained in the signal 30 is inputted in the serial register 102 in synchronization with the horizontal deflection signal HSYNC acting as a sampling clock, as will be described with reference to Figures 6 and 7. After the entire 8-bit data byte has been received in the register 102, the control logic 104 of the controller 100 sends an interruption request IRQ9 to the CPU as an acknowledgement of the receipt of the data. As the result of the interruption request, the CPU reads the content of the register 102 in parallel form over a data bus 40. In addition to the reception of data, the serial communication controller 100 may perform data synchronization, serial-to-parallel conversion, and parity and checksum check-outs. The controller 100 may thereby contain one or more status registers in addition to the data register. The status bits of the status registers inform the communication software of the computer how the reception of data has succeeded. They may indicate a parity error, transfer error, protocol error, etc. The controller 100 may also generate the interruption request IRQ9 as a result of faulty reception. If the interruption request IRQ9 cannot be used or is not used for some other reason, the computer may regularly poll the content of the register 102.

At extremely high data transfer rates, a stack of several bytes may be provided in the serial com¬ munication controller 100, either as an extension of the reception register 102 or as a separate register in which the received information can be stored temporarily if the processor is not able to provide sufficiently rapid service for the interruption request IRQ9 or poll the content of the register 102 sufficiently rapidly. During transmission the microcomputer writes at least one outgoing data byte in parallel form in the transmission shift register 101 over the bus 40. In the shift register 101, the control logic 104 inserts the start, parity and termination bits into the data byte in accordance with the programming of the control registers of the control logic 104 of the controller 100. The data transmission may also utilize a higher- order protocol and packet the transmission so that it will consist of a number of bytes also containing information about the correction and/or detection of data transmission errors, such as parity, checksum, etc.

Data is transferred from the transmission register 101 in serial form in synchronization with the horizontal deflection signal HSYNC acting as a transmission clock. After the transmission of the entire 8-bit data byte, the control logic 104 sends the interruption request IRQ9 to the CPU. In the preferred embodiment of the invention, the serial bit stream from the register 101 is transferred through the multiplexing means 106 to control the two-part colour, index register 103 having two digital control values programmed therein. The control values cor- respond to the logical states "1" and "0" of the bits of the serial data from the register 101. The purpose of the colour index register 103 is to select the appropriate data byte (or word) to form an index within the RAM area of the colour palette circuit 19, which appears more clearly from Figure 4. In the preferred embodiment of the invention, the colour index register 103 contains two programmable registers the effective word length of which is selected so that it corresponds to the display mode used (generally 8 or 16 bits). When the state of the bit received from the register 101 is "1", the index register 103 applies the first control word (index) on the address line P0-P7 to the colour palette circuit 19. When the state of the bit is "0", the index register 103 applies the second control word. A direct D/A control to be described below enables the use of a one-part register 103 having a single programmable control value. The second control value of the register 103, corresponding to the second logical state, is fixed, e.g. a zero output.

The control byte received by the colour palette circuit 19 from the index register 103 (e.g. BT476 by Brooktree Inc) represents three parallel memory locations in the RAM portion of the circuit 19. The memory locations contain the final information (generally an 18- or 24-bit word) which directly controls three D/A converters supplying current for the R, G and B signal, respectively. The content of the addressed RAM memory location and thus the drive current of the analog signal have to be selected so that the voltage levels induced in the signals R, G and B will not exceed the threshold voltage of the level indicators 20, 21, 22 but will exceed the threshold voltage of the corresponding indicator 24 of the display unit 4 (Figure 2). In this way, data transmission can be realized concurrently in two directions. (For instance, the R signal is used for transmission, and the B signal for reception. The G signal can be reserved for the transfer of the syn- chronizing signal (composite video)).

Certain application programs may alter the values of the memory locations of the colour palette circuit 19, so that the index values stored in the colour index register 103 have to be altered accord- ingly. Therefore the colour index register has to be programmable and comprise two parts, i.e. it has to comprise a separate register for both logical values.

In order to avoid the above-mentioned problem with certain applications, it is also possible to use the overlay functions of certain colour palette circuits 19. The problem does not occur in the direct D/A control, where the RAM memory is bypassed, as shown in Figure 4. The control word P0-P7 from the index register 103 is passed by the three-part RAM memory 190 through a multiplexer 191 directly to three D/A converters 192, 193, 194. The multiplexer 191 applies the outputs of the memory 190 during the normal display mode and the data word P0-P7 during the direct D/A control to the converters 192-194. In the direct D/A control, the colour index registers com¬ prise 18 or 24 bits, depending on the length of the word of the D/A converters. Furthermore, the direct D/A control can be effected by an overlay function typical of certain colour palette circuits, in which the content of the overlay register 195, which can be written from the outside, can be selected by the multiplexer 191 for controlling the D/A converters 192, 193, 194. The direct D/A control may also be effected in arrangements where the circuit 19 is integrated in the circuit 10. An example of this type of integrated VGA circuit is the AVGA2 circuit by Acunos Inc.

Figure 6 illustrates the way in which outgoing serial data is positioned in time in an arrangement synchronized with the horizontal deflection signal. The control signals of the video display are normally formed as follows. The horizontal deflection period HPER means a period during which one horizontal line is scanned from the left to the right, and then returned to the beginning of the next horizontal line. The HPER comprises an active display period H_active, which defines a horizontal active image area on the screen and during which the image data read from the image memory is displayed; and a blanking period HBLANK which comprises at least a front porch HFP, a deflection pulse HSYNC and a back porch HBP. During the blanking period HBLANK the electron beam of the cathode ray tube is returned to the beginning of the next line. Correspondingly, the vertical deflection period VPER comprises periods V.-_Ctive, VBLANK, VFP, VSYNC and VBP (not shown). The display periods H_active and V_active define together the active image area, which is indicated by the reference B in the figure. In the invention, data is transmitted at a time instant when no image information is normally transferred to the screen (outside H--_Ct:ive), or the display operation is switched off during the transfer. A very common practice is to position the synchronizing pulse HSYNC at the beginning of the blanking period HBLANK in time though within the blanking period HBLANK. In accord¬ ance with Figure 6, the data bit to be transferred is transmitted over the transmission path (the cable) at the leading edge (front edge) of the deflection pulse HSYNC. Correspondingly, the data bit is read from the transmission path at the back edge of the syn¬ chronizing pulse HSYNC. This can be done due to variation in the transmission path delay, on account of which transmitted data can still be read from the transmission path at the reception end when the de- flection pulse HSYNC terminates, as shown in Figure 7. In the embodiment of Figures 6 and 7, one data bit is transmitted during each successive HSYNC pulse. If the transfer rate so achieved is too high for the computer or the display adapter 5 used, it can be decreased, if desired, by transmitting a data bit only at every second, third, fourth, etc., deflection pulse HSYNC. Correspondingly, the transfer rate can be increased by using more than one signal (R, G and B signals, for instance) during transmission concurrently in the same direction, i.e. parallel transmission paths.

Correspondingly, the transfer clock can be syn¬ chronized with the vertical deflection pulse VSYNC. Furthermore, any clock frequency can be used as transmission and reception clocks. Figure 5 shows an alternative arrangement in which data interlaced in the video signals R, G, B in time is separated from the video signals and connected to the existing data communication channels of the computer, such as the keyboard interface, the mouse interface, the serial port C0M1, etc. A sampling circuit 51 is thereby positioned on the display adapter board 5. The sampling circuit 51 samples the output signal 30 of the level indicators 20, 21, 22 in synchronization with the clock signal used in the data transmission, such as the horizontal deflection signal HSYNC, and converts it to an appropriate level. It then applies the sampled level-adjusted signal to the serial communication port C0M1 of the computer so as to process it by the standard serial communication controller provided in association with the port. The timing diagram of Figure 8 illustrates the sampling performed by the circuit 51. In the embodiment of Figure 5, the transmission section is realized by positioning a multiplexing circuit 52 in the bus P0-P7 between the display adapter circuit 10 and the colour palette circuit 19. By means of the multiplexing circuit 52, serial data coming from the port C0M1 via a buffer 53 during the pulse HSYNC and video in¬ formation coming from the display adapter 10 during the active display period H_aet:ive can be connected to the colour palette circuit 19. The control words from the register 53 thereby correspond to the content of the index register 103 shown in Figure 3. In place of the register 53, the serial data from the port C0M1 can be connected to the overlay input OVERLAY of the colour palette circuit 19 (Figure 4). Alternatively, the transmission can be performed by using a separate D/A converter circuit connected in parallel with the outputs of the circuit 19. A disadvantage of the procedure described above is that the data trans¬ mission reserves one of the serial communication ports of the computer. In most cases, the number of serial communication ports is limited.

It is also possible to position the serial communication controller 100 shown in Figure 3 as a separate circuit in the display adapter board 5 for the data communication purposes. The communication could be performed e.g. similarly as in Figure 5. This arrangement, however, requires separate components, and therefore it is not as advantageous as the integ¬ rated embodiment of Figure 3.

Even though the data communication has been described above mainly with reference to the video signals R, G and B, the data communication based on the serial communication controller may also be used for data communication on the other signal lines of the video interface, such as the deflection signal lines HSYNC and VSYNC, which is described by way of example in FI Patent Application 914435. The shift registers of the serial communication controller can thereby be connected (via an appropriate buffer means) directly to the signal line(s) used in the data com¬ munication. In the preferred embodiment of the inven¬ tion shown in Figure 3, where the serial communication controller 100 is integrated in the circuit 10, the transmission and reception registers 101, 102 are selectively connectable to any desired connection pin or internal unit of the circuit 10, such as the colour index register 103, by means of the programmable multiplexing means 106. For this reason, the video interface signals used in the data communication can be selected freely by software by varying the control value of the control register of the multiplexing means 106. The drawings and the description related to them are only intended to illustrate the present invention. In its details, the computer video display system according to the invention may vary within the scope of the attached claims.

Claims

Claims :

1. Computer display system, comprising a video display unit (4) and display adapter means (5) controlling the display unit and connected to the display unit over at leasτ one signal line intended for controlling the image displayed by the display unit, the display adapter means being controlled by a processor (1) over an address and data bus thereof, c h a r a c t e r i z e d in that a one-way or two- way serial data communication channel is established between the display unit (4) and the display adapter means (5), the data communication channel utilizing at least one signal line (11, 12, 13, 14, 15) intended for controlling the displaying of the image on the screen of the display unit, and the display adapter means comprising a serial communication controller (100) comprising an addressable transmission shift register (101) to which data is written in blocks of several bits and from which data is transmitted over the data commun¬ ication channel in serial form in synchronization with a transmission clock; and/or an addressable reception shift register (102) which receives data from the data communication channel in serial form in synchronization with a reception clock and from which data is read in parallel form in blocks of several bits.

2. Display system according to claim 1, c h a r- a c t e r i z e d in that the transmission and reception clock are synchronized with the horizontal or vertical deflection signal of the display unit.

3. Display system according to claim 1 or 2, c h a r a c t e r i z e d in that the serial communication controller (100) adds starting, parity and/or termination bits to the data to be transmitted from the shift register in accordance with a program¬ mable transfer protocol; is synchronized with the received data; and/or performs a parity check on the received data.

4. Display system according to claim 1, 2 or 3, c h a r a c t e r i z e d in that the serial commun¬ ication controller (100) forms the signal to be trans¬ mitted from the shift register (101) into a packet consisting of a number of data bytes preferably also containing error correction and/or synchronizing in¬ formation.

5. Display system according to claim 3 or 4, c h a r a c t e r i z e d in that the serial communication controller (100) contains a control means (104) generating an interruption for the computer (1) after the reception or transmission of a predetermined amount of data.

6. Display system according to any of the pre- ceding claims, c h a r a c t e r i z e d in that said data communication channel utilizes at least one sig¬ nal line (11, 12, 13) used in the transfer of video information and being connected on the side of the display adapter means (5) to the output of a digital- to-analog converter means (19), and that the serial communication controller (100) contains an addressable one-or two-part index register (103) applying a first or a second control value to the digital-to-analog converter means (19) in response to the status of the bit supplied by the transmission shift register (101), at least one of said control values being program¬ mable.

7. Display system according to any of the pre¬ ceding claims, c h a r a c t e r i z e d in that the serial communication controller (100) bypasses the colour conversion memory and controls the digital-to- analog converters of the digital-to-analog converter means directly.

8. Display system according to any of the preceding claims, c h a r a c t e r i z e d in that said data communication channel utilizes at least one signal line (11, 12, 13) used in the transmission of video information and connected on the side of the display adapter means (5) to a level indicator means (20, 21, 22) the output of which is in a first state when the level of the signal line is below a pre¬ determined threshold level and in a second state when the level of the signal line exceeds a predetermined threshold level, and that the serial signal received by the reception shift register (102) is formed from the output of the level indicator means (20, 21, 22) in synchronization with the reception clock.

9. Display system according to any of the pre¬ ceding claims-, c h a r a c t e r i z e d in that the serial communication controller (100) is positioned in an integrated display adapter circuit (10) or on the same circuit board as the integrated display adapter circuit.

10. Display system according to any of claims 1 to 8, c h a r a c t e r i z e d in that the serial communication controller is formed by the serial communication controller of a serial interface (C0M1) of the computer, and that the display system further comprises a data separation means (51) which separates the received serial data from the output signal of said level indicator means (20, 21, 22) in syn¬ chronization with the reception clock and applies the separated data to the serial communication controller.

11. Display system according to any of claims 1 to 8, c h a r a c t e r i z e d in that the serial communication controller (100) is positioned in an integrated display adapter circuit (10), and that the serial communication controller comprises programmable selection means (106) for selectively connecting the transmission and reception registers to any desired connection pin or internal unit in the display adapter circuit.