WO1993022720A2 - Procede de production du nombre inverse d'un diviseur par approximation progressive - Google Patents

Procede de production du nombre inverse d'un diviseur par approximation progressive Download PDF

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Publication number
WO1993022720A2
WO1993022720A2 PCT/AT1993/000074 AT9300074W WO9322720A2 WO 1993022720 A2 WO1993022720 A2 WO 1993022720A2 AT 9300074 W AT9300074 W AT 9300074W WO 9322720 A2 WO9322720 A2 WO 9322720A2
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Prior art keywords
divisor
sign
quotient
circuit
cycle
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PCT/AT1993/000074
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German (de)
English (en)
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WO1993022720A3 (fr
Inventor
Cornell Vacariu
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Firma Johann Kamleithner
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Publication of WO1993022720A2 publication Critical patent/WO1993022720A2/fr
Publication of WO1993022720A3 publication Critical patent/WO1993022720A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5332—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4824—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices using signed-digit representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G06F7/537—Reduction of the number of iteration steps or stages, e.g. using the Sweeny-Robertson-Tocher [SRT] algorithm
    • G06F7/5375—Non restoring calculation, where each digit is either negative, zero or positive, e.g. SRT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
    • H03M7/06—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two

Definitions

  • the invention relates to a division method and a division circuit and in particular to a new method and a new circuit arrangement of symmetrical architecture for carrying out the bidirectional exact division by step-wise approximation, in several operating modes and formats.
  • Redundant representations such as the modified sign digit format (further referred to as MSD, from the English "odified sign digit”) are usually used to increase the throughput.
  • MSD modified sign digit format
  • ROM memory As described in the patent DE 38 32 796 (OS) "division circuit". Lookup tables with data which are dependent on the divisor or also on the divider are stored in these.
  • the ROM memories usually contain the reciprocal of the divisor, which acts as a multiplier on the dividends as a multiplicand by means of a multiplier.
  • the logarithmic values of the occurring operands are stored, the quotient also being generated by means of a ROM memory which contains the exponent values of the occurring data.
  • the object of the invention is therefore to maximize the computing speed, accuracy and generality of the division process in arithmetic units.
  • Another object of the invention is to do without tables / memories in the design of the division circuit.
  • the method according to the invention is suitable and applicable for a majority of forms of representation, as a result of which an increased degree of generality is achieved.
  • An increase in the computing speed results from the fact that no ROM memory look-up tables are necessary for the implementation of the method and no multiplications, but only addi operations must be carried out.
  • the computing time itself is not predetermined, but may be less than conventional methods for a fairly wide range of divisor values.
  • a partial quantity of digits of the reciprocal of the divisor is generated in each cycle.
  • B. can be used in advance for chained calculations.
  • the method directly generates the periodic fraction generated by the divisor, which enables an increased degree of accuracy in the calculation.
  • the method or the circuit arrangements executing the method can also be used or equipped with the same advantages and effects for a serial execution of the division process.
  • each addition will take place without a "carry-ripple" carry, starting from the second stage of the conventional MSD adders, so that the MSD adding circuits can be simplified and the sequence time is thereby greatly reduced. Furthermore, the comparison process of 2 numbers can be carried out more easily and the rounding process is immediate.
  • a preferred embodiment of the method is that when a '1' is recognized as the last total result, the cycle sequence is stopped.
  • the advantage here is that it can be recognized whether half or the entire period of the reciprocal has already been generated, depending on whether the sign of the last total result is the same or complementary as the sign of the divisor.
  • Another method for generating the reciprocal of a divisor is described by the features of claim 3. This method has all the advantages and effects of the method according to claim 1. In contrast to the method according to claim 1, however, the calculation is started with the lowest value. Nevertheless, the computing time of such a right-justified procedure is e.g. B. for the divisor range from '1' to '100' (in the decimal number system) on average only less than 1% greater than the computing time of the left-justified division process, both considered for an accuracy of 32 digits.
  • Another advantage of such a method starting at the least significant digit is that bi-directional methods are made possible.
  • a modification of the methods for generating the reciprocal of a divisor is described for the left-justified method by the features of claim 5 or for the right-justified method by the features of claim 6.
  • the particular advantages of these methods are that several digits of the reciprocal of the divisor can be generated in a single cycle. So z. B. if the 3rd and 5th multiple of the divisor is generated, in one cycle at least 3 digits of the reciprocal of the divisor, if the 7th and 9th multiple of the divisor is also generated, at least 4 digits of the reciprocal of the divisor.
  • a method for the bidirectional generation of the reciprocal of a divisor is formed by the features of claim 7.
  • the parallel use of the left-justified and right-justified division method increases the computing speed compared to a one-sided method.
  • the divisor can be normalized in a particularly advantageous manner by converting the divisor in MSD format in accordance with the display strategy of the “non-adjacent non-zero trits”, and since the divisor to to remove the leading zeros while simultaneously correcting the exponent.
  • a further development of the left-justified method for forming the reciprocal is formed by the characterizing part of claim 9 and allows to calculate at least one more digit of the reciprocal of the divisor in the cycle following the START cycle.
  • the features of claim 21 improve the accuracy of a method according to the invention for generating a quotient.
  • An exact division result can be recognized and the division process can then be stopped. This enables a reduction in the computing time. If the quotient is to be rounded after its calculation, an advantageous embodiment of the method is described by the features of claim 22. Since the quotient deviation of the generated quotient digits compared to the exact quotient value has a minimum absolute value due to the method, the rounding process is immediate.
  • Another object of the invention is to provide a circuit arrangement which is suitable for carrying out the method according to the invention.
  • a purely hardware-based division circuit of symmetrical architecture which generates the reciprocal of a divisor or a quotient of a dividend and a divisor by using a new division method, by stepwise approximation, recursively and optionally bidirectionally. This is possible in various operating modes and formats.
  • the division circuit can be used as a ROM memory simulator if the reciprocal of the divisor is generated.
  • the circuit arrangement can be used bidirectionally, the calculation being able to begin with the most significant or least significant bit / trit or simultaneously, in parallel, with the two extreme positions of the divisor / divider / quotient. Therefore, the arrangement is also suitable for serial processing of the data.
  • the circuit arrangement can have a symmetrical architecture, which consists of a left and a right part, corresponding to the processing beginning with the most significant or least significant bit / step.
  • the two symmetrical parts can work independently of one another, that is to say separately, with which it is possible to carry out two different exact division operations simultaneously using the two symmetrical halves. Work the two halves on one single dividends and divisor bidirectionally, the computing time is reduced. From this and from the peculiarity of possibly treating two different formats, the increased degree of generality of the designed division circuit arrangement also follows.
  • circuit arrangements have several advantages. Neither the multiplication between the divisor and the iteratively generated reciprocal of the divisor, see equation (1), nor the multiplication between the reciprocal of the divisor and the dividend and the calculation of the remainder of the division are necessary.
  • the sequence time is not fixed, as in most division circuits, but is dependent on the divisor value, in the sense that it can be smaller for a fairly wide range of divisor values.
  • An embodiment of the circuit arrangement according to the invention is characterized by the features of claim 29. If the divisor and dividend are shown in the redundant MSD format, the sign no longer has to be treated separately, since this is implicitly part of the operands shown in this format.
  • This redundant form of presentation has on the one hand the additional advantage that no "carry-ripple" transfer occurs when two summands are added, and on the other hand the rounding process is immediate since the generated quotient deviation is equal to that due to its possible positive or negative value corresponds to the minimum absolute value.
  • a possible exemplary embodiment of an MSD adder cell is shown in the patent specification EP 0 353 041 A2 "Signal processing apparatus and method using odified signed digital arithmetic" in FIG. In the same patent 2 shows a converter from MSD to NRF format.
  • a circuit arrangement according to the characterizing part of claim 30 is used to convert a conventional NRF data word into a new data format.
  • the advantage of this arrangement for implementation is that in the case of implementation with a gate combination as described in FIG ⁇ the minimum number of gates that can be found.
  • a further development of the invention according to the characterizing part of claim 32 offers the advantage that with the aid of the divisor multiple generator an average of two additional result digits can be generated per computing cycle.
  • a further embodiment of the division circuit according to the invention consists in that at least one of the adders of the division circuit according to claim 29 is formed by an adder for input numbers which are represented in MSD format according to a display strategy of the "non-adjacent non-zero trits".
  • This design simplifies the adders considerably compared to conventional MSD adders, which not only reduces the outlay on circuitry, but also shortens the computing time.
  • a development of the invention according to the characterizing part of claim 34 allows leading redundant zeros to be eliminated in a simple manner; furthermore, the comparison process of operands is facilitated and simplified MSD adders can be used.
  • a further development of the invention consists in the fact that, according to the characteristics of claim 36 and claim 37, the division circuit according to claim 32 has sign evaluation circuits which have the correct values of the extreme values Issue trits. In this embodiment, redundant zeros can also be recognized.
  • a circuit arrangement for rounding a number according to the characterizing part of claim 41 can be used universally.
  • it offers the advantage that the rounding process can take place immediately.
  • the absolute deviation of the quotient from the exact result that is to say the absolute value of the last remainder of the division, can be programmed to be smaller than a certain value "e":
  • 1 for the operands shown on 32 bits will be 32 in single precision or 64 in double precision.
  • the division circuit according to the invention can be carried out as follows:
  • the division circuit arrangement according to the invention is extensive since it contains an increased degree of generality. It contains an increased redundancy, since it is equipped with all factors that can reduce the computing time and is equipped with various possible operating modes. It is self-evident that this new method, or the circuit arrangement, with minor changes, can be used for almost all conventional areas. Depending on the specific field of application, the circuit arrangement can be minimized by taking into account the following parameters: number of bits of the operands (operand length), necessary computing speed, available circuit scope, working mode, structure of the interface for the supply of the operands and for the occurrence of the result, etc. According to the current state of the art and technology, there is a tendency towards parallel processing in order to obtain maximum time gain.
  • a minimal display redundancy which requires a correspondingly smaller amount of circuitry, is usually dispensed with in favor of saving time.
  • this is perfectly achievable in today's high technology, as a result of the greater degree of integration and density of the components within the microchips. This is in contrast to the previous tendency, which attempted to achieve a minimal circuit size by means of maximum minimization.
  • the advantage is that the computing speed, accuracy and generality increase significantly.
  • serial / parallel data processing systems digital real-time signal processing of the signals implemented by analog-digital converters or modulated by the delta function, digital filters, robot technology, spectral analyzers with FFT devices, speech and image recognition , Telecommunication technology (in serial, bidirectional working mode), encryption and decryption of the data, expert systems, CAD (for graphics, modeling, simulation and complex calculations in the field of physics, chemistry, biology etc.).
  • Fig.1 the block diagram of a division circuit of minimal, symmetrical architecture according to the invention, in any display format
  • Fig.4a and Fig.4b the block diagram of the left and right approximation circuit from Fig.3;
  • Fig.4c the structure of the adder circuits from Fig.4a and Fig.4b;
  • Fig.5a and Fig.5b circuits of the left and right divisor multiple generators from Fig.4a and Fig.4b;
  • Fig.5c the structure of the adder circuits from Fig.5a and Fig.5b;
  • Fig. 5f the circuit of a cell "i" of the strategic converter in the display strategy of the "non-adjacent non-zero trits" from Fig. 5c;
  • Fig.6a and Fig.6c circuits of the left and right comparison devices from Fig.4a and Fig.4b;
  • 6b shows a circuit for the recognition of a sequence of leading digits of the positive or negative square root of r 2 ⁇ , which is used in the first coincidence circuit from FIG. 6a;
  • Fig. 6d the circuit of a cell "i", which is used in the coincidence circuits of Figs. 6a and 6c;
  • Fig.7b - a slide correction circuit which ensures the necessary alignment operation from Fig.7a;
  • Fig.8a and Fig.8c circuits of the left and right coding devices of the reciprocal of the divisor from Fig.4a and Fig.4b, which can generate the reciprocal of the divisor;
  • Fig. 10 the same example as in Fig. 2, but with the operands converted into the MSD format and with an invented bidirectional implementation of the DivisionsVorgan ⁇ ges;
  • Fig. 12 - Table which contains the generated period lengths of odd-numbered divisors less than 100 (in the decimal number system) and their sign of deviation from the exact results;
  • Appendix 1 used signal names, arranged alphabetically;
  • Appendix 2 Circuits and signals used, arranged according to the identification number.
  • FIG. 1 has a block diagram of a division circuit of minimal, symmetrical architecture operating in NRF or MSD format.
  • NRF format numerical examples in NRF format are shown left-justified or right-justified execution of the division process in FIGS. 2a and 2b.
  • FIG. 10 in MSD format and with a parallel left-justified and right-justified execution of the division process, which shows the bidirectional character of the division process.
  • the division circuit consists of four parts, two of which are symmetrical.
  • the left main circuit 1, which is symmetrical with the right main circuit 3 processes the divisor and controls by means of the two control signals D / I and AS the left secondary circuit 2, which is symmetrical with the right secondary circuit 4 and the dividends processed to generate the quotient.
  • the right main circuit 3 Since the right main circuit 3 is symmetrical to the left main circuit 1, this was shown only by means of its distinguishing element, the right shift register 52, which, in contrast to the left shift register 50, ensures a right shift.
  • the right subcircuit 4 was also switched off using the right quotient shift sters 53 shown, which in contrast to the left Quotien ⁇ teschieberegister 51 secures a right shift.
  • the division process is carried out bidirectionally.
  • the entire circuit thus allows three operating modes: one bidirectional and two single-acting.
  • the divisor register 10 contains the divisor stored left-justified. Via a multiplexer 30, the divisor is fed directly or inverted to an adder circuit 40 as the first summand. The adder circuit 40 adds this value to the content of the left shift register 50, which is the second summand. The output sum signal is fed to the left shift register 50, which has the role of an accumulator register and contains the last sum result. . Furthermore, the zero detector 60 must recognize the leading zeros of the last total result in order to control the left shift of the register content 50 in accordance with its removal, by means of the signal AS. The shifted content of the left shift register 50 is fed back to the input terminal of the adder circuit 40 as a second summand. The generator of inverted divisor value 70 and multiplier register 80 are additional circuits which are not absolutely necessary for generating the quotient.
  • the signal Sc- will have the sign of the divisor. Depending on whether the divisor is a positive or negative number, Sc- takes the logical value '1' or '0'. At the beginning of the DivisionsVorgan ⁇ ges the logical value '1' is present at the START signal. This signal is supplied in negated form to an input of the NON-AND gate 23. The output signal D / I of the gate 23 is thus set to '1', as a result of which the multiplexer 30 selects and passes on the original value of the divisor (at the input '+'). The initial content of the left shift register 50 is '0'.
  • the sum signal of the adder circuit 40 will be the same as the divisor.
  • the divisor is loaded practically left-justified in the left shift register 50. Additions between the shifted content of the left shift register actually only start from the first cycle 50 as the second summand and the divisor with a direct or in the vertical original sign as the first summand.
  • the zero detector 60 detects the leading left-justified zeros of a last total result and accordingly it generates a signal AS for the alignment shift. After the left shifting of the content in the left shift register 50, a digit ⁇ tc-> which is designated as a sign will be at its most significant position, while the digit after the following will be a significant '1', since the leading zeros have been eliminated.
  • the digit ⁇ t ⁇ -_ > is fed to the modulo adder 22, which determines the coincidence with S ⁇ ») through the negated Signa OS.
  • the START signal drops to '0' so that the D / signal assumes the negated value of the negated OS signal, that is, OS.
  • This signal selects one of the two inputs of the multiplexer 30 in such a way that the result obtained in the adder circuit 40, the result obtained next, the last total result, should be as small as possible in the absolute value.
  • the process repeats until the content of the left shift register 50 contains a single '1' digit. This ends the first phase of the division process and the zero detector 60 generates the STOP signal. This produced half or all of the periodic breakage of the divisor, depending on the sign of the remaining '1' compared to the signal S ⁇ * ). If the two signs are the same, half, otherwise the entire periodic break was generated.
  • the above left-justified division process can also be described with the aid of the numerical example shown in FIG. 2a.
  • the upper part with the associated table shows the continuous cycles identified by cycle numbers with the associated values of the left shift and selection of the divisor (D / Ix,) that are assigned to them.
  • the divisor has, for example, the decimal who '641', which is implemented in the binary number system in NRF format is '1010000001'.
  • the left shift register 50 loads left the original value of the divisor. Since the diviso is a positive number, the signal S ⁇ > with the logical value '1' is applied.
  • the content of the first left-justified position value is always accepted by the zero detector 60 as '0' men.
  • the content of the left shift register 50 is shifted 2 places to the left in the first cycle.
  • the remaining content of the left shift register 50 '1000000100' is positive, i.e. xtc -_> is '0' and consequently:
  • the multiplexer 30 will pass the divisor to the adder circuit 40 with an inverse sign (input '-'), ie its two's complement.
  • the sum signal in the 2nd cycle has a negative value, equal to '1.110000011' in the two's complement representation. Its corresponding positive value would be r 0.001111101 '.
  • the zero detector 60 will assume the zeros of a corresponding positive number as' 0 f . If the number is negative, the leading '1' is assumed to be '0' by the zero detector 60.
  • This detection logic which determines the left shift value, can be summarized in the following table:
  • the divisor is a positive number that begins left-justified with a leading '11' combination.
  • the functionality of the circuit is not necessarily taken into account for "60 summarizes the zero detector the content of the left shift register 50 as negative on. In this way you could have a cycle of division organges save time-wise.
  • the left shift determined in the first cycle, for any leading combination of the divider have a value which will be at least '2'.
  • the division result is generated in the left auxiliary circuit 2 using the control signals D / I and AS.
  • the left subcircuit 2 has a structure similarity to the left main circuit 1.
  • the left secondary circuit 2 contains a dividend register 20, which stores the dividend, a multiplexer 31 for supplying the positive or negative dividend values to an adder circuit 41, a left quotient shift register 51, the output of which is connected to an input of the adder circuit 41 and thus forms a loop and a result register 61.
  • the process i of the left secondary circuit 2 runs in parallel with the parameters of the same type present in the left main circuit 1. Again in the second part of FIG. 2a, the left-justified division process for generating the quotient can be followed.
  • the dividend is loaded in the first cycle with the decimal value '889', ie '1101111001' in binary NRF format in the left quotient shift register 51. Furthermore, under the control of the signal AS, the content of the left quotient shift register 51 is shifted to the left by 2 places and, as signal D / I, is set to '0'; it leads in the 2nd cycle to the divi ends with inverse sign by means of multiplexer 31 of the ad dier circuit 41. The result is assumed in the left quotient shift register 51 to be an " equivalent left shift determined by the left main circuit 1. Similarly, there is a cyclical sequence up to the 8th cycle, with left-hand quotient bits being marked continuously, that is, in FIG After 8 cycles, the quotient has the following normalized binary value:
  • the quotient generated in the left quotient shift register 51 is available to the result block 61, which can carry out a possibly required rounding process. It goes without saying that one takes into account the sign rule of the division if one wants to generate the quotient with the correct sign, which is practically exclusively dependent on the value of the signal S ⁇ >. If Sc »j is '0', for example, the two's complement of the value loaded in result block 61 is the correct quotient value.
  • the generator of the inverted divisor value 70 is not necessary to generate the quotient. This would only be useful if the division was carried out by means of a multiplier in which the dividend acts as a multiplicand and the inverted divisor value by means of a multiplier register 80 as a multiplicand. In this way, the generator of the inverted divisor value 70 would use the two control signals AS and D / I.
  • the left-justified generation of the inverted divisor value can be followed in the lower part of FIG. 2a.
  • the first bit will be the same as the sign bit Sc »), that is to say '1' in the numerical example.
  • the subsequent bit slices are separated by dots and have the length of the left shift value. To the right of each bit slice, a digit dependent on the signal D / I is set in accordance with a Booth coding, as follows:
  • the other positions of the bit slice are filled with zeros.
  • the inverted divisor value is converted in accordance with a Booth decoding and displayed in the NRF format.
  • the right main circuit 3 and the right subcircuit 4 have the same functions as those of their homologous left main circuit 1 and left subcircuit 2.
  • FIG. 2b shows the same numerical example, but with a right-justified sequence of the division process. So the content of the least significant digit, denoted by tic-j, plays the same role as the content of the most significant digit, _t c -> in the formation of the control signal D / I.
  • the control signals generated by the right main circuit 3 are right-justified with an index "R" to distinguish them from their left correspondents z generated in the left main circuit 1.
  • the signal S ⁇ > will have a different meaning in the right main circuit 3, etc. depending on the logical values of the 2 least significant digits of the divisor according to the following table (it is assumed that the final zeros will be removed):
  • the result * V resulting from a '0' row
  • the result * V is also obtained after 8 cycles in the right shift register 52, a signal STOP being generated.
  • the quotient is obtained, the bits of which are marked by underlines in FIG. 2b and which, as can be seen, has the same value as that in the left subcircuit 2 ⁇ generated quotient.
  • the individual digits in accordance with the Booth coding, are set symmetrically, ie left-justified within the bit slice, compared to the division process on the left.
  • a second phase of the calculation is started, which starts from the start of the STOP signal, for example cycle 9 (FIG. 2).
  • This time only the results located in the shift registers 50, 51 and 52, 53 are processed.
  • the only difference compared to the first phase is the replacement of the divisor or divider at the input of the adder circuits by the associated results, while the control signals retain their meaning and effect.
  • the first relative offset of the two sums will be equal to the sum of the above shifts associated with the first phase. In the given example for the left-justified or right-justified division process, the following values are obtained:
  • this value will double in each cycle (64, 128, ).
  • an accuracy of the quotient of 64 bits is achieved in the 9th cycle.
  • the quotient value is partially shown in Fig.2a and in Fig.2b in the 9th cycle.
  • the quotient value and the inverted divi sor value occur in a two's complement representation in FIG. 2b, since their sign has a negative number.
  • the example shown in FIG. 2 is resumed in MSD format, i a bidirectional, parallel left-justified and right-justified division process, in FIG. 10.
  • Fig.3 shows the connection of the left main circuit and right main circuit 3 of a bus-oriented architecture, with an implementation of the division process in the MSD arithmetic.
  • the division circuit was designed for an operand length of 32 bits.
  • the divisor can be taken over by a Bu in NRF format or MSD format.
  • the C register 7 with the divisor value shown on 32 data bits and a sign bi can be loaded in parallel from the NRF bus 5.
  • the C double register 11 can be loaded in parallel by means of the multiplexer 9 with date from both the NRF bus 5 and the MSD bus 6. There is also the possibility of serial connection of the operands to the division circuit, starting with the most significant and / or least significant bit / trit.
  • the C register 7 and the C -Double register would be 11 FIFO registers.
  • the division process would be suitable for a one-sided (left-justified or right-justified) as well as for a left-right cooperating implementation.
  • the C double register 11 is left-justified and right-justified, each with a left zero detector 12 or right zero detector 13 for the detection of up to 31 leading or trailing zeros.
  • FIG. 3a shows the structure of a cell "i" of the converter 8 from FIG. 3, which realizes the truth table from FIG. 3a and consists of the gates 172-180.
  • the variable i can take values from 1 to n, where n is 32.
  • the sign bit b » ⁇ is also used in order to be able to handle signed operands.
  • the circuits for generating the extreme trits t_ and _t consisting of the gates 181-185 and 168-171 were shown separately, since they are suitable for minimization according to the truth tables from FIG. 3b.
  • the left C shift register 14 as a divisor register 10
  • the multiplexer 32 as a multiplexer 30
  • the left adder circuit 42 as an adder circuit 40
  • the left result shift register 54 as a left shift register 50
  • the left zero detector 62 as a zero detector 60
  • the left coding device of the inverted divisor value 72 as a generator of the inverted divisor value 70
  • the left multiplier encoder 82 as a multiplier register 80
  • the left comparison device 24 as a selection gate 22 and 23.
  • the left divisor multiple generator 18 which can produce the 3rd and 5th multiples of the divisor (denoted by Rs or R 5 ) and the left shift register 21, which secures the transfer connection to the right adapter circuit 17.
  • the function of the left approximation circuit 16 is equivalent to the left main circuit 1 and is carried out in MSD format.
  • the divisor is thus left-justified in the left-hand C shift register 14 and converted in accordance with the presentation strategy of the “non-adjacent non-zero trits”.
  • the most significant trit represents the sign of the divisor, since the leading zeros have been removed by means of the left shift, controlled by the signal LN.
  • the initiation of a di ision process is controlled by the signal INIT.
  • the 33 positive and negative output trits are supplied to the left divisor multiple generator 18.
  • Ri denotes the unchanged divisor
  • the sign digit S__ and two signals for the left shift correction SL are also generated.
  • the selection of the multiples which is to occur at the output is determined by the control signals Si and S 2 .
  • the selected multiple is fed on a 36-trunk line bundle, the Multiplexer 32, via two inputs with a direct or inverse sign.
  • the 3 additional digits come from 5th divisor multiples, which adds two digits and a transfer.
  • the other two inputs of the multiplexer 32 are those who adjust the right result
  • the selected output signal is passed to the left adding circuit 42 as a first summand.
  • the left-aligned output signal jLR of the left result shift register 54 is fed back at the other input of the left adder circuit 42 as a second summand.
  • the results generated in the MSD adder 157 are shown in the redundant MSD format of the two summands are stored in the lock memory 158 in order to make them available to the left and right result shift registers 54 and 55 from FIG. 4b in the corresponding form.
  • the output signal LR as the last sum result is first examined by the left zero detector 62 at the more significant points and, depending on the recognized zeros, shifted to the left by means of the signal ASL.
  • a control signal ISx is generated for the left coding device 72.
  • the leading part is then fed to the most significant trit following the left-justified signal
  • An additional one-digit or two-digit left shift for the alignment process can then take place, depending on the signals SL.
  • LR are then examined in order to check the completion of the first phase of the division process.
  • the left comparison device 24 compares the contents of the left result shift register 54,
  • the signal D / I_ will be dependent on the signals Sx, the divisor and ⁇ t c -j of the signal jLR and, as can be seen in FIG. 1, determine the corresponding preferred choice in the multiplexer 32.
  • the inverted divi sor value in the left coding device 72 could also generate the inverted divi sor value in the left coding device 72 by means of the early signals D / Ix ,, Sx, and OSx ,, the selection signals Sx, S_> and S 3 and the left shift signal ISr. Supplementation with the right partial result is guaranteed by the left-justified signal jIR.
  • the signal ILSO is regarded as a possible serial output of the inverted divisor value starting with the most significant trit. If the divider is a multiplicand within a multiplier, the reciprocal of the divisor, which is transmitted in parallel in the left multiplier encoder 82, could act as a multiplier.
  • FIG. 4b shows a further development of the right approach circuit 17 from FIG. 3, which is symmetrical of the homologous left approach circuit 16.
  • the following equivalent elements can be found here: the right C shift register 15, the right divisor multiple generator 19, the multiplexer 33, the right adder circuit 43, the right result shift register 55, the right zero detector 63, the right comparison device 25, the right one Coding device 73 and the right multiplier encoder 83.
  • a first difference is that the connection to the left approach circuit 16 is established on one side as a transfer.
  • a second difference is that the two shift correction signals SR are optional and dependent on the connection strategy with the left approximation circuit 16. These should not necessarily be available.
  • a final difference relates to the number of positive and negative trits produced by the right divisor multiple generator 19. Since the divisor multiple is right-justified, no second will occur because of the carry already present in the right C shift register 15, so that the number of tritches remains at 35.
  • the signals S R , t ⁇ t -), D / IR and OSE apply as sign signals.
  • selection signals S__ and S B as selection signals S__ and S B ; as control signals ASR, IS R FR. and LNDs. and as a serial output signal starting with the least significant trit, IRSO.
  • the operation of the right approach circuit 17 is the same, right-justified and symmetrical the left approach circuit 16. The only difference in the right comparison device 25 would be the absence of the signal LR ',.
  • FIGS. 4 a and 4 b show the developments of the left divisor multiple generator 18 and right divisor multiple generator 19 from FIGS. 4 a and 4 b, respectively. These generate the 3rd and 5th divisor multiples, the left and right sign of the divisor and the two left and right shift correction signals.
  • the divisor multiples generated are implemented at least at their 6-digit significant leading or closing parts in accordance with the presentation strategy of the "non-adjacent non-zero trits" in order to carry out the comparison process within the left or right comparison device 24 or 25 to facilitate.
  • the minimum number 6 of the significant leading or final trits to be implemented would be sufficient, since the decisive differences between the elements to be compared already exist within those parts.
  • the left adder circuits 26 and 28, the structure of which is shown in FIG. 5 c, are supplied with the input with the divisor value with a direct sign to 33 trit pairs, left-justified, at one input.
  • the divisor is fed with an inverse or direct sign to the 3rd multiple (R3) or 5th multiplication ⁇ che (Rs) to generate in the adders 26 and 28, respectively.
  • R3 3rd multiple
  • Rs 5th multiplication ⁇ che
  • the two shift correction signals, SLx negated by means of gate 46 and gate 48 by means ⁇ SL, are generated from the utilisewer ⁇ term Tritschreiben. These will check the absence or the presence of a non-zero step at the most significant position of the 3rd or 5th multiple to ensure the alignment process in the left adding circuit 42.
  • the effect of the two shift correction signals approved by the signal ESC can be followed in columns 7, 8 and 9 of the table from FIG. 11a.
  • the 10 is a numerical sches example for the generation of the 3rd (R3) and 5th (R_) multiples of a divisor ('641') and a dividend ('889') in MSD format, as well as the logical values of the two signals SL, for the divisor.
  • the 3rd and 5th multiples are further fed to the multiplexer 34, which determines the continuation selection by means of the selection signal S_.
  • the next multiplexer 36 either selects the divisor (the 1st multiple, Ri) or the signal that has occurred at the output of the multiplexer 34 by means of the output signal of the gate 44.
  • the START signal is set to '1' during the START cycle and is therefore selected left-justified with the aid of the gate 44 de divisor (Ri) which reaches the left result shift register 54. STAR drops to '0' from the 1st cycle. As a result, the selection is determined exclusively by the negated signal Sx by means of gate 44.
  • the elements with the same meaning are: the right adding circuits 2 and 29 with the left adding circuits 28 and 26, the multiplexers 35 and 37 with the multiplexers 34 and 36, the signal memory 39 with the signal memory 38, the gate 45 with the gate 44 and the signals S ⁇ , S 5 and tx ⁇ »> with the signals Sa, Sx and ⁇ t ( *> .
  • the possible effect of the two sliding correction signals, depending on the right-left connection strategy, can be seen in the last 2 columns follow the table from Fig.11a ver.
  • 5c shows the structure of the left and right adding circuits 26 and 28 or 27 and 29.
  • the first 6 right-justified sum trits zi are implemented by means of the strategic converter 49 only for the comparison process in the output trits t_.
  • the circuits for the MSD adder 47 and the strategic converter 49 are also shown in FIGS. 5d and 5f.
  • FIG. 5d shows the construction of an adder cell "i" of the MSD adder 47 from FIG. 5c, which realizes the truth table from FIG. 5e and consists of the gates 206 to 215.
  • the circuit is considerably simplified compared to the known MSD adders. The computing time is therefore shorter. However, it is only suitable for summands with non-adjacent non-zero trits.
  • FIG. 5f shows the structure of a cell "i" of the strategic converter 49 in FIG. 5c that realizes the truth table from FIG. 5g and the gates 186 to 205 in the presentation strategy of the "non-adjacent non-zero trits" consists.
  • the display format generated was actually only intended to facilitate the comparison process within the left and right comparison devices (24 and 25).
  • FIG. 6 a shows the development of the left comparison device 24 from FIG. 4 a.
  • the signal memory 76 uses the initiation signal INIT to generate the negated START signal, which occurs at its negated output and initiates the START cycle in the two approach circuits 16 and 17.
  • the delayed START signal STx is generated by means of the signal memory 78, which allows the recognition of a 6-digit sequence of leading digits of the positive or negative square root of '2' within the coincidence circuit 64.
  • the corresponding circuit is shown in FIG. 6b.
  • the coincidence circuits 64, 66, 68 and 74 compare left-justified, from the 3rd higher trit (3t), the content of the divisor C
  • LR direct or inverse form
  • RR [it] are implemented by means of the strategic converters 160 and 159, respectively, in accordance with the presentation strategy of the "non-adjacent non-zero trits".
  • LR is generated by inversion of the logical value of the most significant negative trit ⁇ tc_ > of the left result by means of NOT gate 216.
  • the elementary cell of the coincidence circuits is shown in FIG. 6d.
  • the output signals of the coincidence circuits iC, * CC, 3 C and 4 C, which represent the coincidence number of the corresponding comparison, are fed to a left selector 58.
  • the latter recognizes the largest coincidence number and accordingly generates the selection signals Sx, Sz and S 3 . If the largest coincidence number occurs twice, the selection is made according to the following priority: xC, 2 C, 3 C and 4C.
  • Gates 90 and 94 are necessary in order to negate the selection signals Sx and S_, form required by the left approach circuit 16.
  • the negated START signal at the input of gate 94 prevents the selection of signal jRR from multiplexer 32 from FIG. 4 a in the START cycle.
  • S 3 is thus initially set to '0'.
  • the gate 92 is available for the detection of a selection of the 3rd or 5th multiplicity in order to allow the shift correction, wherein Sx and S 3 have the logical value '0' and the signal ESC is set to '1'.
  • Gates 86 and 88 have the functions of gates 22 and 23 from FIG. 1.
  • gate 84 appears which, in the event of the recognition of a sequence of leading digits of the positive or negative square root of '2' within the divisor (Rx), during the first cycle, by the signal C
  • the signal D / Ix is also pulled to the control input of the multiplexer 56 in negated form leads.
  • the result obtained after the first significant trit in the presence of a gate, contains 84 several zeros (at least 3). In the absence of gate 84, however, only 2 zeros are obtained. Thus, several quotient bits are generated in the 2nd cycle of the left-justified division process. However, one must take into account the one-digit shift to the right of the most significant step, which is compensated for by a decrementation of the quotient exponent.
  • ⁇ / 2 in FIG. 6b can only be generated by the authorization signal STx, which is active ('1') only during the 1st cycle.
  • Gate 79 complements signal Sx, and the NIC ⁇ T AND gate 81 performs the OR operation between the negated outputs of the gates 75 and 77.
  • 6c shows a development of the right comparison device 25 from FIG. 4b, the structure of which is the same as that of the left comparison device 24.
  • the coincidence circuits 69, 67 and 65 compare right-aligned, as well as in the left comparator 24, the third low-Trit (t 3), the content of the divisor (RXJ), the third (Rs
  • the strategic translator 161 converts 6 final trits of the right result (RRJ ttd.]) According to the presentation strategy of the "non-adjacent non-zero trits".
  • the third multiple of the divisor, R 3 1 is brought in complementary form to the input of the coincidence circuit 67, so that its right-justified sign corresponds to the signal SR. is equal to.
  • the output signals of the coincidence circuits Ci, C_ ⁇ and C 3 which represent the coincidence number of the corresponding comparison, are fed to a right selector 59, which accordingly selects the selection signals S * and negated S s , according to a certain order of priority (Cx, C 2 and C 3 ).
  • Gates 85 and 87 have the same functions as their homologous gates 86 and 88 from left comparison device 24, respectively. equal to produce the signal D / I R at the selection input of the multiplexer 57 corresponding to a sign selection of the signal SRR 'the right-justified Divisorvor Carl SR TO.
  • FIG. 6d shows the structure of a coincidence cell which is used in the coincidence circuits from FIGS. 6a and 6c.
  • the modulo-2 adder gates 89 and 91 have as inputs the positive or negative trits of the same place value "i" of the elements to be compared, ⁇ LR and ⁇ R X or RR! and R x ⁇ . In the event that two of the four trits to be compared are equal, the output signals of gates 89 and 91 will be '0' and NOR gate 93 will set signal Eq ⁇ to '1'.
  • FIG. 7 a shows a further development of the left zero detector 62 from FIG. 4 a.
  • the left result shift register 54 contains the left result LR generated by the left adding circuit 42, as the last total result, the leading part of which begins with zeros (at least in a number of 2).
  • the left zero encoder 96 will output the number of recognized leading zeros, which can also occur in a redundant form (the signal LNDx. Accordingly, the content of the left result shift register 54 is shifted to the left by * a signal ASL generated by the alignment adder 98
  • the left-justified signal iLR is thus obtained for the left comparison device 24.
  • the trit pair ot will assume the logical value '0 r and the most significant trit pair xt will determine the sign ⁇ ter form has been eliminated, one of the trit pairs ot will be a significant '1' and the most significant trit pair xt will be set to complementary values supply the correct value of the most significant negative trit to the signal memory 166.
  • the output signal t c-a (ILR) of the signal memory 166 is used for the sign selection.
  • the circuit from the Schiebekorrektur- be generated from the Figure 7b secured. If the operand length is '32', 5 bit signals are required for the left shift number ASL.
  • the signal ASL is continued in the first phase of the division process, in which F_ is' 0 ', by means of gates 110 and 112 of the left coding device 72 under the name ISx, since a' 1 'occurs and also, at the output of the NAND gate 108 from the signal Fr, a' 1 'is saved.
  • the addirer 100 sums the occurring signals ASL with the last received signal SASL, which is fed to the other input of the adder 100 by means of the signal memory 102.
  • the adder 100 will give the sum of all the above signals ASL, also to 5 bit signals. It has been shown who a signal Ci ⁇ / 2 is present in the first cycle, must be compensated with the value (-1) of the sum SASL. For this purpose, this signal was supplied to the least significant position value of the adder 100 in order to achieve decrementation.
  • the 7b shows the shift correction circuit for the generation of the necessary left alignment signals xA and 2 A.
  • the input signals for the left shift correction are: ESC, negated SLx, S 2 and SL 2 .
  • the signals xA or 2 A set to '1' mean an additional left shift with or 2 digits, which counts as shift correction values '0' or (+1) (see columns 7, 8 and 9 of the table from Fig. 11a ). Both signals xA and 2 A set to '0' do not mean an additional left shift, which is considered a shift correction value (-1). Therefore, if there is no shift correction, the signal xA must be applied to '1'.
  • ESC must have the logical value '1', and the multiple of the divisor selected by the signal S_ must have a shift correction.
  • the NOT gate 95 uses gate 115 to approve the effect of the signal SL_ when the 5th divisor multiple is selected, since S 2 has the logical value '0'.
  • the right signals Ax and A 2 are also generated by means of the input signals negated S 5 , negated SRx, S 4 and SR_, the shift correction values of which are shown in the last two columns of the table from FIG.
  • FIG. 7c shows a development of the right-hand zero detector 63 from FIG. 4b.
  • the elements which are symmetrical with the left zero detector 62 and which have the same functions, namely the right result shift register 55 with the left result shift register 54, the right zero encoder 97 with the left zero encoder 96, the adder 101 with the adder 100, the signal memories 103 and 167 with the signal memories 102 and 166, the gates 105, 107, 109, 111, 113, 163 and 165 with the gates 104, 106, 108, 110, 112, 162 and 164, respectively.
  • FIG. 8a shows a development of the left coding device 72 from FIG. 4a.
  • the inverted divisor value is generated in a left inverse shift register 118, the content of which can be shifted to the left by the signal ISr.
  • the input data of the left inverse shift register 118 are taken over in parallel in each cycle via a multiplexer 120 during the first phase of the division process. This supply takes place either from a circuit which is shown in FIG. 8b (the trit pairs t 3 , t 2 and tx), or from a left shift register 71, which contains the right reciprocal of the divisor.
  • the multiplexer 120 is controlled by the negated selection signal S 3 . If S 3 is at '1', the 35
  • ) is stored, speaking ent the logical value of OSx signal, and after a certain shift to the left in the left inverse shift register 11 is at this returned in parallel again in order to ensure continuous chaining.
  • the right-justified zero detector 124 emits the number of detected final zeros by means of signal ITN in order to ensure alignment of the right inverted divisor value. It can be seen that the circuit is provided with two possible serial outputs, ILSOx and ILS0 2 , which can make the reciprocal of the divisor available in serial form to an interface.
  • the output ILSOx from the 3rd low-order step 3 has data during the first phase of the division process and the output ILS0 2 occurs at the most significant position of the left inverse shift register 118.
  • FIG. 8c shows a development of the right coding device 73 from FIG. 4b. It can be seen that the circuit is symmetrical to its left equivalent counterpart, with the exception of the lack of the connecting elements for linking with the left coding device 72.
  • the input data i right inverse shift register 119 are during the first phase of the division process, in each cycle, from a circuit, which is shown in Figure 8d, taken over in parallel (the trit pairs ⁇ t, 2 t and 3 t). If one enters the second phase of the division process, in which Fx is equal to '1', the content (!
  • IR stored in the right block 123, consisting of a multiplex with signal memory, becomes the content of the right inverse shift region shifted by the signal IS R sters 119 added in parallel, so a concatenation takes place.
  • IR is from the signal OS » b Right.
  • the circuit is provided with two possible serial outputs, IRSOx and IRS0 2 .
  • the output IRSOx from the 3rd higher-value step 3 t has data only during the first phase of the division process, and the output IRS0 2 occurs at the lowest value position of the right inverse shift register 119.
  • the circuit from FIG. 8b realizes the truth table, which is shown in columns 10 to 13 on FIG. 11a.
  • the left sign S_ of the divisor is denoted by "S".
  • the two modulo-2 adder gates 126 and 136 play the role of a NOT gate in that their second input signal is passed on in negated form.
  • the modulo-2 adder 128 ensures the corresponding dependence of the tread pair tx on the signal Sa.
  • the circuit from FIG. 8d realizes the truth table, which is shown in columns 6 to 9 of FIG. 11b.
  • the right sign S_ of the divisor is designated with "S".
  • the circuit only works during the first phase of the division process Fs ⁇ 'O').
  • the existing gates have the same functions as those of the gates from Fig. 8b.
  • the gates 133, 139, 129, 131, 135, 127 and 137 correspond to the gates 134, 138, 130, 132, 126, 136 and 128, respectively.
  • there is an additional NOT gate 125 which, because of the supply of the 3rd divisor multiple (R 3 ) on the right comparator 25 with inverse sign (-R 3 ) has been used, which can also be seen in the truth table.
  • FIG. 9a shows a circuit for recognizing a possibly exact division result and can be used in the dividend part CSlave) both in the left secondary circuit 2 (in the result block 61) and in the right secondary circuit 4. Their presence is optional and in some cases can help to reduce computing time.
  • the circuit is only effective from the end of the first phase of the division process.
  • the signal Fx, or F R uniformly designated F (L / R), was introduced as an approval signal at the input of the coincidence circuit 141.
  • This circuit compares the content of the left-justified half of the quotient (1QU) with the content of the right-justified half of the quotient (QUj), which is provided with a direct or inverse sign, depending on whether the logical value of the signal OS (L / R) '0 'or' 1 '. If the coincidence is correct, the STOPx signal will stop the division process and in the quotient register 143 the left-justified half of the quotient is the exact result with a direct or inverse sign, depending on whether the left-justified divisor sign Sx, the logical value '1' or '0 'has loaded for the left-justified or bidirectional detection process.
  • the left-justified half of the quotient is loaded into the quotient register 143 as an exact result with a direct or inverted sign, depending on whether the least significant negative trit (tic-j) . of the right result shift register 55 has the logical value '0' or '1'. If the coincidence is not correct, the division process is continued until the required accuracy ("e") is reached.
  • the constant "e” is supplied from the NRF bus 5 or MSD bus 6 via a constant register 140 to a comparison device 142 which determines the numerical ratio between the constant "e” and the signal SAS (L / R). If “e” is less than SAS (L / R), the STOP 2 signal is generated and the division process is ended.
  • the continuation signal 156 is generated and the division process is continued until the signal SAS (L / R) reaches a corresponding size.
  • the result in the quotient register 143 can be transferred to both the MSD bus 6 and the NRF bus 5 by means of a conventional NRF converter 144.
  • FIG. 9b shows a circuit for carrying out the rounding process at an arbitrary place value "e".
  • the lower-order trit pairs are analyzed within the left quotient shift register 51, starting with the place value "e" (»° t, _ 1 t, _ 2 t, ).
  • the place value "e” (»° t, _ 1 t, _ 2 t, .
  • the higher-order trit pairs 146 are passed unchanged to the result register 149 from the position value "e". Its content!
  • the selection signal 154 of the e-multiplexer 147 selects either the original trit pair ⁇ ° t or the adjacent trit pair «as rounding strits.
  • the selection signal is generated with the aid of a block 145, consisting of a zero detector with a comparison device, which evaluates the lower-order trit pairs 148.
  • the zero detector from 145 recognizes the left-justified zeros of the positive trits separately from the left-justified zeros of the negative trits.
  • the comparison device from 145 sets the positive or negative distance signal, 150 or 152, to '1', depending on whether the number of recognized zeros has the smaller value in the case of the positive or negative trits.
  • the AND gates 153 and 151 confirm the presence of a significant positive and negative trit ⁇ '-t and a significant subsequent lower order trit of the same polarity, '+' and '-', respectively.
  • the OR gate 155 generates the selection signal 154 when the mentioned condition for the positive or negative trits is fulfilled.
  • the divisor is normalized by generating its mantissa (M), the absolute value of which should belong to the area centered on '1':
  • E (d) E (d) o + ⁇
  • the shift ⁇ can be regarded as a normalization shift, with the following value:
  • N number of digits used to the left of the dual point
  • LN number of leading zeros of the divisor (see Fig. 3)
  • FIG. 10 the same example from FIG. 2 is adopted, with the operands shown in MSD format and with a bidirectional left-right according to the invention cooperative implementation of the division process with regard to the left and right approximation circuits 16 and 17 from FIGS. 4a and 4b, the 3rd and 5th multiples of the operands also being present.
  • the non-zero positive and negative trit is designated with '+' or '-' and the zero trit with '0'.
  • the left and right multiple generators After the operands have been converted into MSD format, the left and right multiple generators generate the 3rd and 5th multiples of the operands and the left shift correction signals, negated SLx and SLa.
  • the left and right zero detectors 62 and 63 become 2 Recognize leading zeros or 7 trailing zeros and the content is shifted accordingly in the registers.Furthermore, the left and right comparison devices 24 and 25 are the multiples ([R 3 or R 5 ! and their signs (inverse or select inverse), which are fed to the left and right adder circuits 42 and 43 for the first addition cycle since the negated signal SLx is '0', the left shift correction will also assume the value '0' 2nd cycle we the leading and trailing zeros are recognized within the results obtained (4 and 7) and their contents are accordingly shifted.
  • ) are also selected.
  • the left comparison device 24 will select the left-justified right result with a direct sign (+ JRR). If you do the same in the 3rd cycle, you get the result '1' within the 4th cycle.
  • the signal Fx is thus set to '1' by the left zero detector 62, which signals the end of the first phase of the division process by obtaining the periodic break of the divisor.
  • the accuracy obtained at this time takes on a value that is the sum of the previous ones Existing links Verse same is:
  • the process takes place under the control (shift and selection) of the master part. After 3 addition cycles, a result is obtained which represents the quotient with an accuracy of 32 trits / bits.
  • the quotient value is obtained with an accuracy of 64 digits, both in the MSD format and in the NRF format.
  • the dual point can be seen to the right of the 2nd most significant value, since the following normalization shift ( ⁇ ) of the divisor, which changes the quotient exponent, has taken place:
  • ⁇ / 2 - 32 + 23 + 0
  • FIG. 11a the first 6 columns (for 0 ') on the left comparison device 24 or (for 1 ') on the left coding device 72, columns 7, 8 and 9 on the left divisor multiple generator 18 or on the shift correction circuit from FIG. 7b, columns 10 to 13 on the left coding device 72 and the last 2 columns on the right divisor multiple generator 19 or on the shift correction circuit from Fig. 7b.
  • FIG. 11a the first 6 columns (for 0 ') on the left comparison device 24 or (for 1 ') on the left coding device 72, columns 7, 8 and 9 on the left divisor multiple generator 18 or on the shift correction circuit from FIG. 7b, columns 10 to 13 on the left coding device 72 and the last 2 columns on the right divisor multiple generator 19 or on the shift correction circuit from Fig. 7b.
  • the division process can only be carried out right-justified. In this case, however, the second phase of the division process must be reached, in which FR should become '1'. 12 therefore shows the period lengths which are the same as the corresponding end values of the SASR signal for odd-numbered divisors smaller than 100 (in the decimal number system) and the deviation sign compared to the exact results.

Abstract

On décrit un nouveau procédé ainsi qu'un circuit diviseur à architecture symétrique à base purement matérielle qui produit par approximation, en mode récursif et bidirectionnel, un quotient à partir d'un dividende et d'un diviseur. Le calcul peut ainsi commencer avec la valeur de position la plus élevée ou la plus basse ou simultanément, dans un traitement parallèle, avec les deux extrêmes du diviseur, du dividende et du quotient. Dans ce but, le circuit diviseur est constitué de quatre parties symétriques deux à deux. Le circuit principal gauche (1), qui est symétrique au circuit auxiliaire droit (3), traite le diviseur et commande, au moyen des deux signaux de commande D/I et AS, le circuit auxiliaire gauche (2), qui est symétrique au circuit auxiliaire droit (4) et qui traite le dividende pour produire le quotient. Les deux parties symétriques peuvent fonctionner indépendamment l'une de l'autre, et donc séparément, ce qui permet d'exécuter simultanément deux opérations de division différentes au moyen des deux moitiés symétriques. L'opération de division peut donc être exécutée de manière bidirectionnelle ou unilatérale (vers la gauche ou vers la droite). Les opérateurs peuvent être représentés sous une forme non redondante ou sous la forme d'un chiffre accompagné d'un signal, et la stratégie de représentation du 'trit non voisin non nul' empêche le report de la retenue ('carry-ripple'), tandis que la valeur absolue de mantisse (M) appartient, après l'opération de normalisation, à un domanie centré sur 1.
PCT/AT1993/000074 1992-04-30 1993-04-29 Procede de production du nombre inverse d'un diviseur par approximation progressive WO1993022720A2 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3777132A (en) * 1972-02-23 1973-12-04 Burroughs Corp Method and apparatus for obtaining the reciprocal of a number and the quotient of two numbers
US4011439A (en) * 1974-07-19 1977-03-08 Burroughs Corporation Modular apparatus for accelerated generation of a quotient of two binary numbers
EP0353041A2 (fr) * 1988-07-26 1990-01-31 THORN EMI plc Appareil et procédé de traitement de signaux en utilisant l'arithmétique à chiffres signés modifiée

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3777132A (en) * 1972-02-23 1973-12-04 Burroughs Corp Method and apparatus for obtaining the reciprocal of a number and the quotient of two numbers
US4011439A (en) * 1974-07-19 1977-03-08 Burroughs Corporation Modular apparatus for accelerated generation of a quotient of two binary numbers
EP0353041A2 (fr) * 1988-07-26 1990-01-31 THORN EMI plc Appareil et procédé de traitement de signaux en utilisant l'arithmétique à chiffres signés modifiée

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS Oktober 1963 , NEW YORK US Seiten 503 - 511 W. DALY ET AL. 'A High-Speed Arithmetic Unit Using Tunnel Diodes' *
K. HWANG 'Computer arithmetic' 1979 , J. WILEY & SONS , NEW YORK, USA. Abschnitte 5.7 - 5.10 und 7.7 - 7.9 (Seiten 149 - 159, 226 - 238) siehe Seite 150, Zeile 1 - Seite 151, Zeile 6; Tabelle 5.5 siehe Seite 227, Zeile 1 - Seite 228, Zeile 15; Abbildung 7.15 *
PROCEEDINGS OF 9TH SYMPOSIUM ON COMPUTER ARITHMETIC, SANTA MONICA, CA, USA, 6-8 SEPT. 1989. 1989 , WASHINGTON, DC, USA, IEEE COMPUTER SOCIETY PRESS, USA Seiten 169 - 173 XP000135365 M. ERCEGOVAC ET AL. 'On-the-fly Rounding for Division and Square Root' *
PROCEEDINGS OF THE SECOND INTERNATIONAL CONFERENCE ON COMPUTERS AND APPLICATIONS, 23-27 JUNE 1987, BEIJING, CHINA. 1987 , IEEE, NEW YORK, USA. Seiten 833 - 838 D. YUN ET AL. 'time-space optimal systolic array divider using redundant binary representation' *

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