WO1993017455A3 - Configuration de boitier de circuit integre pour l'encapsulation d'une puce a circuit integre et procede d'encapsulation d'une puce a circuit integre - Google Patents

Configuration de boitier de circuit integre pour l'encapsulation d'une puce a circuit integre et procede d'encapsulation d'une puce a circuit integre Download PDF

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Publication number
WO1993017455A3
WO1993017455A3 PCT/US1993/001490 US9301490W WO9317455A3 WO 1993017455 A3 WO1993017455 A3 WO 1993017455A3 US 9301490 W US9301490 W US 9301490W WO 9317455 A3 WO9317455 A3 WO 9317455A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated
bonding
circuit die
packaging
conductive traces
Prior art date
Application number
PCT/US1993/001490
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English (en)
Other versions
WO1993017455A2 (fr
Inventor
Young Il Kwon
Louis H Liang
Original Assignee
Vlsi Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vlsi Technology Inc filed Critical Vlsi Technology Inc
Priority to JP5514969A priority Critical patent/JP2691799B2/ja
Publication of WO1993017455A2 publication Critical patent/WO1993017455A2/fr
Publication of WO1993017455A3 publication Critical patent/WO1993017455A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/4805—Shape
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/20654—Length ranges larger or equal to 3000 microns less than 4000 microns

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

Un type de boîtier destiné à une puce à circuit intégré (104) comporte une grille de connexion dont les pattes de connexion (106) sont connectées à la périphérie d'un substrat (102) conducteur de chaleur, électriquement isolé, constitué par exemple d'un matériau céramique. Plusieurs trajets conducteurs électriques (110), ou îlots de liaison, servent de sites de liaison intermédiaire pour les fils de liaison plus courts (112, 116) connectant les plages de connexion (114) placées sur la puce à circuit intégré (104) aux pattes de connexion (106) de la grille de connexion. La puce à circuit intégré recouvre les trajets conducteurs tout en laissant une partie exposée qui sert respectivement de zone de rattachement intermédiaire pour chacun des fils de liaison. Les trajets électriques servant d'îlots de liaison sont créés par dépôt d'un matériau en couche mince recourant aux techniques de fabrication des semi-conducteurs ou par dépôt d'un matériau en couche épaisse recourant aux techniques d'impression.
PCT/US1993/001490 1992-02-20 1993-02-19 Configuration de boitier de circuit integre pour l'encapsulation d'une puce a circuit integre et procede d'encapsulation d'une puce a circuit integre WO1993017455A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5514969A JP2691799B2 (ja) 1992-02-20 1993-02-19 リードフレームに接合された介在ダイ取付基板を有する集積回路パッケージ設計

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US83919192A 1992-02-20 1992-02-20
US07/839,191 1992-02-20

Publications (2)

Publication Number Publication Date
WO1993017455A2 WO1993017455A2 (fr) 1993-09-02
WO1993017455A3 true WO1993017455A3 (fr) 1993-11-25

Family

ID=25279091

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1993/001490 WO1993017455A2 (fr) 1992-02-20 1993-02-19 Configuration de boitier de circuit integre pour l'encapsulation d'une puce a circuit integre et procede d'encapsulation d'une puce a circuit integre

Country Status (2)

Country Link
JP (1) JP2691799B2 (fr)
WO (1) WO1993017455A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598031A (en) * 1993-06-23 1997-01-28 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
JP2002515175A (ja) * 1993-06-23 2002-05-21 ブイ・エル・エス・アイ・テクノロジー・インコーポレイテッド 別個のシリコンサブストレートを用いる電気的および熱的に向上したパッケージ
US5757070A (en) * 1995-10-24 1998-05-26 Altera Corporation Integrated circuit package
WO2001027996A1 (fr) * 1999-10-14 2001-04-19 Motorola Inc. Grille matricielle a billes a brochage reconfigurable
TWI325617B (en) 2006-12-18 2010-06-01 Chipmos Technologies Inc Chip package and method of manufacturing the same
US11476182B2 (en) * 2017-10-10 2022-10-18 Shenzhen Chipuller Chip Technology Co., Ltd Assembly of flexible and integrated module packages with leadframes

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0036907A1 (fr) * 1979-12-28 1981-10-07 Fujitsu Limited Empaquetage du type à broches multiples pour élément de circuit
US4754317A (en) * 1986-04-28 1988-06-28 Monolithic Memories, Inc. Integrated circuit die-to-lead frame interconnection assembly and method
US4774635A (en) * 1986-05-27 1988-09-27 American Telephone And Telegraph Company At&T Bell Laboratories Semiconductor package with high density I/O lead connection
EP0351581A1 (fr) * 1988-07-22 1990-01-24 Oerlikon-Contraves AG Circuit intégré à haute densité et procédé pour sa fabrication
EP0443044A1 (fr) * 1989-09-12 1991-08-28 Kabushiki Kaisha Toshiba Cadre de montage pour dispositif a semi-conducteurs et dispositif a semi-conducteurs utilisant ce cadre de montage

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0036907A1 (fr) * 1979-12-28 1981-10-07 Fujitsu Limited Empaquetage du type à broches multiples pour élément de circuit
US4754317A (en) * 1986-04-28 1988-06-28 Monolithic Memories, Inc. Integrated circuit die-to-lead frame interconnection assembly and method
US4774635A (en) * 1986-05-27 1988-09-27 American Telephone And Telegraph Company At&T Bell Laboratories Semiconductor package with high density I/O lead connection
EP0351581A1 (fr) * 1988-07-22 1990-01-24 Oerlikon-Contraves AG Circuit intégré à haute densité et procédé pour sa fabrication
EP0443044A1 (fr) * 1989-09-12 1991-08-28 Kabushiki Kaisha Toshiba Cadre de montage pour dispositif a semi-conducteurs et dispositif a semi-conducteurs utilisant ce cadre de montage

Also Published As

Publication number Publication date
WO1993017455A2 (fr) 1993-09-02
JPH06507276A (ja) 1994-08-11
JP2691799B2 (ja) 1997-12-17

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