WO1993008597A1 - A semiconductor device, a semiconductor wafer for manufacturing a semiconductor device and a method for manufacturing such a semiconductor wafer - Google Patents

A semiconductor device, a semiconductor wafer for manufacturing a semiconductor device and a method for manufacturing such a semiconductor wafer Download PDF

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Publication number
WO1993008597A1
WO1993008597A1 PCT/SE1992/000707 SE9200707W WO9308597A1 WO 1993008597 A1 WO1993008597 A1 WO 1993008597A1 SE 9200707 W SE9200707 W SE 9200707W WO 9308597 A1 WO9308597 A1 WO 9308597A1
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WIPO (PCT)
Prior art keywords
layer
wafer
semiconductor
glass
layers
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Application number
PCT/SE1992/000707
Other languages
French (fr)
Inventor
Kjell Bohlin
Jonas Tiren
Original Assignee
Asea Brown Boveri Ab
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Application filed by Asea Brown Boveri Ab filed Critical Asea Brown Boveri Ab
Publication of WO1993008597A1 publication Critical patent/WO1993008597A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Definitions

  • the present invention relates to a semiconductor device comprising a carrier material in the form of a silicon wafer, at least one active layer of a semiconductor material, in which semiconductor circuits are produced, as well as electrically insulating layers between the carrier material and the active layers.
  • the invention also relates to a semiconductor wafer for the manufacture of semiconductor devices and comprising a carrier material in the form of a silicon wafer, an active layer of a semiconductor material for the production of semiconductor circuits, as well as electrically insulating layers between the carrier material and the active layer.
  • the invention relates to a method for the manufac ⁇ ture of a semiconductor wafer which is intended for the manufacture of semiconductor devices and which comprises a carrier material in the form of a silicon wafer, an active layer of a semiconductor material for the production of semiconductor circuits, as well as an electrically insula ⁇ ting layer between the carrier material and the active layer.
  • Certain semiconductor devices contain a plurality of semi ⁇ conductor circuits, applied to one and the same carrier (substrate) , in the form of separate layers of semiconductor material, usually silicon.
  • Each one of the semiconductor circuits may consist of one single device, for example a transistor, or of a more or less complicated integrated
  • circuit with a plurality of devices For the circuits applied to the carrier to be able to work at different electrical potentials r it is desirable that they are electrically insulated from the carrier and hence from each other.
  • SOI Silicon On Insulator
  • SOS Silicon On Sapphire
  • the carrier consists of a silicon wafer.
  • a silicon dioxide layer is formed at a certain depth below the substrate surface.
  • the semiconductor circuits are then produced.
  • this technique only a very thin oxide layer can be obtained, and this layer will therefore have a low dielectric strength.
  • the thin oxide layer entails a conside ⁇ rable risk that the semiconductor circuits of the device may influence each other in an undesirable way - parasitic effects.
  • a third previously known method of producing a semiconductor device of the kind referred to is by bonding two silicon wafers to each other. On the surface of one of the wafers, or of both wafers, silicon dioxide layers are formed, whereupon the wafers are bonded to each other with the oxide layer of each wafer facing the other wafer.
  • the bonding is performed by heating to a relatively high temperature, for example to about 1100°C. After the bonding, one of the silicon wafers is ground or etched down to the desired thickness, whereafter the desired semiconductor circuits are produced in the layer which constitutes the remaining part of this wafer.
  • a relatively high temperature for example to about 1100°C.
  • the present invention aims to provide a semiconductor device with a considerably thicker insulating layer than what has previously been possible and which can be manufactured at lower process temperatures and hence with reduced risk of defects in the active semiconductor layer.
  • the invention also relates to a semiconductor wafer for the manufacture of such semiconductor devices and to a method for manufacturing such a semiconductor wafer.
  • Figure 1 shows an example of successive process steps in the manufacture of a semiconductor wafer according to the invention.
  • Figure 2 schematically shows a semiconductor device according to the invention.
  • Figure 3 shows an example of a finished semicon ⁇ ductor device according to the invention.
  • Figure 1 shows an example of successive steps in the manufacture of a semiconductor wafer according to the invention.
  • the starting material are two silicon wafers 1 and 2. They have a diameter of, for example, 50-100 mm and a thickness of, for example, about 0.5 mm.
  • Wafer 2 is intended to serve as carrier (substrate) for the finished semicon ⁇ ductor devices, and the material in wafer 1 is intended to serve as the active layer of the finished devices.
  • each wafer is first provided, as shown in Figure la, with thermal oxide by heating in the presence of oxygen.
  • the oxide layers 11 and 21, respectively, thus formed substantially consist of silicon dioxide and have a thickness of about 50 n (typically, the thickness of this layer may be within the interval 10-100 nm) .
  • the wafer 1 is provided with a layer 12 of silicon nitride .
  • This layer is produced by LPCVD (Low Pressure Chemical Vapour Deposition) from dichlorosilane (SiH 2 Cl 2 ) and has a thickness of 0.15 ⁇ m.
  • the silicon nitride has a good diffusion barrier effect and prevents dopants from the subsequently applied doped glass layers from diffusing into the silicon wafer 1 and distur ⁇ bing the function of the circuits formed therein.
  • the two wafers are heated to the yielding tempe ⁇ rature of the glass, which typically is 800-900°C, whereby the glass layers will float out and very even surfaces of the glass layers be attained.
  • the wafers After cooling, the wafers are put together with the glass layers facing each other in the manner shown in Figure Id, and a certain adhesion is obtained between the wafers. Then, the wafers thus joined together are heated to such a high temperature, typically 800-900°C, that a complete bonding is obtained between the wafers, which means that they will stick together like one single body.
  • a high temperature typically 800-900°C
  • the material in wafer 1 is removed down to the dashed line A-A in Figure Id. This can be done by grinding and polishing or by etching.
  • the remaining part of wafer 1, namely, the layer designated 14 in Figure Id constitutes the active layer, in which the semiconductor circuits of the finished semiconductor devices are to be formed.
  • the thick ⁇ ness of the layer 14 must be adapted to a suitable value for the circuits for which the wafer is intended, and in typical cases the thickness is within the interval 0.1-30 ⁇ m.
  • the wafer shown in Figure Id thus constitutes the starting material for the manufacture of semiconductor devices.
  • the thickness of the wafer is greatly exaggerated in Figure 1.
  • its diameter is typically 50-100 mm and its thickness about 0.5 mm.
  • semiconductor devices are manufactured from the above- described wafer by selectively etching away the active layer 14 such that a number of separate silicon islands are formed.
  • Figure 2 which shows the carrier 2 , an insulating layer 3 consisting of the layers 11, 12, 13 r 23, 21 shown in Figure 1, and a number of separate silicon islands 40, 41, ..., 48.
  • the latter may, for example, have the dimensions 10x10 ⁇ m.
  • semiconductor circuits for example in the form of MOS transistor circuits, are formed in the islands in a known manner by selective doping and contacting.
  • the wafer is divided in a check pattern (along the dashed lines B-B and C-C shown as example in Figure 2) into the semiconductor devices I, II, III etc.
  • Each device consists of a carrier with a number of silicon islands with circuits formed therein. After division of the wafer, there are formed, for example, the devices I, II and III, where , for example, device II consists of the part of the wafer 2 located between lines B-B and C-C and the corre ⁇ sponding part of the insulating layer 3, and the silicon islands 41-45.
  • Figure 3 schematically shows a picture of the device II with the silicon islands 41-50 prior to enclosing the device.
  • the semiconductor device according to the invention descri ⁇ bed above has a high dielectric insulation between the sub- strate and each semiconductor circuit, and hence also between the individual semiconductor circuits. This is achieved since the doped glass, which according to the invention is used as insulation between the carrier and the silicon islands, can be applied in thick layers.
  • the glass layers 13 and 23 have a thickness of about 1 ⁇ m.
  • the glass layers may without difficulty be given thicknesses of 2 ⁇ m or more. Together with the oxide layers 11 and 21, a total thickness of the insulation layers of 5 ⁇ m or more may thus be obtained. In typical cases, an insulation strength of several kv may be attained.
  • the manu ⁇ facturing process according to the invention makes it possible to attain this high insulation in an advantageous manner from the point of view of manufacturing and therefore provides considerable advantages compared with prior art methods.
  • the bonding of the wafers can be performed at a low temperature ( ⁇ 900°C) . In this way, the risk of defects being generated in the active semiconductor layers is greatly reduced, and better electrical properties may be obtained in the finished devices.
  • the oxide layers 11 and 21 provide a good and controlled adhesion of the other layers to the silicon wafers.
  • the carrier wafer 2 only has the function of serving as a carrier for the active semiconductor circuits.
  • the method and the semiconductor wafer according to the inven ⁇ tion can be used also in other applications, for example for the manufacture of semiconductor devices in which the carrier wafer consists of a silicon wafer in which a power component, for example a thyristor, is formed.
  • the semicon ⁇ ductor circuits arranged on the carrier wafer may then, for example, consist of control electronics for the power com ⁇ ponent.
  • both of the joined semiconductor wafers consist of silicon wafers.
  • this wafer may consist of germanium or a germanium-silicon mixture, or or another semiconductor material, such as gallium arsenide (Ga As) or indium phosphide (InP) .
  • the oxide layers 11 and 21 consist of thermal oxide.
  • these layers may be generated in some other known way, for example by a CVD process.
  • a thickness of the oxide layers of about 50 nm have been mentioned above.
  • these layers may be made considerably thicker, without any problem up to about 1 ⁇ m.
  • the oxide layers consist of an oxide of the semiconductor material (silicon) .
  • these layers may consist of another material, for example zirconium oxide or aluminium oxide.
  • the diffusion barrier layer 12 of silicon nitride described above layers of other materials with a correspon ⁇ ding function may be used, for example titanium nitride or zirconium nitride.
  • the oxide layer 21 may consist of an oxide generated in some other way, for example of undoped CVD- oxide. A layer of the latter kind has good diffusion- preventing properties, and the special barrier layer 12 can then be eliminated.
  • barrier layer 12 and the glass layers 13 and 23 are deposited with the aid of an LPCVD process.
  • a plasma-CVD process or so- called atmospheric CVD may be used.
  • the glass layers 13 and 23 consist of boron-phosphorus-doped glass containing about 4 per cent by weight boron and 4 per cent by weight phos- phorus.
  • boron-phosphorus-doped glass containing about 4 per cent by weight boron and 4 per cent by weight phos- phorus.
  • boron or only phosphorus may be used as dopant, and, of course, other dopants than boron and phosphorus (both single dopants and combinations of dopants) may be used, as well as other doping concentrations than those described above.
  • both wafers are provided with glass layers before the bon ⁇ ding of the wafers to each other.
  • only one of the wafers is provided with a glass layer.
  • this glass layer is then bonded to the other wafer. It has been found that a good bonding is obtained between the glass layer and that material in the other wafer which is nearest the glass layer, for example silicon, nitride or silicon oxide, and, in principle, the same advantages can be obtained with this embodiment as with the previously descri- bed one with two glass layers.
  • the device described above is only an example and can be formed in a large number of other ways.
  • the number of semi ⁇ conductor circuits which are applied to the carrier may be both lower and higher than that described above. In certain cases, several thousand semiconductor circuits may be applied to the carrier. Also other semiconductor circuits than purely electrical ones can be produced in the active layers, for example optoelectronic devices or circuits.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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Abstract

A semiconductor wafer for manufacturing semiconductor devices has a carrier wafer (2) of silicon, an active layer (14) for producing a number of semiconductor circuits which are electrically insulated from each other and from the carrier. An insulation layer is arranged between the carrier wafer and the active layer and comprises two layers (12, 23) of boron-phosphorous-doped glass which are bonded to each other.

Description

A semiconductor device, a semiconductor wafer for manufac¬ turing a semiconductor device and a method for manufacturing such a semiconductor wafer
TECHNICAL FIELD
The present invention relates to a semiconductor device comprising a carrier material in the form of a silicon wafer, at least one active layer of a semiconductor material, in which semiconductor circuits are produced, as well as electrically insulating layers between the carrier material and the active layers.
The invention also relates to a semiconductor wafer for the manufacture of semiconductor devices and comprising a carrier material in the form of a silicon wafer, an active layer of a semiconductor material for the production of semiconductor circuits, as well as electrically insulating layers between the carrier material and the active layer.
Further, the invention relates to a method for the manufac¬ ture of a semiconductor wafer which is intended for the manufacture of semiconductor devices and which comprises a carrier material in the form of a silicon wafer, an active layer of a semiconductor material for the production of semiconductor circuits, as well as an electrically insula¬ ting layer between the carrier material and the active layer.
BACKGROUND ART
Certain semiconductor devices contain a plurality of semi¬ conductor circuits, applied to one and the same carrier (substrate) , in the form of separate layers of semiconductor material, usually silicon. Each one of the semiconductor circuits may consist of one single device, for example a transistor, or of a more or less complicated integrated
Figure imgf000004_0001
2 circuit with a plurality of devices. For the circuits applied to the carrier to be able to work at different electrical potentials r it is desirable that they are electrically insulated from the carrier and hence from each other.
A previously known method of achieving this is with the aid of the so-called SOI technique (SOI = Silicon On Insulator) , according to which the carrier consists of an electrically insulating material, on which a plurality of semiconductor layers, separated from each other, are applied adjacent to each other. A common variant of the SOI technique is the so- called SOS technique (SOS = Silicon On Sapphire) , according to which the carrier consists of a wafer or a layer of sapphire. On the sapphire silicon layers are grown, and in the silicon layers the semiconductor circuits are then produced. It has proved that the quality of the silicon layers becomes poor owing to defects in the transition between the sapphire substrate and the silicon layers. This results in a low minority carrier life and hence poor elec¬ trical properties.
Another previously known method of producing a semiconductor device of the kind referred to here is the so-called SIMOX technique. In this case, the carrier consists of a silicon wafer. By implantation of oxygen a silicon dioxide layer is formed at a certain depth below the substrate surface. In the silicon layer between the oxide layer and the substrate surface, the semiconductor circuits are then produced. With this technique only a very thin oxide layer can be obtained, and this layer will therefore have a low dielectric strength. Further, the thin oxide layer entails a conside¬ rable risk that the semiconductor circuits of the device may influence each other in an undesirable way - parasitic effects.
A third previously known method of producing a semiconductor device of the kind referred to is by bonding two silicon wafers to each other. On the surface of one of the wafers, or of both wafers, silicon dioxide layers are formed, whereupon the wafers are bonded to each other with the oxide layer of each wafer facing the other wafer. The bonding is performed by heating to a relatively high temperature, for example to about 1100°C. After the bonding, one of the silicon wafers is ground or etched down to the desired thickness, whereafter the desired semiconductor circuits are produced in the layer which constitutes the remaining part of this wafer. For reasons of manufacturing technique, it is not possible with this technique to attain a larger thickness of the oxide layer than about 1-2 μm. The dielectric strength and the resistance against parasitic effects are therefore limited. Further, the high bonding temperature entails a considerable risk of defects being generated in the silicon and hence a risk of a low carrier life and poor electrical properties.
SUMMARY OF THE INVENTION
The present invention aims to provide a semiconductor device with a considerably thicker insulating layer than what has previously been possible and which can be manufactured at lower process temperatures and hence with reduced risk of defects in the active semiconductor layer. The invention also relates to a semiconductor wafer for the manufacture of such semiconductor devices and to a method for manufacturing such a semiconductor wafer.
What characterizes a semiconductor device, a semiconductor wafer and a method according to the invention will become clear from the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following the invention will be described with reference to the accompanying Figures 1-3. Figure 1 shows an example of successive process steps in the manufacture of a semiconductor wafer according to the invention. Figure 2 schematically shows a semiconductor device according to the invention. Figure 3 shows an example of a finished semicon¬ ductor device according to the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 1 shows an example of successive steps in the manufacture of a semiconductor wafer according to the invention. The starting material are two silicon wafers 1 and 2. They have a diameter of, for example, 50-100 mm and a thickness of, for example, about 0.5 mm. Wafer 2 is intended to serve as carrier (substrate) for the finished semicon¬ ductor devices, and the material in wafer 1 is intended to serve as the active layer of the finished devices.
One surface of each wafer is first provided, as shown in Figure la, with thermal oxide by heating in the presence of oxygen. The oxide layers 11 and 21, respectively, thus formed substantially consist of silicon dioxide and have a thickness of about 50 n (typically, the thickness of this layer may be within the interval 10-100 nm) .
After that (see Figure lb) , the wafer 1 is provided with a layer 12 of silicon nitride
Figure imgf000006_0001
. This layer is produced by LPCVD (Low Pressure Chemical Vapour Deposition) from dichlorosilane (SiH2Cl2) and has a thickness of 0.15 μm. The silicon nitride has a good diffusion barrier effect and prevents dopants from the subsequently applied doped glass layers from diffusing into the silicon wafer 1 and distur¬ bing the function of the circuits formed therein.
As the next step (Figure lc) there are applied on both wafers layers 13 and 23, respectively, of boron-phosphorus- doped quartz glass by LPCVD from silane (SiH^) with phosphine (PH^) and borontrichloride (BCI3) as doping gases. The doping is performed in such a way that the glass layers will contain about 4 per cent by weight boron and about 4 per cent by weight phosphorus, the remainder of the layers consisting of silicon dioxide (Siθ2) • The glass layers 13 and 23 have a thickness of 1 μm. The thickness of the glass layers preferably lie within the interval 1-2 μm but the layers may alternatively be made both thicker and thinner.
Thereafter, the two wafers are heated to the yielding tempe¬ rature of the glass, which typically is 800-900°C, whereby the glass layers will float out and very even surfaces of the glass layers be attained.
After cooling, the wafers are put together with the glass layers facing each other in the manner shown in Figure Id, and a certain adhesion is obtained between the wafers. Then, the wafers thus joined together are heated to such a high temperature, typically 800-900°C, that a complete bonding is obtained between the wafers, which means that they will stick together like one single body.
After that, the material in wafer 1 is removed down to the dashed line A-A in Figure Id. This can be done by grinding and polishing or by etching. The remaining part of wafer 1, namely, the layer designated 14 in Figure Id, constitutes the active layer, in which the semiconductor circuits of the finished semiconductor devices are to be formed. The thick¬ ness of the layer 14 must be adapted to a suitable value for the circuits for which the wafer is intended, and in typical cases the thickness is within the interval 0.1-30 μm.
The wafer shown in Figure Id thus constitutes the starting material for the manufacture of semiconductor devices. For the sake of clarity, the thickness of the wafer is greatly exaggerated in Figure 1. As will be clear from the above, its diameter is typically 50-100 mm and its thickness about 0.5 mm.
Semiconductor devices are manufactured from the above- described wafer by selectively etching away the active layer 14 such that a number of separate silicon islands are formed. This is shown in Figure 2, which shows the carrier 2 , an insulating layer 3 consisting of the layers 11, 12, 13 r 23, 21 shown in Figure 1, and a number of separate silicon islands 40, 41, ..., 48. The latter may, for example, have the dimensions 10x10 μm. Then, semiconductor circuits, for example in the form of MOS transistor circuits, are formed in the islands in a known manner by selective doping and contacting. Finally, the wafer is divided in a check pattern (along the dashed lines B-B and C-C shown as example in Figure 2) into the semiconductor devices I, II, III etc. which constitute the end products. Each device consists of a carrier with a number of silicon islands with circuits formed therein. After division of the wafer, there are formed, for example, the devices I, II and III, where , for example, device II consists of the part of the wafer 2 located between lines B-B and C-C and the corre¬ sponding part of the insulating layer 3, and the silicon islands 41-45. Figure 3 schematically shows a picture of the device II with the silicon islands 41-50 prior to enclosing the device.
The semiconductor device according to the invention descri¬ bed above has a high dielectric insulation between the sub- strate and each semiconductor circuit, and hence also between the individual semiconductor circuits. This is achieved since the doped glass, which according to the invention is used as insulation between the carrier and the silicon islands, can be applied in thick layers. As an example a semiconductor wafer has been described above, in which the glass layers 13 and 23 have a thickness of about 1 μm. However, the glass layers may without difficulty be given thicknesses of 2 μm or more. Together with the oxide layers 11 and 21, a total thickness of the insulation layers of 5 μm or more may thus be obtained. In typical cases, an insulation strength of several kv may be attained. The manu¬ facturing process according to the invention makes it possible to attain this high insulation in an advantageous manner from the point of view of manufacturing and therefore provides considerable advantages compared with prior art methods.
Since thick insulation layers can be obtained between the carrier material and the semiconductor circuits, the risk of parasitic effects is also reduced to a considerable extent.
Since the doped glass has a low yielding temperature, the bonding of the wafers can be performed at a low temperature (< 900°C) . In this way, the risk of defects being generated in the active semiconductor layers is greatly reduced, and better electrical properties may be obtained in the finished devices.
The oxide layers 11 and 21 provide a good and controlled adhesion of the other layers to the silicon wafers.
In the foregoing, a device has been described in which the carrier wafer 2 only has the function of serving as a carrier for the active semiconductor circuits. However, the method and the semiconductor wafer according to the inven¬ tion can be used also in other applications, for example for the manufacture of semiconductor devices in which the carrier wafer consists of a silicon wafer in which a power component, for example a thyristor, is formed. The semicon¬ ductor circuits arranged on the carrier wafer may then, for example, consist of control electronics for the power com¬ ponent.
Further, an embodiment has been described above in which both of the joined semiconductor wafers consist of silicon wafers. Alternatively, of course, other semiconductor materials may be used for the wafer (1) in which the active layers are to be produced. For example, this wafer may consist of germanium or a germanium-silicon mixture, or or another semiconductor material, such as gallium arsenide (Ga As) or indium phosphide (InP) . In the embodiment described above, the oxide layers 11 and 21 consist of thermal oxide. Alternatively, these layers may be generated in some other known way, for example by a CVD process. As an example a thickness of the oxide layers of about 50 nm have been mentioned above. Alternatively, however, these layers may be made considerably thicker, without any problem up to about 1 μm.
In the embodiment above, the oxide layers consist of an oxide of the semiconductor material (silicon) . Alternati¬ vely, these layers may consist of another material, for example zirconium oxide or aluminium oxide. Although the oxide layers provide the advantages described above, it is possible in certain cases to eliminate one of or both of the layers.
Instead of the diffusion barrier layer 12 of silicon nitride described above, layers of other materials with a correspon¬ ding function may be used, for example titanium nitride or zirconium nitride. According to an alternative embodiment of the invention, the oxide layer 21 may consist of an oxide generated in some other way, for example of undoped CVD- oxide. A layer of the latter kind has good diffusion- preventing properties, and the special barrier layer 12 can then be eliminated.
It has been described above how the barrier layer 12 and the glass layers 13 and 23 are deposited with the aid of an LPCVD process. Alternatively, a plasma-CVD process or so- called atmospheric CVD may be used.
In the embodiment described above, the glass layers 13 and 23 consist of boron-phosphorus-doped glass containing about 4 per cent by weight boron and 4 per cent by weight phos- phorus. Alternatively, only boron or only phosphorus may be used as dopant, and, of course, other dopants than boron and phosphorus (both single dopants and combinations of dopants) may be used, as well as other doping concentrations than those described above. However, it has been found that a particularly low yielding temperature is attained in the glass, and hence particularly good electrical properties attained in the finished semiconductor devices, if boron- phosphorus-doped glass is used, which is doped with 1-10 per cent by weight boron and with 1-10 per cent by weight phosphorus.
In the foregoing, an embodiment has been described in which both wafers are provided with glass layers before the bon¬ ding of the wafers to each other. According to an alter¬ native embodiment of the invention, only one of the wafers is provided with a glass layer. When joining together the wafers, this glass layer is then bonded to the other wafer. It has been found that a good bonding is obtained between the glass layer and that material in the other wafer which is nearest the glass layer, for example silicon, nitride or silicon oxide, and, in principle, the same advantages can be obtained with this embodiment as with the previously descri- bed one with two glass layers.
The device described above is only an example and can be formed in a large number of other ways. The number of semi¬ conductor circuits which are applied to the carrier may be both lower and higher than that described above. In certain cases, several thousand semiconductor circuits may be applied to the carrier. Also other semiconductor circuits than purely electrical ones can be produced in the active layers, for example optoelectronic devices or circuits.

Claims

1. A semiconductor device comprising a carrier material in the form of a silicon wafer (2) , at least one active layer (14) of a semiconductor material, in which semiconductor circuits (41, 42 ... 50) are produced, and an electrically insulating layer (11, 12, 13, 23, 21, 3) between the carrier material and the active layers, characterized in that the insulating layer comprises a doped glass layer (13, 23).
2. A semiconductor device according to claim 1, characterized in that the glass layer (13, 23) consists of a glass doped with boron and phosphorus.
3. A semiconductor device according to claim 2, characterized in that the glass layer (13, 23) contains between 1% and 10% boron and between 1% and 10% phosphorus.
4. A semiconductor device according to any of claims 1-3, characterized in that the glass layer consists of two glass layers (13, 23) which are bonded to each other.
5. A semiconductor device according to any of claims 1-4, characterized in that it comprises a diffusion barrier layer (12) arranged between the glass layer (13, 23) and the active layer (14) .
6. A semiconductor device according to claim 5, characterized in that the diffusion barrier layer (12) consists of a layer of silicon nitride.
7. A semiconductor device according to any of the preceding claims, characterized in that it comprises a layer (21) of silicon dioxide arranged between the glass layer (13, 23) and the silicon wafer (2) .
8. A semiconductor device according to any of the preceding claims, characterized in that it comprises a layer (11) of an oxide, arranged between the glass layer (13, 23) and the active layer, of the semiconductor material included in the active layer.
9. A semiconductor wafer for manufacturing semiconductor devices and comprising a carrier material in the form of a silicon wafer (2), an active layer (14) of a semiconductor material for the production of semiconductor circuits, and an electrically insulating layer (11, 12, 13, 23, 21, 3) between the carrier material and the active layer, characterized in that the insulating layer comprises a doped glass layer (13, 23).
10. A semiconductor wafer according to claim 9, characterized in that the glass layer (13, 23) consists of a glass which is doped with boron and phosphorus.
11. A semiconductor wafer according to claim 10, characterized in that the glass layer (13, 23) contains between 1% and 10% boron and between 1% and 10% phosphorus.
12. A semiconductor wafer according to any of claims 9-11, characterized in that the glass layer (13, 23) consists of two layers which are bonded to each other.
13. A semiconductor wafer according to any of claims 9-12, characterized in that the wafer comprises a diffusion barrier layer (12) arranged between the glass layer and the active layer.
14. A semiconductor wafer according to claim 13, characterized in that the diffusion barrier layer (12) consists of a layer of silicon nitride.
15. A semiconductor wafer according to any of claims 9-14, characterized in that it comprises a layer (21) of silicon dioxide arranged between the glass layer (13, 23) and the silicon wafer (2) .
16. A semiconductor wafer according to any of claims 9-15, characterized in that it comprises a layer (11) of an oxide, arranged between the glass layer (13, 23) and the active layer, of the semiconductor material included in the active layers.
17. A method for manufacturing a semiconductor wafer intended for manufacturing semiconductor devices, the semiconductor wafer comprising a carrier material (2) in the form of a silicon wafer, an active layer (14) of a semicon¬ ductor material for producing semiconductor circuits, and an electrically insulating layer (11, 12, 13, 23, 21, 3) between the carrier material and the active layer, characterized in that at least one of the carrier wafers (1) and a second wafer (2) of said semiconductor material are provided with a layer of doped glass (13, 23), whereupon the two wafers are joined together by means of bonding and with the glass layer of each wafer facing the other wafer.
18. A method according to claim 17, characterized in that the glass layers (13, 23) consist of quartz glass doped with boron and phosphorus.
19. A method according to claim 18, characterized in that the glass layers (13, 23) contain between 1% and 10% boron and between 1% and 10% phosphorus.
20. A method according to any of claims 17-19, characterized in that a diffusion barrier layer (12) is applied to said second wafer (1) prior to the application of a glass layer (13) to the wafer.
21. A method according to claim 20, characterized in that the diffusion barrier layer (12) consists of a layer of silicon nitride.
22. A method according to any of claims 17-21, characterized in that after application of a glass layer (13, 23) to a wafer, the wafer is heated to the yielding temperature of the glass to attain an increased evenness in the surface of the glass layer.
23. A method according to any of claims 17-22, characterized in that the silicon wafer (2), prior to the application of a glass layer (23) to this wafer, is provided with a layer (21) of silicon dioxide.
24. A method according to any of claims 17-23, characterized in that said second wafer (1) , prior to the application of a further layer to this wafer, is provided with a layer (11) of an oxide of the semiconductor material included in the wafer.
PCT/SE1992/000707 1991-10-15 1992-10-08 A semiconductor device, a semiconductor wafer for manufacturing a semiconductor device and a method for manufacturing such a semiconductor wafer WO1993008597A1 (en)

Applications Claiming Priority (2)

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SE9102984-3 1991-10-15
SE9102984A SE469863B (en) 1991-10-15 1991-10-15 Semiconductor component, semiconductor disk for producing semiconductor component and method for producing such semiconductor disk

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CN107004639A (en) * 2014-07-08 2017-08-01 麻省理工学院 Substrate manufacture method

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EP0209173A1 (en) * 1985-06-20 1987-01-21 Koninklijke Philips Electronics N.V. Method of manufacturing semiconductor devices comprising the mechanical connection of two bodies
US4826787A (en) * 1986-03-18 1989-05-02 Fujitsu Limited Method for adhesion of silicon or silicon dioxide plate
EP0418737A1 (en) * 1989-09-13 1991-03-27 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor substrate dielectric isolating structure
US5028558A (en) * 1988-04-13 1991-07-02 U.S. Philips Corporation Method of manufacturing a silicon on insulator semiconductor

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
EP0209173A1 (en) * 1985-06-20 1987-01-21 Koninklijke Philips Electronics N.V. Method of manufacturing semiconductor devices comprising the mechanical connection of two bodies
US4826787A (en) * 1986-03-18 1989-05-02 Fujitsu Limited Method for adhesion of silicon or silicon dioxide plate
US5028558A (en) * 1988-04-13 1991-07-02 U.S. Philips Corporation Method of manufacturing a silicon on insulator semiconductor
EP0418737A1 (en) * 1989-09-13 1991-03-27 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor substrate dielectric isolating structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107004639A (en) * 2014-07-08 2017-08-01 麻省理工学院 Substrate manufacture method
CN107004639B (en) * 2014-07-08 2021-02-05 麻省理工学院 Substrate manufacturing method

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SE9102984D0 (en) 1991-10-15
SE469863B (en) 1993-09-27

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