WO1992022129A1 - Generateur de signaux ameliore et appareil d'essai - Google Patents

Generateur de signaux ameliore et appareil d'essai Download PDF

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Publication number
WO1992022129A1
WO1992022129A1 PCT/GB1992/001008 GB9201008W WO9222129A1 WO 1992022129 A1 WO1992022129 A1 WO 1992022129A1 GB 9201008 W GB9201008 W GB 9201008W WO 9222129 A1 WO9222129 A1 WO 9222129A1
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WO
WIPO (PCT)
Prior art keywords
frequency
marker
signal
dac
signals
Prior art date
Application number
PCT/GB1992/001008
Other languages
English (en)
Inventor
Graham Capper
Chris Turl
Original Assignee
Wiltron Measurements Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB919112175A external-priority patent/GB9112175D0/en
Priority claimed from GB919112177A external-priority patent/GB9112177D0/en
Application filed by Wiltron Measurements Limited filed Critical Wiltron Measurements Limited
Publication of WO1992022129A1 publication Critical patent/WO1992022129A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B23/00—Generation of oscillations periodically swept over a predetermined frequency range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006—Functional aspects of oscillators
    • H03B2200/0092—Measures to linearise or reduce distortion of oscillator characteristics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2201/00—Aspects of oscillators relating to varying the frequency of the oscillations
    • H03B2201/02—Varying the frequency of the oscillations by electronic means
    • H03B2201/0225—Varying the frequency of the oscillations by electronic means the means being associated with an element comprising distributed inductances and capacitances
    • H03B2201/0241—Varying the frequency of the oscillations by electronic means the means being associated with an element comprising distributed inductances and capacitances the element being a magnetically variable element, e.g. an Yttrium Iron Garnet

Definitions

  • This invention concerns apparatus for generating radio frequency (RF) signals up to 20GHz in frequency and beyond and test apparatus for use therewith whereby the response of electrical and electronic components and assemblies (devices) can be tested at specific frequencies and over bands of frequencies.
  • RF test apparatus and the signal generator will be referred to as an RF signal generator while the components and assemblies under test will be referred to as RF components or devices - it being understood that the expression RF is not in any way limiting as to the frequency of the generated signal or the frequency at which a component or device under test is to perform.
  • the test apparatus typically comprises a signal analyser.
  • a method of setting the frequency of the source comprising the following steps:
  • leading and trailing edges may be detected during a single sweep from just below to just above the known above the known marker pulse, and the trailing edge is detected by sweeping the frequency in the reverse direction from just above to just below the known marker.
  • the initial calibration of the fine tuning control element (step 2) enables a scalar factor to be determined for the fine tuning control element by which a change of control signal therefor results in a known change in frequency, and a frequency other than that relating to the computed arithmetic mean may be derived with reference to the computed frequency control signal value (corresponding to the arithmetic mean of the leading and trailing edge values of the known marker pulse) together with the scalar, to arrive at a computed value for the fine tuning control element which will produce a shift (if needed) in the oscillator frequency from that to which the known marker relates to the desired frequency.
  • the process may be repeated for the second known marker and the scalar for the fine tuning control computed with reference to the known frequency step between the two marker frequencies and the values of the two frequency control signals computed for the two known marker frequencies, thereby to enable a more accurate computation of the fine frequency control scalar which may then be employed to compute the fine frequency control signal for shifting the oscillator frequency to any frequency intermediate the two known marker f equencies.
  • start and stop frequencies of a sweep are to be defined the above techniques may be employed to determine the control signals for the oscillator tuning control elements at the beginning and end of the sweep. Where the latter is determined by specifying a centre frequency and a swept range, centered on the centre frequency, a frequency controlling signal for determining the start and stop frequencies may be derived using historical calibration data for the oscillator frequency control elements and the above-described techniques employed to redefine the end points of the sweep, correction signals being generated thereby to adjust the oscillator frequency at the start and stop positions as appropriate, to thereby obtain a more accurately defined frequency sweep.
  • the above described techniques may be performed manually by the user of the instrument but more preferably are performed automatically under microprocessor control and to this end a programmable central processor and memory are employed with suitable interfaces to enable data relating to markers, leading and trailing edges thereof, computed positions, related frequencies and the like to be stored and updated and employed for controlling the frequency of oscillation.
  • the oscillator is a YIG oscillator having a main coil for relatively coarse frequency adjustment and an fm coil by which fine tuning of the oscillator frequency can be performed.
  • the coarse calibration comb of signals is preferably generated using a 500MHz crystal controlled source and a harmonics generator for generating at least 50 harmonics above the 500MHz fundamental
  • the fine calibration comb signal is based on a 25MHz fundamental (which itself may be derived by division from the 500MHz source) together with its own harmonic generator for generating an appropriate number of harmonics of the 25MHz fundamental.
  • Calibration may be performed by comparing the YIG oscillator RF output with either or both of the combs of harmonics so as to produce marker pulses as the YIG oscillator frequency sweeps through each marker pulse in the comb signal, each marker being generated by detecting a beat signal produced by interaction between the YIG oscillator RF signal and one of the harmonically related markers.
  • a symmetrical technique is employed for generating each marker pulse so that the position at which marker pulse begins before the point of zero beat frequency between the two signals, is spaced by substantially the same amount therefrom as is the position thereafter at which the marker pulse ends so that the zero beat frequency position can be determined by the half-way point of the marker pulse.
  • the marker pulses By relating the marker pulses to the varying parameter (typically amplitude) of a signal supplied to a frequency controlling element, so the value of that parameter corresponding to the zero beat frequency position is determined by computing the arithmetic mean of the two values of the frequency controlling signal corresponding to the leading and trailing edges of each marker pulse.
  • Each marker pulse may be digitised using a digital sampling technique which is initiated before the leading edge of the pulse and continues until after the trailing edge of the pulse has been seen.
  • the above described techniques do rely on the marker pulses having symmetry about their centre positions (corresponding to zero beat frequency) and an inspection of the digital profile of a marker pulse may be performed to enable the symmetry or otherwise of the pulse to be checked.
  • the marker pulse profile may be displayed by the display if desired.
  • the invention also lies in apparatus for generating an RF signal adapted to be calibrated and set up in accordance with any of the foregoing methods.
  • the invention also lies in testing apparatus comprising an RF source (as aforesaid) an RF signal detector together with a central control unit for controlling the frequency of operation of the RF source and controlling the operation of the detector.
  • the apparatus may include a signal analyser and display.
  • At least the source, the detector and central control unit are incorporated within a unitary housing to facilitate the transfer of data between the central control unit and the source and the detector.
  • signal analysing apparatus and display apparatus may also be incorporated in the same housing together with any power supplies and environmental controlling devices such as temperature controlling elements .
  • T ⁇ ve apparatus ⁇ aa ⁇ also include a paratus as describe d in our copending application reference C262/W and optionally may be operated in accordance with the methods of calibration and setting-up described therein.
  • test apparatus for use in the GHz range of RF frequencies, by which the response of devices under test can be ascertained to signals in that range, comprises:
  • an RF source for generating RF signals up to tens of GHz with output means for delivering signals to a device under test;
  • RF detector means adapted to receive signal(s) from a device under test and generate signal(s) indicative of the attentuation of the device to the supplied RF signal(s);
  • microprocessor based control means receptive of signals from and adapted to generate control signals for both the RF source and the detector for calibration and control of the source and to optimise the sensitivity of the detector to the RF signals and decrease its sensitivity to electrical noise signals
  • FIG. 1 is a block schematic diagram of an RF test apparatus constructed in accordance with the invention
  • FIG. 2 is a similar block schematic diagram of the CPU based control module of Figure 1;
  • Figure 3 is a block schematic diagram of that section of the system of Figure 1 which controls the YIG oscillator and provides for marker detection;
  • Figure 4 is a block circuit diagram of an RF souce for generating signals in the 8-27GHz range
  • Figure 5 is a block circuit diagram of an RF source for generating signals in the dc-8GHz range
  • Figure 6 is a block circuit diagram of that part of the RF signal generator which generates 500MHz markers
  • Figure 7 is a block circuit diagram of that part of the RF signal generator which generates 25MHz markers for use with the 500 MHz markers;
  • Figure 8 is a block circuit diagram of a voltage controlled oscillator source for generating a comb of frequencies
  • Figure 9 is a block circuit diagram of a frequency divider module as employed in the apparatus of the foregoing drawings;
  • Figure 10 is a block circuit diagram of a frequency divider module and 25MHz marker pulse generator, for use with the low band RF source of Figure 5;
  • Figure 11 is a block circuit diagram of those parts of the system which perform noise signal compensation on the RF signals, processed by the analyser, of which it forms a part;
  • Figure 12 illustrates a common housing testing apparatus embodying the invention.
  • FIG. 1 An overall system embodying the invention is shown in Figure 1 in which a device under test 10 is supplied with an RF signal from the output 12 of the test system and after passing through the device under test 10, the signal is applied to the input 14 of a signal analyser 16. The latter produces via ADC 18 a digital signal whose value is proportional to the amplitude of the RF signal at the input 14.
  • This digital signal is routed via a central processor unit 20 (based on an Intel 80C88-2 processor) to a display 22 which may be LCD or CRT based, to produce a visible trace representative of the attentuation of the device 10 to different frequencies.
  • a central processor unit 20 based on an Intel 80C88-2 processor
  • the processor unit 20 produces additional signals for generating in the display calibration traces for reference, corresponding to amplitude and frequency, which additional signals are supplied also to the display.
  • the operation of the processor unit is under the control of front panel controls which may include a keyboard 24, and the latter and the control unit are not only employed to control the display 22 but also the operation of the overall system as will be described later.
  • the RF signal is obtained from a YIG oscillator 26, control signals for which are derived from a source control unit 28 itself under the control of the processor unit 20.
  • the unit 28 includes inter alia Digital to Analogue devices (DAC's) 30 for generating currents for driving the YIG oscillator coils from digital signals and a detector circuit 32 adapted to detect markers generated by a crystal controlled oscillator contained in a marker generator 34.
  • DAC's Digital to Analogue devices
  • additional RF signal sources such as shown in dotted outline at 36 may be provided, and the appropriate source (YIG or otherwise) selected and caused to operate under the control of the source control unit 28 as required by demand signals from the processor unit 20.
  • YIG or otherwise
  • down conversion techniques may be employed such as described in UK Patent Specification 2181911 to achieve RF frequencies below 2GHz. It is to be understood that the references to a YIG oscillator in Figure 1 is intended to cover all such systems as appropriate.
  • FIG. 2 is a block schematic circuit diagram of the control unit of item 20 of Figure 1.
  • the actual processor typically an Intel 80C88-2 chip
  • the control signals therefor clock, reset and wait state signals
  • the usual address and data buffers are denoted by 42 and 44 respectively and data from an EPROM 46 and RAM 48 is supplied via the data bus 50 either to the processor 28 (via the buffer 44) or to the output/input data buffer 52. Externally generated data supplied to the buffer 52 can also be routed either to the processor 38 and/or the EPROM 46 and/or RAM 48.
  • Address information from the processor 38 is decoded by memory select decode unit 54 and is supplied to the address line of the EPROM direct and the RAM via control unit 56, by which inter alia data in the RAM can be preserved in conventional manner by refresh techniques.
  • Interrupts for controlling inter alia the processor 38 are obtained from an interrupt generator 58 which also receives interrupts from external sources along line 60 and supplies interrupts to and receives interrupts from other devices along interrupt line 62 and the main data bus 50.
  • Certain address signals from buffer 42 on address line 64 are to enable internal devices and a device selector 66 is supplied with the address signals and in turn enables different I/O ports 68, 70, 72 and 74 depending on the address signal, via address line 76.
  • a time slice generator 78 also derives signals from the output signal of decoder 66.
  • the input signal 40 on line 41 is derived from a graphics display processor (not shown) and is a signal which inhibits operation of the CPU 38 until the display CPU is ready to change the graphics display.
  • the interrupts on line 60 will in general be derived from front panel and/or keyboard, to prevent operation of the CPU 38 until the front panel controls and/or keyboard have been left untouched for a programmed interval of time.
  • the time slice device 78 is a monostable device which fires every 30ms to trigger the controller 58.
  • the address bus 82 and I/O select bus 86 provide the signals for addressing devices external to the unit 20, and routing signals to and from the unit 20 and between other devices external thereto, and enabling the disabling devices in units external to 20.
  • the address bus 82 controls addressable devices in other units (yet to be described)
  • the signals on 86 enable for example selected DAC's, the YIG oscillator, front panel and/or keyboard controls etc.
  • the data bus 58 provides inter alia numberical values for the DAC's 30 in the YIG control unit 28.
  • the GPIB port 68 is a parallel port allowing remote control to IEE 488.
  • the switched filter port 70 provides control signals for switching different remote filters into and out of operation (to be described) and in the same way port 74 provides control signals for the step attenuator incorporated in the YIG based RF source to be described with reference to Figures 4 and 5.
  • the bus 59 is an important element in that it contains information by which the CPU 38 can be informed as to where a particular interrupt signal has originated.
  • the front panel may generate an interrupt signal whereupon an appropriate signal appears on the bus 59 which via data bus 50 relays this to the CPU.
  • the latter is programmed internally to address the front panel to determine what front panel control has been altered.
  • keyboard interrupts identify that the CPU 38 should interrogate the keyboard.
  • the processor control unit 20 includes an address buffer 80 for routing addresses to external devices (not shown) via line 82 and an input/output selector 84 by which external input and output devices (not shown) can be addressed and/or selected to operate in a particular manner by signals along line 86.
  • the data bus for the units external to unit 20 is denoted by 88.
  • the external bus associated with the GPIB port 68 is denoted by 90, and the signal output lines of ports 70- 74 are denoted by 92-96 respectively.
  • Figure 3 shows in more detail the relevant sections of item 28 of Figure 1 for controlling the YIG oscillator 26. - 15 -
  • Data along line 88 is buffered by data buffer 98 onto a data bus 102.
  • Address data and sSlect signals on 82 and 86 are decoded by an input/output decoder 100 onto a bus 104.
  • Address signals on 104 are supplied to different elements of the circuit including a marker detector 106 which will be described later.
  • Data, address and select signals are supplied to the control port 108 within the YIG control circuit which essentially controls the currents flowing in a main YIG coil 110 and a subsidiary FM coil 112.
  • the main YIG coil current is controlled by a summing amplifier 114 one input of which is derived from a digital to analogue converter 116 set to respond to a digital data signal on bus 102 to produce a mean current for the main coil corresponding to the centre of the range which the YIG oscillator is intended to sweep.
  • the frequency range swept by the YIG oscillator is determined by the analogue signal from a second digital to analogue converter 118 again supplied with digital data from bus 102 but additionally with a ramp signal from a third digital to analogue converter 120 also supplied with digital data from bus 102 so as to generate a ramp signal which causes the sweep width DAC 118 to generate an appropriate bi-polar ramping signal to effect the sweep.
  • the output from DAC 118 is shown supplied via switch 122 to the second input of summing amplifier 114.
  • the width DAC output combines with the centre DAC output signal to generate a current for the main YIG coil which starts at a low value and increases to a high value or vice versa, to effect a desired sweep centred about a desired centre frequency.
  • a fourth digital to analogue converter 124 also receives digital data from the bus 102 and supplies an output signal via summing amplifier 126 to control the FM coil current.
  • the frequency change effected by the FM coil is relatively small and the signal from DAC 124 is essentially a fine tuning control.
  • the digital data appropriate to initiating the sweep and causing the YIG oscillator to oscillate at the start frequency are provided to the appropriate DAC'S 116, 118, and the actual YIG oscillator frequency is determined using the marker signals (to be described) and in accordance with the technique described in our British Patent 2181911.
  • Any adjustment needed to the YIG oscillator to bring the frequency within the desired range of accuracy of the start frequency is achieved by generating appropriate digital data and supplying this to the error DAC 124 so as to generate a bi-polar signal for supply to the FM coil to fine tune the YIG oscillator to the desired frequency.
  • switch 122 may be placed in the alternative position shown in dotted outline shown in Figure 3 so that the width DAC output 118 is supplied to summing amplifier 126 and this signal is used to swing the YIG frequency between two extremes within the range of sweep capability determined by the FM coil 112.
  • the centre frequency will be determined by the signal supplied by the centre DAC 116 to the main YIG coil 110 via summing amplifier 114 but with switch 122 in the alternative position, the centre DAC signal will not be altered during the sweep and the change in frequency of the YIG oscillator is achieved solely by changing the signal to the FM coil.
  • Further error adjustment may be made by checking the frequency of the YIG oscillator at the end of the sweep as well as the beginning and noting any change in error DAC signal needed to bring the YIG oscillator frequency to the target frequency at the end of the sweep. Any such change in error signal to be delivered by the error DAC 124 during the sweep can then be apportioned over the sweep in any desired manner either linearly or according to an algorithm so that the error signals produced by the error DAC 124 at the beginning and the end of the sweep produce the precise start and finish points of the sweep and to a first approximation the correct error signal is delivered by the error DAC 124 during the sweep at all intermediate frequencies.
  • Signals for the error DAC may be stored in a memory associated with the processor 38 and the central processor is adapted to interrogate the frequency of the YIG oscillator and compare this with the markers generated by circuit 34 so as to determine precisely the frequency of oscillation and enable error signals to be computed so as to correct the operation of the YIG oscillator to achieve the desired frequency at the beginning and the end of the sweep.
  • Two sets of markers are generated one set at 25MHz intervals and one at 500MHZ intervals. The manner in which these signals generate will be described in more detail in relation to later drawings but for the purposes of Figure 3, the 25MHz spaced markers are shown incoming on line 130 and the 500MHz spaced markers on line 132. Both inputs are supplied to each of an edge detector circuit 134 and 142, one of which is set to determine leading edges and the other trailing edges of pulses appearing on the inputs 130 and 132. The outputs from the detectors 134 and 142 appear on lines 138 and 144 and logic circuits 140 are provided for inspecting the outputs of the detectors to determine one unique condition, namely when a leading edge is detected immediately after a trailing edge. In this situation the logic circuit 140 generates a pulse for delivery along line 141 as a data signal for routing to the microprocessor to inform the latter that a marker pulse has been seen.
  • the precise position of the mid point can be determined from the position of the detected trailing and leading edges and additional logic circuits may be provided to determine the positions of the leading and trailing edges of a dip in amplitude for this purpose.
  • the circuit of Figure 3 will be used with the switch 122 in the position shown where the sweep range is in excess of 40MHz.
  • the alternative position of the switch 122 may be used since sweeps of less than 40MHz can be normally be accommodated by alteration of the current to the FM coil 112 via the summing amplifer 126.
  • Figure 4 shows in detail the essential parts of a high- band RF source for use in a test system according to the invention.
  • the source can be used for signals in excess of 2GHz up to the maximum frequency obtainable from a YIG oscillator, typically between 20-30GHz.
  • a YIG oscillator typically between 20-30GHz.
  • any one user only has a requirement for a range of frequencies well within the overall range capability of a YIG oscillator and typically a variety of instruments may be offered each having the same basic design but with component selection and YIG oscillator design specific to the restricted band for that particular users requirements.
  • an instrument might well be offered having a range 2-8.4GHz, another between 8-12.4GHz, another between 12.4-20GHz etc.
  • the YIG oscillator 148 is shown driven by coils 110 and 112 as previously referred to and the output from the YIG oscillator is supplied to a control modulator 150 to which an automatic level control signal is supplied along line 152 and a gating pulse along 154.
  • the latter is used to gate the RF signal since in practice it may be desirable to be able to gate the RF signal without turning the YIG oscillator on and off.
  • the signals passed by the circuit 150 enter a directional detector 156 the operation of which is to sample signals passing from left to right in Figure 4 but not from right to left.
  • the circuit is based on a diode detector so as to generate an amplitude proportional signal for controlling the level of the RF signal supplied thereto via the ALC circuit in the control modulator 150. To this end the signal along line 157 is supplied to the ALC input 152.
  • the circuit operates so as to restrict the amplitude of the signal supplied from the directional detector 156 so that the RF signal is substantially constant in amplitude throughout the working range of the oscillator. Normally this will mean restricting the amplitude of the RF signal to the lowest amplitude obtained and normally amplitude reduces with frequency so that the lower frequencies will be attenuated more than the higher.
  • the RF output appears at the output socket 158 and an optional user controlled step attenuator 160 may be inserted as shown to allow selective attenuation of the RF signal.
  • a step attenuator is essentially frequency independent so that any attenuation introduced is uniform across the range.
  • Marker pulses at 500MHz spacings and 25MHz spacings are obtained using the circuit in the lower section of Figure 4.
  • part of the RF signal from the YIG oscillator 148 is tapped off from the control modulator 150 via line 161 to form one input to a sampler or mixer 162.
  • the other input for the sampler is a comb of frequencies produced from a voltage controlled oscillator and appropriate harmonic generating circuit 164. These will be described in greater detail in relation to later drawings. It is sufficient to note that the signal supplied to the sampler 162 is made up of a 500MHz fundamental and a large number of harmonics (typically 50 or more) each spaced from the other by 500MHz.
  • the effect of the sampler is to produce a beat signal as the YIG oscillator signal sweeps through frequencies corresponding to the different harmonics in the input along line 165 and as each coincidence occurs, the difference signal from the sampler 162 will sweep from a high frequency through a low frequency (possibly DC) up to a high frequency again.
  • An IF amplifier 166 is set to produce 500MHz pulses in the region of each frequency excursion through DC along line 167 and a mid-range sweep from 250MHz through DC back up to 250MHz is supplied along line 169. This signal is a by-product of the action of amplifier 166 as will be described later.
  • a divider 168 serves to generate a 25MHz signal from the 500MHz voltage controlled oscillator output of 164. This is also supplied to a 25MHz marker pulse generator 170 which in combination with the signal along line 169 produces a series of marker pulses similar to the 500MHz pulses but of reduced width and spaced by 25MHz intervals as the YIG oscillator is swept through its range.
  • Figure 5 shows an alternative source which can be switched between low and high band operation to give an extended range of frequency from frequencies well below those at which a YIG oscillator will normally oscillate through to signals in the YIG oscillator range.
  • 500MHz and 25MHz marker pulses are required and to this end part of the circuit of Figure 5 is identical to that shown in Figure 4 and is enclosed within dotted outline 34.
  • the YIG oscillator 148 is shown driven by coils 110 and 114 and the control modulator, directional detector and step attenuator operate in the same manner as described in relation to Figure 4, to provide an RF output at 158.
  • the additional circuit elements essentially comprise a down converter 172, switched filter 174 and the alternative 25MHz marker pulse generator 178.
  • the down converter 172 operates in essentially the same manner as that described in our British Patent Specification 2181911 particularly with regard to Figure 7 thereof.
  • Signals in the range 6-8.3GHz are supplied to the down converter along line 176 which includes a local oscillator at the lower frequency to generate a heteradyne signal in the range DC to 2GHz for supply to a switched filter 174.
  • the latter operates on the signal on line 175 from the control modulator 150 or the line 177 from the down converter and provides the RF output signal to the directional detector 156.
  • the switched filter 174 passes the fundamental and removes any harmonics and it is this part of the system which tends to produce different broad band noise as it is switched to allow the passage of lower or higher frequency signals. Compensation for this introduced noise must be provided and is a feature of the circuit.
  • the down converter 172 is included together with the appropriate switched filter 174.
  • the control modulator unit 150 also provides an output signal corresponding to the YIG oscillator frequency to a sampler 162 of the type described in UK Patent Specification 2181911.
  • the device is additionally supplied with a comb signal at 500MHz and harmonics from a voltage controlled crystal oscillator and power amplifier 164.
  • the sampler output is subjected to filtering and processing in an amplifier 166 to provide 500 MHz marker pulses.
  • the amplifier 166 will be described in more detail with reference to Figure 6.
  • the basic 500 MHz signal from oscillator 164 is divided by a divider 168 to produce a 25 MHz signal locked in frequency and phase to the 500 MHz source and this together with a signal which varies from 250MHz to DC and back from the amplifier 166 are supplied to a second amplifier and signal processing device 170 for producing markers separated by 25 MHz.
  • Figure 5 is in many respects similar to Figure 4 except for the down conversion and switched filter which enable the device to operate in the MHz range as well as in the GHz range.
  • a YIG oscillator does not operate reliably much below 2 GHz and consequently for frequencies below 2 GHz the down conversion technique is employed either to enable the overall range of a single instrument to be increased or to permit a low band instrument to be produced.
  • the instrument can be used to generate radio frequency signals from DC to 8.3 GHz. This is done in two separate modes of operation. Below 2 GHz a hetrodyne principle is employed using a local oscillator operating at 6.3 GHz in the down converter 172 so as to obtain frequencies in the range DC to 2GHz which appear at the RF output 158. Above 2 GHz, the RF signal can be derived directly from the oscillator 148 via the modulator 150 and in this mode the down converter 172 is are effectively removed from circuit. The filter 174 is required to remove other products of the heterodyne mixing above 2GHz.
  • the switched filter 174 is a device which is arranged to pass the fundamental but remove any harmonics. By its nature it will tend to introduce electrical noise into the signal so that when the filter is switched in, the electrical noise in the RF output signal at 158 will be different from that when the filter is switched out.
  • the 25 MHz spaced marker pulses from 178 can be compared with the 500 MHZ spaced marker pulses from circuit 166. If there is no offset then it can be assumed that the down converter local oscillator is working correctly. Ideally there should be no offset.
  • S ⁇ B ⁇ rur Figure 6 indicates in greater detail the construction and operation of circuit 166 of Figure 5.
  • the sampler or mixer 162 is supplied with two signals.
  • the first is a comb signal of harmonics at 500 MHz intervals derived from a voltage controlled oscillator 164 as will be described in more detail later. This is applied as input 180.
  • the second input is derived from the control modulator 150 and is denoted as input 182 to the sampler 162.
  • This signal is essentially the output of the YIG oscillator 148 and as the latter is swept from one frequency to another, all intermediate frequencies will be seen at input 182 and will be mixed with the signals from 180.
  • the harmonic content of the signal at 180 is sufficient to extend up to the highest of the frequencies at which the YIG oscillator 148 will operate so that as the latter is swept through its entire range, the output of the sampler or mixer 162 will contain beat frequency signals as the frequency of the signal from the YIG oscillator sweeps through each of the harmonic frequencies in the comb signal from 164.
  • the pattern of beat frequencies at each coincidence will follow a similar pattern and the output signal from the sampler 162 will in each case begin at a high frequency sweep down to a very low frequency or even d.c. and then up again as the point of coincidence is passed.
  • a single marker pulse is derived from the output of the sampler to appear on line L3 for each point of coincidence by first of all amplifying the sampler output in amplifier 184, splitting the signal in the output of 184 by means of a power split 186 and feeding some of the signal via buffer amplifier 188 to a low pass filter 190 whose cutoff frequency is approximtely 10 MHz.
  • Two high gain amplifiers 192 and 194 provide a relatively fast rise time rectangular pulse to one input of a differential amplifier 196 the other input of which is provided with a threshold voltage on line 198 from a potentiometer 200 which is preset during manufacture.
  • the action of the differential amplifier 196 is to produce a relatively square pulse for the duration of the amplitude excursion in the output of amplifer 194 which exceeds the threshold voltage set by potentiometer 200. If the low pass filter has a sharp cutoff at 10 MHz and the amplifiers 192 and 194 are wide band amplifiers, the pulse at input 202 of differential amplifier 196 will be relatively steep sided. The width of the pulse will therefore correspond to approximtely 20 MHz and the halfway point along the width of the pulse will correspond to the point of coincidence of the YIG oscillator frequency with the particular harmonic in the comb signal supplied to input 180 to which the marker pulse refers.
  • a second signal is derived from the output of amplifier 184 which is used to produce the 25 MHz marker pulses between each 500 MHz marker pulse produced by the circuit 170 of Figure 5.
  • the remainder of the signal split by device 186 is amplified in amplifier 204 and passed through a low pass filter 206 having a cutoff frequency of 250 MHz.
  • the filtered output is again amplified by amplifier 208 to appear on line LI.
  • the signal entering the low pass filter 206 will be varying in frequency between very high frequencies and approximately DC as the YIG oscillator sweeps through each of the harmonics in the comb signal supplied to the sampler along line 180. The effect of the low pass filter will be to remove frequencies above 250 MHz.
  • the sampler output signal will always contain a component in the range DC to 250 MHz since, considering a rising YIG oscillator frequency, after the YIG oscillator frequency has equalled and begun to exceed the frequency of the nth harmonic in the comb signal 180, the difference signal will begin to increase until, when the YIG signal is halfway towards the (n+l)th harmonic, the difference signal will equal 250 MHz.
  • the difference signal between it and the nth harmonic will become greater than 250 MHz and will be attenuated by the low pass filter 206 but the new difference signal occurring as a result of beating between the YIG oscillator signal and the (n + l)th harmonic in the comb signal 180, will enter the 250 MHz band and start falling in frequency as the YIG oscillator frequency continues to rise towards the (n + l)th harmonic.
  • the output signal along line LI will therefore cycle between 250 MHz and a very low frequency or DC and back to
  • FIG. 7 shows in detail the construction and operation of circuit 170 of Figure 5.
  • MHz pulse generator of Figure 7 has two input signals. The first is derived from line LI output of Figure 6 and comprises the 250 MHz to DC to 250 MHz varying signal obtained as the YIG oscillator sweeps through the comb of harmonics. This is applied at input 210 of sampler 212.
  • the second input is a 25 MHz pulse train obtained from divider 168 (see Figure 5) the construction and operation of which will be described in more detail later.
  • This is applied along line L2 to two amplifiers 214 and 216 to produce a suitable signal for driving a step recovery diode circuit 218 (which will be described in more detail later) to produce a comb of harmonics based on a fundamental of 25 MHz.
  • the characteristic of the diode is selected so as to produce at least 10 harmonics so that signals at 25 MHz intervals up to 250 MHz are obtained.
  • the comb signal is amplified by amplifer 220 and provides the second input to the sampler or mixer 212.
  • the output of the sampler is amplified by a wide band amplifier 222 and then subject to low pass filtering by a first low pass filter 224 having a cutoff frequency of 1 MHz.
  • the filtered signal is amplified again by amplifier 226 and again filtered by a second low pass filter 228 again having a cutoff frequency of 1 MHz.
  • the filtered output signal is amplified by two amplifiers 230 and 232 to drive a further low pass filter 234 having a cutoff frequency of 400 KHz.
  • the output signal on line 236 thus comprises signals in the range 400 KHz down to zero and back up to 400 KHz again as the frequency bearing signal on line LI sweeps through each of the 25 MHz harmonics in the comb signal from 218.
  • the signals on line 236 are supplied as one input to a differential amplifier 238 the other input of which at 240 is derived by summing two signals via summing resistors 242 and 244.
  • the action of differential amplifier 238 is to produce a generally reactangular pulse for the duration of each cyclic variation of frequency from low pass filter 234 between 400 KHz through zero and back to 400 KHz.
  • the signal applied to input 245 takes account of the variation of YIG oscillator output with frequency and therefore will tend to fall in value on the YIG sweep frequency increase.
  • the rectangular pulses so produced appear on line 246 and are centered about frequencies in the rising frequency YIG oscillator output correspond to the harmonics in the comb signal from generator 218. Twenty such pulses will therefore be produced in succession as the YIG- oscillator sweeps from one 25 MHz harmonic up to and through the next in the signal from the comb generator 218.
  • Figure 8 shows in detail the construction and operation of the voltage controlled oscillator circuit of 164 in Figure
  • This circuit serves to provide a comb output comprising a fundamental at 500 MHz and at least 50 harmonics above 500 MHz each separated by 500 MHz from adjoining harmonics.
  • a primary signal is generated by an oscillator 248 the frequency of which is determined by a control voltage on line 250 derived from an active feedback loop. The latter will be described in more detail in relation to Figure 9 from which two signals are derived for application at inputs 252 and 254 respectively of a differential amplifier 256.
  • a high pass RC feedback loop 258 is connected between input 252 and the amplifier output line 250 and a second similar RC network 260 is provided between input 254 and earth.
  • the oscillator 248 is controlled so as to produce a stable 500 MHz signal which is split in a power splitter 262 to provide an input signal to the first of two amplifiers 264 and 266 the output of which comprises a 500 MHz drive signal on the line 268 to a divider circuit (to be described) for producing a lower frequency of 25 MHz.
  • the other signal from the power splitter 262 is amplified by a chain of amplifiers 270,272,274 and 276, to provide a gain of 27 dB at 500 MHz before the signal is applied to a step recovery diode based comb generator circuit 278.
  • the diode characteristic is selected so as to produce at least 50 harmonics based on the 500 MHz fundamental signal in a comb signal at output 280.
  • the latter provides the input for sampler (mixer) 162 of Figures 5 and 6.
  • Figure 9 illustrates the construction and mode of operation of the divider 168 of Figure 5.
  • the function of the divider circuit is to produce two lower frequency signals from the 500 MHz output signal 268 of Figure 8.
  • the fist signal (at 25 MHz) comprises the 25 MHz input on line L2 of the 25 MHz marker generator 170 of Figure 5.
  • the second signal at 10 MHz is compared with another 10 MHz signal derived from a crystal controlled oscillator to generate the control signals for the feedback loop generating the voltage control signal for the voltage controlled oscillator 248 described with reference to Figure 8.
  • the 25 MHz output signal is obtained by two stages of division. To this end the 500 MHz signal is divided by 10 in divider 282 to produce a signal at 50 MHz and the 50 MHz signal is divided by two in divider 284 to produce a 25 MHz output signal on line 2.
  • the second signal is obtained by a third divider 286 to which is supplied the 50 MHz signal. 286 divides by 5 to produce a 10 MHz signal on line 288 which provides one input to a phase detector 290.
  • a crystal controlled 10 MHz oscillator 292 in a temperature controlled environment (not shown) so as to maintain a very high stability 10 MHz signal provides an output signal which is buffered by amplifier 194 to provide the second 10 MHz input to the phase detector 290.
  • the latter generates signals on lines 296 and 298 for supply to input terminals 252 and 254 of the differential amplifier 256 forming the feedback loop controlling the frequency of oscillation of the voltage controlled oscillator 248 of Figure 8.
  • the phase detector indicates whether the 10 MHz signal on line 288 is increasing or decreasing in frequency and produces feedback signals to control the frequency of the oscillator 248 accordingly.
  • Figure 10 shows the construction and operation of the 25 MHz hetrodyne amplifier 178 of Figure 5 by which 25 MHz marker pulses are derived in the low frequency range of operation i.e. d.c. to 2 GHz when the down converter 172 is in operation.
  • 25 MHz spaced pulses are generated by marker pulse generator 170 these are related to the 500 MHz pulses and in the lower frequency ranges (up to 2 GHz) it is not essential for 500 MHz marker pulses to be generated in order to be able to determine the frequency of the YIG oscillator by hetrodyne principles. In the range 0 - 2 GHz, it is merely sufficient to generate 25 MHz spaced marker pulses from 25 MHz up to 2 GHz and this is achieved by the circuit of Figure 10.
  • the circuit includes two inputs.
  • a first comprises an RF takeoff from the down converter 172 and comprises line 173 of Figure 5.
  • the other input is a signal derived from a crystal controlled oscillator 300 which supplies an accurate frequency signal at 25 MHz along line 302.
  • the signal on line 302 is amplified by two amplifiers 304 and 306 which drive a step recovery diode comb generator circuit 308 to produce up to 100 harmonics based on 25 MHz in the output signal line 310. Further amplification in amplifier 312 provides the comb signal on line 314.
  • the signals on lines 173 and 314 are combined in a sampler (mixer) 316 and the output from the sampler appears along line 318.
  • Marker pulses are produced by subjecting the varying frequency signal on line 318 to low pass filtering by a first low pass filter 320 having a cutoff frequency of 1MHz, amplifying the filtered signal in amplifier 322, further low pass filtering in a low pass filter 324 having a cutoff frequency of 500 KHz and further amplification by means of amplifier 326.
  • the pulses so obtained provide one input to a differential amplifier 328 the other input of which is derived from the addition of two signals one from a potentiometer 330 and the other from a threshold tracking of the voltage source.
  • differential amplifier 328 The operation of differential amplifier 328 is to produce a rectangular pulse in the output at 332 at each point of frequency coincidence during a sweep of frequency from the down converter with one of the harmonics from the comb generator 308.
  • the effect of the low pass filters 320 and 324 is to control the duration of each pulse so that it starts approximately 500 KHz before the coincidence of the down converter frequency and one of the harmonics in the signal on line 310, to a point at which the down converter signal exceeds the nearest harmonic by 500 KHz.
  • the YIG oscillator Since the lowest frequency at which the YIG oscillator will operate reliably is well defined, it is readily straightforward to determine accurately the frequency at the beginning of a sweep by adjusting the YIG oscillator to operate at a frequency just below 2 GHz and which differs from 2 GHz by less than 25 MHz. As the YIG oscillator is increased in frequency the first point of coincidence (25 MHz marker pulse at 332) will correspond to the 2GHz frequency of the YIG oscillator and by counting the 25 MHz markers as they occur so the frequency of oscillation of the YIG oscillator can be determined accurately by reference to the 25 MHz marker pulses.
  • the precise frequency of oscillation of the YIG oscillator can be adjusted within a range of approximately 25 MHz by adjustment of the current flowing in the FM coil so it is possible to adjust the YIG oscillator frequency to any frequency intermediate to 25 MHz's markers by first adjusting the main coil current to produce oscillation at the closer of the two markers on one side or the other of the desired frequency, and thereafter adjusting the current to the FM coil by a calibrated amount so as to adjust the YIG oscillator to the desired frequency of operation.
  • FIG 11 illustrates in detail the construction of operation of the signal detector shown only basically in Figure 1 at 16.
  • the detector 334 converts the RF signal transmitted by the device under test (10 in Figure 1) into a low frequency signal or d.c. level. This is supplied to an instrumentation amplifier 336 the output of which is further amplified by 338 to provide an output signal the amplitude or d.c. level of which can be digitised by the ADC 18 (not shown in Figure 11) before transmission to the control processor unit 20 and thence to the display drivers.
  • the signals to be detailed will typically be below 100 microvolts and at these signal levels it is important to compensate for errors produced by voltage offsets produced by amplifiers following the detector 334, and for wide ⁇ band noise generated from within the RF signal source.
  • correction signals are derived by the micro ⁇ processor unit 20 (as will hereinafter be described) and after digital to analogue conversion by DAC 340 the coarse signal (for amplification by amplifier 342) and the fine control signal (for amplification by amplifier 344) are combined by mixer 346 for combination with the output signal of amplifier 336.
  • the current value for the signals supplied from the CPU 38 ( Figure 2) are obtained by turning off the YIG oscillator 26 and any other RF source and noting the value of the signal V a 348.
  • the processor 38 is programmed to produce two digital values (the coarse and fine feedback signals) to produce a signal at the output of 346 which when combined with the output of 336 reduces V tP zero.
  • the noise introduced by the amplifiers 338 and filters etc will tend to be at a constant level and the wide band noise introduced by the source can likewise be assumed constant for frequency sweeps which do not involve a source change. However if the sweep covers a number of Bands for each of which the wide-band noise is different, it is necessary to initiate the feedback signal compilation at the beginning of the sweep and at each band/source change.
  • the values of the coarse/fine control signals may be derived at the beginning of each sweep and at each band/source change or the values may be computed and stored in a look-up table or memory (not shown) which can be addressed by the processor 38 during a sweep as band and/or source are changed, to provide the appropriate correction signals at the output of 346.
  • the coarse DAC signal provides a bipolar output voltage to cover the main range of correction and the fine DAC signal provides for the accurate setting of the noise cancelling signal.
  • FIG 12 there is shown an RF test apparatus having an RF output socket 410 and an input socket 412 between which a device under test 414 is connected via leads 416, 418.
  • a Keyboard 420 power on/off switch and controls 424 enable the user to set up the apparatus to deliver either a fixed frequency RF signal or a sweep signal (which varies in frequency through a preselected range of frequencies) to the device under test 414.
  • an RF detector and instrumentation amplifier (not shown) for producing a signal whose magnitude is proportional to at least the amplitude of the RF signal transmitted by the device 414.
  • the magnitude is displayed by a trace or bar graph (or the like) against frequency, in a display (typically a CRT based display) 426.
  • Further displays may be provided as at 428, 430 to indicate eg digitally the start and stop frequencies of the range of frequencies applied to the device 414.
  • SUBSTITUTESHEET making up the test apparatus aforesaid enables feedback data to be supplied from the detector and the RF source to the control unit to enable control and correction signals to be generated by the microprocessor for supply to the detector and amplifier to compensate for different electrical noise levels due to range and mode changes in the RF source, thereby enabling a greater consistency of sensitivity to be obtained over the swept ranges of frequency than would otherwise be the case.
  • the frequency source (YIG) 148 is designed to sweep from a start frequency “FI” to a stop frequency “F2" and the microprocessor based control unit is programmed accordingly, see section below entitled “Microprocessor programming” .
  • the source frequency is controlled by four DACs.
  • Start DAC 116 on the main coil Width and Ramp DACs 118 and 128 combined on the main or FM coils, and error DAC 124 on the FM coil.
  • the source is controlled by the Start / Width and Ramp DACs.
  • the Error DAC is used to fine tune the start frequency "Fl” and any adjustment made here will also affect all points within the swept frequency range.
  • the Start DAC is used to set the sweep centre frequency Fl, the Ramp DACs is set to its ramp start value, the Width DAC is set accordingly and the Error DAC is set to give no contribution.
  • the stop frequency "F2" can be obtained by sweeping the Ramp DAC from its start value to its stop value.
  • the source output is obtained by shifting the YIG frequency down using a down-converter.
  • Those types having a 10MHz-8.4GHz range (Types 5417 and 5447) require a down-converter with a 6.3GHz local oscillator and while the 5407, 5409 and 5411 Types use a down-converter with a 10GHz local oscillator.
  • the 5437 and 5447 Types used a YIG oscillator with two oscillator elements. One covers the range 2GHz-8.4GHz and the other covers 8.4GHz-20GHz. It is of course necessary to ensure that the correct oscillator element is active.
  • the Start DAC resolution is quoted, as this specifies to what accuracy it is possible to point to any given frequency, using the main coil only. This is especially important when finding 500MHz markers (or 75MHz markers) .
  • the user is allowed to sweep from a fixed amount below “Band Start” to a fixed amount above “Band Stop” (BS) .
  • min Start (BS-lOMHz)
  • Max stop (BS + 10MHz) which is limited by the software, since it is necessary to be able to reach 500MHz or 75MHz markers on or above Upper Band end (UBE) using Width DAC when on main coil, with Ramp DAC set to Ramp Stop value) .
  • 25MHz - repeated every 25MHz width 0.8MHz (min) to 1.2MHz (max) must be symmetrical about 25MHz centre frequency
  • the marker skirts should be greater than 500kHz and the hole in the middle should be less than 500kHz.
  • the min. width of 10MHz must be symmetrical around each 500MHz marker centre frequency.
  • the Error DAC must always be able to "see” at least two 25MHz markers otherwise it is impossible to define the scalar that allows movement by 25MHz.
  • DACs used to control the YIG frequency. These are:
  • Width DAC which scales the signal from the Ramp DAC, and which controls either the Main or FM coil
  • Calibration is used to determine scaling factors (bits/frequency) for all the DACs, to allow swept frequency conditions to be set-up accurately.
  • scaling factors bits/frequency
  • the DAC profile is a data array, where each member represents a DAC value and this member will hold a value denoting the presence or absence of a marker, for this DAC value.
  • all DACs are 12 bit (ie they can have values in the range 000 to OFFFH) . They are calibrated on the specified coils in the following order using 500MHz or 75MHz (depending on model) and 25MHz hardware markers previously defined.
  • RF power is forced on regardless at a minimum level (0 dBm) , to ensure that hardware markers are generated correctly.
  • the centre point of the marker can be determined since the centre is half way between the marker start and stop.
  • the profile can be searched for all other 500MHz markers. This produces the Start DAC values for all 500MHz markers in the YIG high band.
  • Start DAC can still be set to approximately the right frequency as the default values are calculated for all the marker positions.
  • Start DAC scalar value is determined using the highest and lowest frequency 500MHz (75MHz markers). This is defined as the change in Start DAC value required to move the YIG oscillator through 500MHz (75MHz).
  • a switched filter is fitted as in Types 5417, 5419, 5437, 5447 it must be switched to the highest band. In a multiband unit it is important to ensure that the correct YIG frequency has been selected.
  • Width DAC Determine the position of all the 500MHz (or 75MHz markers) within the swept frequency range, using Width DAC with the Ramp DAC set to its ramp stop position. This allows the Width DAC to be accurately set up for all width frequencies.
  • Start DAC calibration An identical technique is used as in Start DAC calibration, the only difference being that the Start DAC is set to 0, the Ramp DAC is set to its ramp stop value (ie the largest value within its range that can be exactly divided by 400, to allow a 401 point sweep to be actioned) and the Width DAC is swept over its complete range.
  • the Start DAC is set to 0
  • the Ramp DAC is set to its ramp stop value (ie the largest value within its range that can be exactly divided by 400, to allow a 401 point sweep to be actioned) and the Width DAC is swept over its complete range.
  • the initial table of approximate DAC values for marker positions is a direct copy of the Start DAC marker positions as the Start DAC and Width DAC cover very similar frequency ranges.
  • the profile can be searched for all other 500MHz markers.
  • the result should be the Width DAC values for all 500 MHz markers in the YIG low band and the first marker in the YIG high band.
  • the markers previously found in the low band should be left in the profile. Search the profile from the low frequency end looking for three markers as above. After two markers 500MHz apart are found the profile should be searched for all other 500MHz markers. Should now have width DAC values for all 500MHz markers across the full frequency range of the instrument.
  • the markers are found in the low band first since the Start and Width DAC values for these markers will be very similar.
  • the Width DAC In order to allow the Width DAC to be set up for an FM coil sweep, it is necessary to determine a DAC value that gives a width of 40MHz on the FM coil. This allows the Width DAC to be set up for as FM coil sweep when changing the frequency parameters. This can be used for sweep widths less than 40MHz to get lower residual FM and greater width accuracy.
  • Width DAC is set up to drive the FM coil.
  • the accuracy of the down converter local oscillator can be checked by checking the offset of the HET band 25MHz markers from a YIG band 500MHz marker. Ideally there should be no offset.
  • this frequency is greater than 5MHz, then the local oscillator in the down-converter is not functioning correctly. In this connection, if the local oscillator is more than 12.5MHz out of specification, it is possible to lock to the wrong 25MHz marker.
  • Major mode change this happens any time a frequency related parameter is changed. It involves accurately setting up all the DACs for the selected frequency range(s), using calibration data and performing multiple locks and searches for markers (25MHz and 500MHz) .
  • a sweep covering the HET and YIG bands is validated as two individual sweeps occurring one after the other. If alternate sweep is also selected, it is possible to end up validating up to four individual sweeps.
  • steps 4.1.2 to 4.1.7 should always be carried out in the YIG band. This is because the Width DAC validation is done using 500MHz markers and to use an accurate centre frequency, 25MHz markers are needed that correspond exactly to the 500MHz markers. These only appear in the YIG band, as the HET band 25MHz markers can be offset from the 500MHz markers due to the different frequency sources.
  • a Major mode change is always carried out with the CW filter switched out.
  • the RF models can always access the next marker up, and on all other units, if the nearest marker would be the next one up, then that can be accessed.
  • band start frequency coincides with a marker, look at the marker at the start frequency and the next marker up.
  • band start frequency is less than the lowest marker frequency, look at the lowest marker and the next one up.
  • the Start DAC values are known for all the 500MHz (75MHz) markers. This allows the Start DAC to be moved approximately 50MHz (30MHz) below the 500MHz (75MHz) marker calibration position, and then sweep the Start DAC to approximately 50MHz (30MHz) above the marker building a profile of the 500MHz (75MHz) marker. From the marker profile we can determine the exact centre of the 500MHz (75MHz) marker. This can be done for r the two nearest 500MHz (75MHz) markers, and the calibration table of Start DAC marker positions for these two markers, can be updated.
  • the Ramp and Width DACs can be used by moving to the sweep stop frequency and locking to at least one 500MHz (or 75MHz) marker, to validate the Width DAC setting.
  • the stop frequency is not an integer multiple of the marker frequency in the RF models, it is always possible to access the next marker up, and on all other units, if the nearest marker would be the next one up, then that can be accessed. If the band stop frequency coincides a marker, then look at the marker at the stop frequency and the next marker up.
  • the Width DAC values for all the 500MHz (75MHz) markers can be calculated relative to the band start frequency. This allows the Width DAC to be moved to approximately 50MHz (30MHz) below the 500MHz (75MHz) marker calibration position, and then swept to approximately 50MHz (30MHz) above the marker, building a profile of the 500MHz (75MHz) marker.
  • (75MHz) marker can be determined. This can be the nearest one or two 500MHz (75MHz) markers.
  • the Width DAC value can be determined for the required stop frequency.
  • the width frequencies and DAC values required to get to the markers, and the Width DAC value required to move 500MHz (75MHz) are known so that appropriate fractions of 500MHz (75MHz) can be added or subtracted to reach the stop frequency.
  • the Width DAC value for the required stop frequency can still be determined since the Width frequency required to get to the marker is known so that the DAC value can be scaled up or down to achieve the stop frequency.
  • the linearity of the YIG can vary across its frequency range ie the DAC value to move 500MHz from 2GHz might not be the same as that to move 500MHz from 5GHz.
  • a multiband unit when changing from the YIG low band to the YIG high band, only lock at the start of the YIG high band for the first few sweeps after a major mode change. After locking, store the difference in Error DAC values for the YIG low band start lock and the YIG high band start lock. When not locking at the start of the high band, the Error DAC value required can be calculated by adding the difference value to the lock value just obtained for the YIG low band.
  • a major difference between slow and fast locking is the frequency range swept by the Error DAC. Slow locking sweeps over the complete range of the Error DAC, while fast locking only sweeps over approximately 16MHz.
  • the selected frequency will be close to that produced by a value of 800H on the Error DAC. This is because the YIG is positioned as accurately as possible at the selected frequency by the Start and Width DACs with no contribution from the Error DAC. It also means that the frequency can easily be corrected by +/- 12.5MHz without worrying about running out of range on the DAC.
  • the Start DAC is set up for a frequency of 25MHz, with the Error DAC set to mid-range.
  • Using an Error DAC centre value of 25MHz allows the Start frequency to be- locked, but still enables the Error DAC to be swept over two 25MHz markers to allow the local FM Error DAC scalar to be determined.
  • the Error DAC has a range of approximately 60MHz.
  • the closest marker will be at 25MHz and the second marker will be at 50MHz.
  • Step DAC forwards in large steps of approximately 210KHz. At each point, look for the presence of a 25MHz marker.
  • step back another two large steps if this is possible without going below the start point, to find the exact start point of the marker. Wait a short while for the YIG to settle. Step forwards through the sweep again but this time in small steps of approximately 25KHz looking for the marker.
  • step DAC forwards again in small steps.
  • step DAC forwards again in small steps.
  • step forwards through the sweep until the stop value is reached or a value is reached such that if another step is taken, it would exceed the stop value.
  • the Start DAC When a major mode change has been finished, the Start DAC with no addition from any other DAC approximates to the start frequency. With the Ramp DAC set to its ramp stop value, the Width DAC approximates to the stop frequency.
  • the start frequency is corrected by doing slow error locks following later by fast error locks.
  • the process should be performed at the end of a first sweep.
  • the correction X can be progressively applied across the sweep.
  • the Error DAC value is modified by X/(number of steps in the band), so in effect the Error DAC is swept over a very limited range as the Ramp DAC is swept.
  • Calibration of a YIG oscillator RF source may be rendered more simple if the DACs controlling the frequency determining currents to the Main and Fine coils of the YIG oscillator are preset so that the full scale sweep of the YIG oscillator is just greater than and thereby overshoots the extremes of the calibration range at both ends thereof.
  • the microprocessor generated signals for the DACs are arranged to cause the YIG to sweep in frequency from say 1.9GHz to 20.1GHz.
  • Starting at the lowest YIG position, and altering the DAC signals to produce an increasing frequency of oscillation means that the first frequency coincidence of the YIG output with and of the harmonically related coarse calibration 500MHz related markers will be with the fourth harmonic of the 500MHz fundamental of the marker comb (ie 2.00GHz).
  • the first harmonically related coarse calibration (500MHz related) marker to be "seen” as the YIG oscillator frequency is decreased will be the 40th harmonic (based on the 500MH comb fundamental) ie the 00GHz component of the comb.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention se rapporte au réglage de fréquence d'une source RF comportant un oscillateur à éléments de réglage de fréquence approximatif et fin permettant de générer des signaux RF pour tester la réponse RF de dispositifs en faisant passer la source de signaux RF par une bande de fréquences et en détectant et en analysant le signal transmis par le dispositif en cours d'essai. Un signal en peigne approximatif basé sur des harmoniques d'un premier signal NMHz, et un signal en peigne fin basé sur des harmoniques d'un second signal nMHz (N étant plus grand que n) sont générés et les éléments de réglage de fréquence approximatif et fin sont étalonnés. Les oscillateurs passent ensuite par la fréquence à laquelle un marqueur se rapporte et s'arrêtent juste après celle-ci, pour détecter la présence des fronts montants et descendants du marqueur, et les valeurs de signal de réglage fin correspondant aux fronts sont relevées, une valeur de signal de réglage de fréquence correspondant à la position médiane du marqueur est calculée à partir de la moyenne arithmétique des valeurs des fronts montants et descendants, et la valeur ainsi calculée est utilisée pour étalonner l'oscillateur par la suite. L'appareil pour appliquer le procédé est également décrit.
PCT/GB1992/001008 1991-06-06 1992-06-04 Generateur de signaux ameliore et appareil d'essai WO1992022129A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB9112175.6 1991-06-06
GB919112175A GB9112175D0 (en) 1991-06-06 1991-06-06 Improved signal generator and testing apparatus
GB9112177.2 1991-06-06
GB919112177A GB9112177D0 (en) 1991-06-06 1991-06-06 Improved testing apparatus

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WO1992022129A1 true WO1992022129A1 (fr) 1992-12-10

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3917511C1 (en) * 1989-05-30 1990-08-02 Rohde & Schwarz Gmbh & Co Kg, 8000 Muenchen, De Wobbulator frequency value determining device - uses interpolation counter to restart at each frequency marker and processor to determine wanted frequency
GB2236026A (en) * 1989-09-13 1991-03-20 Marconi Instruments Ltd Swept frequency signal generating circuit
EP0420082A2 (fr) * 1989-09-29 1991-04-03 Hewlett-Packard Company Source de signal de balayage synchronisée numériquement

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3917511C1 (en) * 1989-05-30 1990-08-02 Rohde & Schwarz Gmbh & Co Kg, 8000 Muenchen, De Wobbulator frequency value determining device - uses interpolation counter to restart at each frequency marker and processor to determine wanted frequency
GB2236026A (en) * 1989-09-13 1991-03-20 Marconi Instruments Ltd Swept frequency signal generating circuit
EP0420082A2 (fr) * 1989-09-29 1991-04-03 Hewlett-Packard Company Source de signal de balayage synchronisée numériquement

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC ENGINEERING. vol. 59, no. 723, March 1987, LONDON GB pages 103 - 111; PURCHON AND PEGG: 'The digital control-architecture of a microwave sweeper.' *

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