WO1992015086A1

WO1992015086A1 - Multi-tone real time sound synthesizer

Info

Publication number: WO1992015086A1
Application number: PCT/US1992/001206
Authority: WO
Inventors: John Griffin; John Minami
Original assignee: Everex Systems, Inc.
Priority date: 1991-02-15
Filing date: 1992-01-14
Publication date: 1992-09-03
Also published as: AU1429192A

Abstract

A real-time multi-tone sound synthesizer having improved operating characteristics. The synthesizer implements additive musical synthesis on a gate array (1001) which operates through inputs received from a host computer (1009) or other device. The gate array (1001) includes a plurality of oscillators (1102) which share resources such as memory (1014). The gate array (1001) may be arranged to operate in conjunction with a plurality of other gate arrays (1002) all under common control of a host computer (1009) wherein one gate array in the system operates as the 'master' gate array controlling multiplexing of synthesized outputs.

Description

MULTI-TONE REAL TIME SOUND SYNTHESIZER

1 BACKGROUND OF THE DISCLOSURE

2 1. Field of the Invention:

^ 3 This invention relates to computer controlled sound synthesizers useful for

' 4 - synthesiziiig, in real time, multiple musical tones each having a complex frequency

5 spectrum; more specifically, the invention relates to an additive-type digital synthesizer in

6 which each tone is generated by summing the digital representations of its constituent

7 frequency components. The primary purpose of the invention is the synthesis of musical

8 sounds. Therefore, the synthesizer will be described in terms of a music synthesizer,

9 however, aspects of the present invention may also be useful, inter alia, in a general 10 purpose signal synthesizer for other applications.

11 12

13 2. Description of Related Art

14 It is well known in the art of music synthesis that the realistic representation of

15 instrumental music requires the generation of more than a single frequency. For example,

16 the plucking of a string on a string instrument typically results in a combination of

17 harmonically related frequencies, that is the fundamental resonant frequency of the string

18 and even and odd multiples of the fundamental, mainly determined by the mass, length and

19 tension of the string and by the shape of the initial displacement caused by the plucking

20 action. In addition, the energy dissipated over time causes the vibration to decay in

21 amplitude until it is at rest This results in a harmonic acoustic signal that is amplitude

22 modulated in time. In fact, each harmonic component will generally have different rates of

23 decay so that the composite signal may not have a periodic decaying structure, but rather , 24 may have a time varying aperiodic decay envelope. Also, for the example chosen, the

25 effective length of the string may be varied by the use of finger pressure resulting in an

26 increase or decrease in the fundamental and harmonic frequencies producing a frequency modulation of all of the components. Finally, instruments based on resonant structures more complicated than the simple ideal string used in the above example may have characteristic resonances that are not quite harmonically relate Thus, realistic music synthesizers must include the capability of providing multi-frequency amplitude and frequency modulated sinusoids in proper proportions even when simulating the sound of a single instrumenL Over the past several decades many ingenious music researchers have contributed to the evolution of increasingly complex synthesizers aimed at achieving realistic performance. This evolution may be summarized as follows: 1 ) The simplest additive synthesizer consisted of a small number of fixed- frequency, fixed-amplitude oscillators in which the oscillator frequencies were exact integer multiples of a fundamental pitch. The output was only a poor copy of the actual instrument tone no matter how carefully the oscillator amplitudes were set to reflect the relative amplitudes of the individual harmonics. 2) The number of oscillators was increased This gave the tone more fullness, but it still would not be mistaken for the original. 3) Each oscillator was given its own frequency control. The frequencies were still fixed but were no longer required to be exact integer multiples of a fundamental. This improved the ability to simulate the tones of instruments such as the piano in which the higher frequencies are not exact multiples of the fundamental pitch. 4) An overall amplitude envelope was imposed on the synthesizer output to simulate the attack, decay, sustain and release stages of the actual tone. The improvement was noticeable, but the result was still only "good". 5) An overall frequency control was added to allow the frequency of all oscillators to be simultaneously varied. This improvement allowed for vibrato and pitch bend effects. 6) each oscillator was given its own individualized amplitude envelope. This step was prompted by computer analysis which clearly showed that the amplitude of each frequency component ("partial") varied independently with time. The resulting sound quality was considerably improved. At this point the complexity of the additive synthesis instrument had increased so much that a digital computer was necessary for real time control. In fact, most present day electronic music research is accomplished using computer simulations.

Specifically, the following facts have been established concerning the characteristics scillators necessary for full capability additive synthesis:

1) It should be possible to set the frequency of a given oscillator to a value that is completely independent of the frequency of any other oscillator. This allows for the synthesis of tones having non-harmonic components. 2) It should be possible to vary the frequency of a given oscillator, independently of the frequency of any other oscillator, during the production of a tone. The frequency variations experienced by a given oscillator can be both rapid (as in a vibrato) and broad (as in a glissando). 3) It should be possible to set the amplitude of a given oscillator to a value that is completely independent of the amplitude of any other oscillator. The amplitude variations required of a given oscillator are very often different in time and extent from the variations required of other oscillators. 4) It should be possible to independently vary the amplitude of each oscillator during the production of a tone. The amplitude variations required of a given oscillator can be very rapid (often several thousand db per second in the attack stage) and broad (often extending over a range of 60db or more). 5) The faithful reproduction of some complex acoustic instrument tones may require over 50 oscillators.

U.S. Patent No.4,201,105 entitled "Real Time Sound Synthesizer", Alles. issued May 6, 1980, describes the concept of synthesizing instrumental voices by means of piecewise linear approximation to both amplitude and frequency envelope shape by specifying the values of amplitude and frequency at the beginning and end of each segment. Alles describes a computer controller providing the synthesizer with the end point data as well as the linear rate of change, or increment, for creating the ramp between the end points. A further refinement includes means for exponentiating the ramp to better simulate exponential attacks and decays often found in instrumental music. A frequency and an amplitude ramp generator is provided in the synthesizer. Typically, the frequency ramp generator output, representing a phase angle increment, is successively added to the phase angle of a waveform to generate successive addresses for referencing a look-up table thereby generating a series of digital samples of a waveform with constant frequency. The amplitude linear segment is applied by a multiplier means to the waveform samples. This process is repeated for subsequent contiguous segments. Time-division multiplexed operation of the ramp generators permits economies in structure by using a single waveform look-up table and multiplier means. An accumulator means for combining and storing partial results is also provided A rudimentary frequency modulation scheme is provided by allowing previously stored synthesized data to be fed-back to modify the frequency ramp generator output. ■ Prior art synthesizers recognized the heavy burden that the amplitude control function may place on the system resources. Each frequency component sample has an amplitude function sample associated with it, each such sample pair being generated, typically, at 32 microsecond intervals. Further, a typical synthesizer may include 64 distinct frequency components being generated simultaneously. This implies that 64 multiplications must be performed each 32 microseconds or at a rate of two million 16 bit multiplications per second. One proposed solution was suggested by H.G. Alles in an article entitled "An Inexpensive Digital Sound Synthesizer" in the Computer Music Journal, Volume 3, Number 3, dated September, 1979 in which the following trigonometric identity, sin(Δ0 + 0) - sin 0 = 2 sin(Δ0 / 2) ^* cos(0 + (Δ0 / 2)) is used in conjunction with a read only memory to perform the amplitude scaling of the cosine term, on the right hand side, by 2 sin(Δ0 / 2) _t the amplitude term. Thus, changing Δ0 results in a change in amplitude of the cosine term. This technique has two major drawbacks: 1) the non-linear relationship between t&> and sin(Δ0 / 2) limits accurate operation to small values of *& unless arcsin operations are added. 2) large changes in amplitude may cause objectionable angle modulation (fm) of the cosine frequency term. It is, therefore, one object of the present invention to improve sound synthesizing systems. Another object is to provide an enhanced frequency modulation capability that allows previously synthesized or external signals to be used for the modulation of currently generated tones. A further object is to advantageously combine the exponential characteristic means with the multiply means, taking advantage of common resources. It is still a further object to permit efficient miniaturization for packaging by multiplexing the use of said common resources.

SUMMARY OF THE INVENTION A synthesizer especially well-suited for synthesizing multiple musical tones in real-time is described The synthesizersystem of the present invention preferably includes a host (or control) computer and a synthesizer circuit coupled in communication with the host computer through a host computer interface. The system further comprises audio output circuitry for providing synthesized output signals. In one inventive embodiment, multiple synthesizer circuits may be provided all coupled under control and in communication with the host computer. One of the synthesizer units is controlled, by the host computer, to be the master synthesizer and the remaining units are controlled to be slave units. The slave units are coupled to provide output signals to the master. The system further provides circuitry for summation of the output signals of the master and slave synthesizers prior to providing the summed output to the audio output circuitry. In the preferred embodiment the summation circuitry is preferably in the form of a serial bit adder coupled to receive data from both the master and slave synthesizers. However, in an alternative emrxxiiment, a parallel adder may be utilized. The present invention further teaches coupling of memories to each of the synthesizer units to allow receiving and storing of line segment information representative of components of a musical tone. The present invention further discloses use of line segment approximations for approximating waveform components of a musical tone including circuitry which advantageously allows loading of multiple line segments from a control processor into a memory. The multiple line segments may then be accessed by the synthesizer circuitry without further need for intervention from the control computer. The present invention further discloses a block load feature in which the preferred synthesizer circuitry includes addressing means for providing address information to the line segment memory. The control computer may supply a first line segment with a starting block address. Further line segments may be supplied from the control computer and addressing of the line segment memory may be accomplished under control of the synthesizer circuity addressing unit These and other objects of the present invention will be better understood with reference to the below detailed description of the preferred embodiment and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS A more complete understanding of the invention and its various features, objects, and advantages may be had by consideration of the following description, claims and attached drawing in which:

Figure 1(a) is a simple block diagram illustrating a prior art oscillator.

Figure 1 (b) is a waveform representation of a sample output of the oscillator of Figure 1(a).

Figure 1 (c) is a digitized representation of the waveform of Figure 1 (b) such as may result from the input of the waveform of Figure 1 (b) into a digital-to-analog converter.

Figure 2(a) is a block diagram illustrating a basic digital oscillator capable of varying its frequency without varying its sample rate.

Figure 2(b) is a waveform representation of an output of the oscillator of Figure 2(a).

Figure 3 is a block diagram illustrating a basic digital oscillator capable of amplitude control.

Figure 4 is a block diagram illustrating a circuit implementing a plurality of digital oscillators.

Figure 5 is a block diagram illustrating a circuit implementing a plurality of digital oscillators and including pipeline registers.

Figure 6(a) is an exemplary amplitude output of the circuit of Figure 5.

Figure-6(b) is an exemplary frequency output of the circuit of Figure 5.

Figure 7(a) is a line segment approximation of the exemplary amplitude output shown in Figure 6(a).

Figure 7(b) is a line segment approximation of the exemplary frequency output shown in Figure 6(b).

Figure 8(a) is a block diagram illustrating a circuit implementing a digital oscillator including use of frequency line segment data.

Figure 8(b) is a block diagram illustrating a circuit implementing a digital oscillator including use of amplitude line segment data.

Figure 9 is a block diagram illustrating a circuit implementing a digital oscillator including capability for FM synthesis.

Figure 10 is a system level block diagram illustrating two digital oscillator gate arrays in a sound synthesizer system as may be utilized by the present invention.

Figure 11 is a block diagram illustrating components of a gate array as may be utilized in the present invention. Figure 12 is a block diagram illustrating a new value generation unit as may be utilized by the present invention.

Figure 13(a) is a flow diagram illustrating a method for calculation of a value for a sub-sample as may be utilized by the present invention.

Figure 13(b) is a flow diagram illustrating a method for frequency and or amplitude calculation as may be utilized by the present invention.

Figure 13(c) is a flow diagram illustrating a method for calculating a sub-sample value as may be utilized by the present invention.

Figure 14 is a block diagram illustrating a synthesizer engine as may be utilized by the present invention.

Figure 15 is a block diagram illustrating a serial data generation unit of the present invention.

Figure 16 is a diagram illustrating time of certain signals as may be practiced by the present invention.

For ease of reference, it might be pointed out that reference numerals in all of the accompanying drawings typically are in the form "drawing number/" followed by two digits, xx; for example, reference numerals on Figure 1 may be numbered lxx; on Figurel4, reference numerals may be numbered 14xx. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention describes a synthesizer for synthesizing musical and other acoustic tones. In the following description numerous specific details are set forth, such as specific circuits, timing, etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods and structures have not been set forth in order not to unnecessarily obscure the present invention.

OVERVIEW OF DIGITAL OSCILLATORS The preferred embodiment of the present invention has implemented a plurality of digital oscillators to provide for "full capability" real-time additive synthesis (full capability additive synthesis may be defined as an additive synthesis process which is capable of reproducing tones of acoustic instruments with enough fidelity that a group of trained musicians will not be able to reliably tell the difference between recordings of actual and synthesized tones).

A basic digital oscillator Before describing the system of the preferred embodiment in greater detail, it will be useful to describe the functions of a basic digital oscillator and to describe certain features of the basic digital oscillator which has been developed for use with the system of the preferred embodiment Looking to Figure 1 (a), in its simplest form, a digital oscillator comprises a waveform memory 101 which may be addressed by the output of a counter 102. The waveform memory 101 is initially loaded with values, such as the sine function. As the binary counter 102 is incremented (at the sample clock rate 103), a series of increasing address values are presented to the waveform memory 102. In this case, the output 104 of the waveform memory 101 is as shown in Figure 1 ) where each address value (A through P) produces a corresponding sine value (sin[A] through sin[P]), points 104. These sine values may then be passed through any of a number of well known digital-to-analog (D-to-A) converters to obtain an audible waveform. The output of such a D-to-A converter is illustrated with reference to the waveform 105 of Figure 1(c). It is noted that the output of the D-to-A converter is the illustrated "stair step" function. This analog waveform 105 may be passed through a low pass filter which will remove (or smooth) the stair steps and produce a smooth sine wave. One might note that the above-described circuit is limited in that it is necessary to change the sample clock 103 rate in order to change the frequency of the output Changing the clock rate presents a number of obstacles including the possbility of exceeding the maximum access rate for the waveform memory 101 and expected difficulty in synchronizing and combining the output of the oscillator with the output of other oscillators which are running at different clock rates. One known solution to overcome these obstacles is to keep the sample clock 103 rate constant and to accomplish changing the frequency of the waveform by skipping over an appropriate number of samples between accesses. A basic digital oscillator which is capable of skipping a number of samples between accesses is illustrated with reference to Figure 2(a). This oscillator includes a waveform memory 101 as described with reference to Figure 1 (a). However, the circuit of Figure 1 (a) has been modified to replace the memory address register 102 with a memory address generator 201. The memory address generator 201 comprises a memory address increment register 202, a previous memory address register 203 and an adder 204. The outputs of the memory address increment register 202 and the previous memory address register 203 are coupled to the adder 204 to accomplish adding together the contents of these registers. The output of the adder 204 is coupled to provide for addressing the waveform memory 101. Further, the previous memory address register 203 is coupled to receive and latch the output of adder 204. Thus, in the next cycle, the current cycle's address and the increment are added to again address the waveform memory 101. It can be seen that the frequency of the waveform may be varied by changing the contents of the memory address increment register 202. Figure 2(b) illustrates a waveform 212 output from the circuity of Figure 2(a) wherein the value of the memory address increment register is 2. Of course, the digital waveform may be fed through a D-to-A converter and low pass filter to obtain a smoothed sine wave. It is useful at this point to introduce certain terminology. First, the memory address increment register 202 may also be referred to as a phase angle increment register or, as it controls the frequency of the output waveform, may also be referred to as the frequency register. Tie previous memory address register 203 is sometimes also referred to as the phase angle register. In a typical application, the frequency register 202 and the phase angle register 203 each have more bits of resolution than necessary for addressing the waveform memory 101. The most significant bits of the output of adder 204 are used for the memory address while the lower bits provide resolution for fine frequency control.

Amplitude control In addition to control of the frequency of the output of the basic digital oscillator, it is also useful to control the amplitude of the resulting waveform. Figure 3 illustrates the basic digital oscillator with the addition of an amplitude control stage 301 including an amplitude register 302 and multiplier 303. Each value read from the waveform memory 101 is multiplied by the value stored in the amplitude register 302 using multiplier 303. As one aspect of the present invention, it is taught to control the value in the amplitude register 302 under computer control such that the value stored in register 302 may be changed rapidly allowing production of amplitude variations required by full capability additive synthesis. In addition, it is taught to control the value in the frequency register 202, again under computer control, such that the value in register 202 may be changed rapidly allowing production of frequency variations required by full capability additive synthesis.

Implementation of multiple oscillators Heretofore has been described the basic circuitry for a single digital oscillator employing certain features of the present invention. However, it is useful in practical and commercial implementations to include a large number of oscillators in a system to increase the number of tones which may be played simultaneously. Figure 4 illustrates a circuit in which the oscillator of Figure 3 has had its control registers (frequency register 202, previous phase angle register 203 and amplitude register 302) effectively duplicated 64 times. These registers now take the form of frequency RAM (random access memory) 401, previous phase angle RAM 402 and amplitude RAM 403. Note that the waveform memory 101, phase angle adder 204 and amplitude multiplier 303 have not been duplicated in the preferred embodiment of the present invention. In the circuit of Figure 4 time division multiplexing is used to process one sample for each of 64 separate oscillators and to combine the outputs of the samples using sample accumulator 405, all in a single sample output time. It is pointed out that the requirement for adding together the phase angle and phase increment, access the waveform memory and multiply by the amplitude multiplier for each of 64 (or some other relatively large number, e.g., 128) oscillators is today only feasible when such circuitry is implemented in digital form. In fact, to gain adequate performance, it has been found to be necessary to implement pipeline registers between the stages of the oscillator. It will be understood that pipelining allows sample N to be processed through each stage while sample N+l follows only 1 stage behind It is then possible to have as many samples simultaneously in progress as there are stages. The time delay between oscillator samples is no more than the time delay between successive pipeline stages. In the preferred embodiment of the present invention it is desired to provide one accumulated output every 22.68 microseconds (achieving a 44.1 Khz sample rate). This is accomplished by ensuring the maximum delay between the output of any pipeline register and the input of the next pipeline register is less than 354 nanoseconds. Figure 5 illustrates a simplified block diagram showing pipeline registers between each stage of the oscillator of the present invention. Pipeline registers 501 and 502 are coupled between frequency RAM 401 and adder 204, and previous phase angle RAM 402 and adder 204, respectively. Pipeline register 503 is coupled between waveform memory 101 and multiplier 303; and pipeline register 504 is coupled between amplitude RAM 403 and multiplier 303. Finally, pipeline register 505 is coupled between multiplier 303 and adder 406. Each of pipeline registers 501-505 are controlled by common clock 506. Sample accumulator register 405 is also controlled by clock 506, and may be cleared by a . clear signal on clear line 507, typically once per sample output time.

Changing the oscillator's frequency and amplitude in real time As has been previously mentioned the frequency and amplitude of the above-described oscillator may be changed by changing the value of the frequency RAM 401 and amplitude RAM 403, respectively. In the above-described circuit, an external synthesizer control CPU may be used to update the frequency and amplitude RAMS, 401 and 403, in real time. However, updating these values on a frequent enough basis presents a problem for typical commercial processors which are available today. It is assumed that the CPU would be required to change the frequency and amplitude value for each of the oscillators (e.g., 64) at least once every 5 milliseconds and, likely, even more often (perhaps every millisecond or less) as the amplitude of a tone may increase extremely rapidly during the attack stage of the tone. Further, dedicating a CPU to control of the oscillators may very well prove to be prohibitively expensive in commercial systems.

Use of line segment approximations Therefore, the present invention discloses use of line segment approximations of the amplitude and frequency envelopes of the waveform to be generated. The line segment approximations may be specified with much less data than is required for the original curve. This may be conceptually understood with reference to Figures 6(a) and 7(a) which illustrate the amplitude envelope 601 of a waveform and its line segment approximation 701 and to Figures 6(b) and 7(b) which illustate the frequency envelope 602 of a waveform and its line segment approximation 702. Each line segment may be represented as two quantities: (1 ) an increment value (negative or positive); and (2) a count of how many times the increment is to be used. Alternatively, each line segment may be represented as (1) an increment value and (2) a target value which is reached by successively adding the increment value to the current value. In fact, in the prefeired embodiment of the present invention, line segment descriptor information is represented by an increment ( or slope) value and a target (or destination) value. The increment and target values are preferably given as logarithms to the base 2. The use of logarithmic values more closely approximates the exponential nature of the frequency and amplitude changes in musical tones. Further, logarithms allow a wider dynamic range of values to be represented by a fixed length integer number. Also, multiplication of a sine value by its amplitude may be, and in fact preferably is, accomplished by adding logarithms and performing an antilog operation using a look-up table stored in memory. In one embodiment the look-up table is stored in a ROM, as will be seen with reference to Figure 10. In an alternative embodiment, the look-up table is stored in a RAM. Of course, design tradeoffs such as cost, speed and availability will influence the decision to implement the look-up table in either a ROM or a RAM in any particular embodiment It may be noted that use of a RAM allows for flexibility in the contents of the look-up table and, therefore, provides certain advantages. Thus, it is desired to develop a system in which the external control CPU provides line segment information and the oscillator IC is capable of generating frequency and amplitude values from such line segment descriptions. In this way, a frequency or amplitude curve starts at a known value and increment (or decrement in the case of a negative increment) and proceeds to a known target which is also the starting point of the next line segment At that point, the next line segment descriptor is used until its target is reached. This sequence is repeated until the last line segment for the tone is used The oscillator is then free to accept assignment of another tone. Figure 8(a) is a block diagram illustrating a logical view of the frequency control section of a circuit, as provided by the present invention. The frequency line segment pointer 801 provides addressing information for pointing to a value in the current frequency memory, block 802; addressing information for pointing to a value in the current frequency increment memory, block 803; and addressing information for pointing to a value in the current frequency target memory, block 804. The frequency line segment pointer 801 of the prefeired embodiment will be described in greater detail below in connection with RAM address and control line generator 1106 and in connection with the description of the line segment data memories and Table 2. The current frequency value is read from the memory 802 and loaded into the current frequency register 812. Similarly, the current frequency increment is read from the memory 803, and loaded into the current frequency increment register 813. Finally, the current frequency target is read from the memory 804 and loaded into the current frequency target register, block 814. Comparator 820 is coupled to receive the current frequency value from current frequency register 812 and is further coupled to receive the current frequency target value from current frequency target register 814. Comparator 820 is provided to compare the current frequency value with the current target value and to determine whether the frequency increment must be added to or subtracted from the current frequency value in order to reach the target value. In other words, if the comparator 820 determines the current frequency value is less than the target value, the current increment is to be added to the current value. If the comparator 820 determines the current frequency value is greater than the target value, the current frequency increment is to be subtracted from the current value in order to approach the target value. Comparator 820 is coupled to control adder/subtractor 821 based on the result of the above-discussed comparison. Adder/subtractor 821 is coupled to receive as its two inputs the value in the current frequency register 812 and the value in the current frequency increment register 813. Under the control of comparator 820, the adder/subtractor 821 either adds the input values together or subtracts the value of the increment from the current value. In either event the output of adder/subtractor 821 is coupled as a first input to comparator 822. Comparator 822 is further coupled to receive as a second input the value of the current frequency target stored in register 814. Comparator 822 compares the new frequency value output from adder/subtractor 821 with the target value. The output of comparator 822 is coupled, through write-back control circuitry 832, to control multiplexor 811. Multiplexor 811 is coupled to select one of three inputs: (1 ) the value of the current frequency register 812; (2) the value of the current frequency target register 814; or the new frequency value output from adder/subtractor 821. The condition under which the multiplexor 811 is controlled to receive the current frequency value will be discussed below in greater detail in connection with the line segment update interval control circuitry 831. The multiplexor 811 is controlled to receive the current frequency target in the event the comparator 822 determines the new frequency value has exceeded the target (or in the case of subtracting the increment from the current value, the new frequency value is less than the target). Finally, the multiplexor 811 is controlled to receive the new current frequency value in the event that the none of the above-discussed conditions are met (i.e, the new value has not yet reached the target and the line segment increment control circuitry has not controlled multiplexor 811 to receive the current frequency value.) As stated above, comparator 822 is coupled through write back control circuit 832 to multiplexor 811. In addition, write back control circuit 832 is coupled to receive control information from line segment update interval control circuiuy 831. Circuit 832 always controls multiplexor 811 to provide the current frequency target as an output when comparator 822 indicates the new value has reached or exceeded the desired target In the event the new value has reached or exceeded the target, the write back control circuit 832 is further coupled to control line segment pointer update control circuit 841 so as to cause the line segment pointers to be updated to point to the next line segment Otherwise, in the event the new value has not reached the target, control circuitry 831 is utilized to allow finer control on the updating of the current frequency value. This circuitry is illustrated in greater detail with reference to Figure 12 which illustrates line segment update interval control circuit 1205 and new value select logic 1206. As will be understood with reference to the discussions of Figure 12, write back control circuit 832 is coupled to control multiplexor 811 to either accept the current frequency or the new frequency or the frequency target as a new current frequency value to be stored in current frequency RAM 802. The write back control circuit is further coupled to appropriately update the line segment pointer update control circuit 841 whenever writeback control 832 selects the current target value for loading into RAM 802. It should be noted that the output of multiplexor 811, in addition to being provided to be loaded into RAM 802, is provided as an output from the frequency control section of the circuit as an input to the synthesizer unit 1102. In a similar manner, the amplitude control section of the synthesizer (illustrated in block diagram form with reference to Figure 8(b)), is loaded with amplitude line segment data. Figure 8(b) corresponds to Figure 8(a), with the circuitry of Figure 8(a) providing for manipulation of frequency data and the circuitry of Figure 8(b) providing for manipdation of amplitude data wherein pointer 801 corresponds in function to pointer 851; RAM locations 802-804 correspond in function to RAM locations 852-854; registers 812-814 correspond in function to registers 862-864; and comparator 820, adder/subtractor 821, comparator 822, control 831, control 832, control 841 and multiplexor 811 correspond in function to comparator 870, adder/subtractor 871 , comparator 872, control 881, control 882, control 891 and multiplexor 861. It should be noted and it will be explained in greater detail below, that in certain cases corresponding circuitry of Figures 8(a) and Figure 8(b), in the implementation of the preferred embodiment, in fact utilize the same physical circuits on a time shared basis. This advantegously leads to savings in required circuitry and reduced system cost

Use ofFM Synthesis in the circuit of the present invention Prior art musical synthesizers have employed frequency modulation (FM) synthesis to obtain musically interesting sounds without the complexity and expense of full capability, real-time additive synthesis. Sounds produced through FM synthesis are interesting in their own right and it is thought that many musicians would not wish to discard such sounds because of the advent of inexpensive, capable additive synthesizers made available through the teachings of the present invention. Therefore, it is desired to provide FM synthesis capability with the additive synthesis provided by the circuitry of the present invention. Figure 9 illustrates, in block diagram form, a circuit adding FM synthesis capability to the additive synthesis circuit of the present invention. As can be seen, a portion of the amplitude modulated output of the waveform memory 101 is saved in a local FM RAM 901 so that it will be available to be fed back on line 908 and added to the result of adder 204 using adder 906. An FM RAM pointer RAM 902 is coupled to control accesses to FM RAM 901 to allow selection of any of the saved waveform values as input to any oscillator.

OVERVIEW OF CERTAIN OBJECTS OF THE PRESENT INVENTION The basic digital oscillator of the present invention can now be understood and appreciated, as described with reference to Figures 1-9. Before continuing with a more detailed description of the preferred embodiment of the present invention, it is useful to pause and discuss certain objects and features of the circuit of the present invention in an overview form. As a first object of the present invention, it is desired to develop a synthesizer which may be developed, manufactured and commercialized economically while achieving adequate and even superior performance. In acheiving this objective it has been determined that it is useful to implement many functions of such a synthesizer in gate arrays or similar technology. In fact, in the preferred embodiment of the present invention, a single gate array has now been implemented which supports 64 independent oscillators and which can be combined in a single system with up to 7 other gate arrays to support a total of 512 oscillators, which supports multiple data formats, and which supports stereo left and right outputs, among other capabilities. It will be seen that the described gate arrays may be arranged in a single system which supports up to a total of 8 gate arrays wherein a first of such gate arrays acts as a master and sums the outputs of itself and up to 7 slave gate arrays. This allows for an increased number of tones to be played simultaneously from the system. The summing function is preferably performed in a bit-serial manner. However, it is recognized that other summing techniques could be utilized, such as summation in a parallel mode. The eight inputs to the summing circuitry are summed as two groups of four inputs which allows for providing stereo outputs. In addition, AES/EBU serial stereo output format is provided by the master gate array. The master gate array also provides outputs which are compatible with the inputs of common serial input D-to-A converters. For example, one such output provides right channel data followed by left channel data. Another provides two copies of the right channel data, the purpose of which is to provide simultaneous data samples to separate digital-to-analog converters (DACs). An on-chip timer provides a continuous stream of timer interrupts to the controlling computer. Advantageous to carrying out the large number of calculations required by the system of the present invention, the preferred embodiment carries out the "multiplication" (using means 303) of the sine wave value read from the waveform memory 101 by the amplitude value from amplitude RAM 403 by adding the base 2 logarithms of both quantities and then finding the anti-log of the sum through a table look-up and shifting procedure. This technique leads to significant performance advantages over the use of a standard multiplication. Further, as has been seen with reference to the earlier discussed figures, the amplitude and frequency control algorithms use a common data path which results in significant circuitry savings. An important aspect of the present invention is provision to allow a control computer (CPU) to provide line segment descriptors to the osciDator (rather than requiring the control computer to provide frequency and amplitude values). The described circuitry, preferably implemented as a gate array, is then capable of accepting, storing and processing multiple line segment descriptors and using these descriptors in sequence without further direction from the control computer. The described technique and circuitry requires a greatly reduced number of interventions from the control computer as compared to techniques which require the control computer to present frequency and amplitude values directly to the oscillator. A gate array built in accordance with the teachings of the present invention is capable of accepting and storing separate line segment descriptors for each of its plurality of oscillators (64 oscillators exist per gate array in the preferred embodiment; however, it is obvious to one of ordinary skill in the art that a greater or lesser number of oscillators may exist in alternate embodiments). The gate array is then capable of calculating frequency and amplitude values for each of its plurality of oscillators from the stored line segment information. In addition, the gate array will add independent offset values to each computed frequency and amplitude value for the purpose of frequency transposition and volume control, respectively. In the prefeired embodiment, line segment descriptors comprise an increment value and a target value. The described circuitry is capable of determining whether a line segment increment value is to be added to or subtracted from the current value based on the relationship of the target value to the current value. The preferred embodiment utilizes a plurality of bits for its control values (frequency and amplitude) and further stores a plurality of bits in the previous phase angle RAM 402 for each entry. The plurality of bits used by the preferred embodiment is greater than the number of bits required to access the waveform memory 101. The waveform memory is then addressed with the high order bits of the sum resulting from the addition of frequency control value and the previous phase angle. The entire result is stored back into the previous phase angle RAM 402. In this way, the lower order bits provide resolution for fine frequency control. In the preferred embodiment, 20 bit values are used to represent phase angles and 16 bit values are used for most other control values. As one option in the preferred embodiment, the control computer may direct the gate arrays to use either low or high capacity look-up table memories (as discussed previously, these may be either ROMs or RAMs) for table lookup operations. This option allows for trading of accuracy for cost in selecting memories for use in the present invention. The present invention provides for a system in which a control computer provides frequency and amplitude line segment descriptor information and the oscillator control circuitry stores that information for later reference. Frequency and amplitude control information is calculated from the provided descriptor information by the oscillator circuitry. In this system, the control computer is not required to have direct access to the control memories. Therefore, another advantageous feature of the present invention is provided by the fact that all accesses to the control memory are through the oscillator circuitry (provided in the gate array). This feature allows use of relatively inexpensive and highly available single ported memories. The present invention allows the control computer to write line segment descriptor data to the oscillator circuitry while tones are being produced by the oscillator through the use of multiple buffering. In addition, the control computer may communicate with the oscillator circuitry to read the current state of any control and line segment values while tones are being produced As another performance feature of the present invention, the control computer may write line segment descriptor information either singly or in burst mode. During burst mode, the gate array automatically updates memory address pointers used in storing the received data. The circuitry of the oscillator (again, embodied in a gate array) provides for other valuable features. For example, the circuitry automatically "clips" the digital value of a sound sample when the value exceeds a maximum or underflows a minimum value. The circuitry then holds the sample at the maximum or minimum until the signal comes back into the proper range. Further, individual oscillators may be enabled or disabled at any time allowing the control computer to load new parameters without concern over whether some of the parameters will be used before all are loaded. The line segment pointers for each oscillator may be set to any arbitrary value by the control computer allowing such features as freeze and hold functions. Still further, the gate array may be commanded by the control computer to use amplitude and or frequency line segment data of any given oscillator to control other oscillators. This is particularly useful where a number of partials have the same envelope shape. To accomplish fast start-up of these partials, a first oscillator may be loaded with line segment data and all oscillators sharing the same envelope shape may be directed to use the line segment data of the first oscillator. Finally, the sum of the current values for any arbitrary set of oscillators may be used as an FM source for other oscillators. Finally, the preferred embodiment of the present invention further provides for timesharing on pins of the gate array through constructing certain output signals one clock cycle at a time by placing the instantaneous value for such signals onto output lines during clock cycles in which the lines are not used and strobing the values into an external register before the lines are again needed for other uses.

SYSTEM OVERVIEW As has been discussed the prefeired embodiment of the present invention is embodied in a musical synthesizer which produces digital music waveforms by creating and adding together individual sinusoidal components of each musical tone, a technique known as additive music synthesis. Previous techniques to offer full capability, real-time digital additive synthesis have resulted in complex and expensive, rack mounted equipment As will be seen, the present invention utilizes gate array technology and allows interface with commonly available computer systems and the like. Thus, reduced system size arid cost is realized along with increased dependability. Initially, the system of the prefeιτed embodiment will be described with reference to Figure 10 which is a system level block diagram illustrating a first gate array 1001 which is configured to operate in "master mode" and a second gate array 1002 which is configured to operate in "slave mode". The circuitry and method for causing a particular gate array to operate in either master or slave mode will be described in greater detail below; in addition, further detail will be provided on the relative capability of a gate array operating in each of these modes. However, for purposes of a system overview, it is sufficient to state that the system of the preferred embodiment may comprise from 1 to 8 gate arrays which allows an increased number of tones that may be played simultaneously. (Although only one slave gate array 1002 is illustrated, it can be seen that other gate arrays may be coupled in the described circuit in a similar manner to gate array 1002 on line 1006.) If a single gate array is utilized in a particular embodiment, that gate array operates in master mode. Otherwise, one gate array in the particular embodiment operates in master mode and the remaining gate arrays (up to 7 gate arrays) operate in slave mode. It should be noted that each of the gate arrays utilized in any particular embodiment of the present invention are clocked from a common clock source, clock 1007. Clock 1007 clocks at 33.869 Mhz to produce samples at 44.1 Khz. This sample rate is the sample rate of compact disk players and is currently widely recognized as a sample rate capable of representing music with high fidelity. The master gate array 1001 is coupled to receive serial data input from the slave gate arrays (e.g., slave gate array 1002) on time shared memory data lines 1058 and to sum the input in a bit-serial manner. (It should be noted that in an alternate embodiment the summing could take place in a parallel mode.) The master gate array 1001 then provides an output to audio output circuity 1013. The master gate array offers several formats for outputting samples. Instantaneous values of the format control signals are presented in parallel to the input of latch 1021 and a strobe signal is provided on line 1025 to latch the data into latch 1021. In this way, the master gate array may construct output signals one clock cycle at a time and place the instantaneous value of the output signal on lines 1058. The values may then be strobed into latch 1021. Each sample may be output in one of several formats. A first format is a serial format recommended by the Audio Engineering Society for stereo audio data and is output on line 1024., The second format is a serial format compatible with serial input D-to-A converters offered by Sony Corporation and others. In the second format, serial data is presented to serial D-to-A converter 1022. Serial D-to-A converter 1022 is coupled through sample and hold register 1026 (which is coupled under common control with latch 1021 to strobe line 1025) to low pass filter 1023 to provide output on line 1027. To examine the clocking signals associated with audio output circuity 1013 in greater detail it may now be useful to turn to Figure 16 which illustrates such signals. As has been discussed serial data bits are multiplexed out on data lines 1058 to latch 1021. Figure 16 illustrates clocking signals showing a control signal 1601 (corresponds with signals on line 1025) being used to clock the data into register 1021 and thereby reconstruct the serial bit data stream at the output of register 1021. The control signal 1601 is periodic, having a period corresponding to 3 RAM state intervals. Three data lines, 1602-1604, are shown illustrative of typical data values on lines 1058 corresponding to the following output data lines: (1) channel 1 serial data SDl 1605, (2) control signal BCLK 1606, and (3) AES standard serial format data 1606. These three signalsl602-1604 are representative of the signal formats used at output The register 1021 clocks in the data on its input lines 1058 at the positive going transition of the control signal 1601, thereby selecting (or demultiplexing) data present during the positive going transitions. Thus, the master gate array is controlled to ouφut channel 1 serial data SDl on lines 1058 at times to allow signal 1602 to be demultiplexed (on positive going transistions of control signal 1601) to yield the binary signal SDl 1605. During other periods (i.e., periods except for the periods of selection for demultiplexing, e.g., at positive going transitions of control signal 1601), other data such as data being communicated between the master gate array and RAM may be present on lines 1058. As can be appreciated, in this manner serial data is built up and stored in latch 1021 during each of a plurality of cycles of signal 1601. Figure 16 illustrates 5 full cycles (each cycle ending on a positive going edge of signal 1601) although, in the prefeired embodiment, a total of 18 cycles (including two cycles unused for construction of serial 1 SDl data but used for construction of AES data) are required to output one complete audio cycle. Similarly, signals BCLK 1606 and AES 1607 are constructed where BCLK is a periodic "square" wave with half the rate of control signal 1601 and a positive going transition occurring at the mid-point of serial bits of signal SDl 1605. Output signal AES 1607, formatted as a serial biphase mark coded signal, has a transition at the end of each bit interval and an additional transition occurring during the positive going transition of BCLK if the bit is a one. In this manner, the same output pins of master synthesizer gate array 1001 may be beneficially used both for communicating with the RAM and for outputting audio data and control signals to audio output circuity 1013, or any other auxiliary output device, during periods when data is not being communicated between RAM and the master gate array, thereby economizing on the number of pins required for the synthesizer chip. It should be noted that each of the gate arrays utilized in any particular embodiment is preferably provided with dedicated random access memory (RAM) such as the banks of static RAM (SRAM) 1014 illustrated coupled with master gate array 1001. Each gate array is further preferably provided with dedicated look-up table memory such as the banks 1015 illustrated coupled with master gate array 1001. (Although only SRAM 1014 and ROM 1015 are illustrated, both of which are dedicated to master gate array 1001, it will be appreciated that the remaining gate arrays in any particular emobiment have RAM and ROM coupled in a similar manner.) RAM 1014 is coupled to store data equivilent to the data stored in frequency RAM 401, previous phase angle RAM 402, and amplitude RAM 403, RAMs 802-804 and RAMs 852-854. RAM 1014 and its contents will be described in greater detail below. Look-up table memory 1015 is used for storage of the waveform memory 101 and for storage of certain anti-LOG data utilized by the prefeired embodiment of the present invention. Waveform information is preferably stored as the logarithm base 2 of the waveform values (e.g., log2(sin)). Look-up memory 1015 will be discussed in greater detail below. Interface to a control or host computer is provided through host computer interface 1009. Host processor communications are accomplished via a bidirectional data bus 1031 and various control lines 1034 and address lines 1033. Control lines 1034 comprise interrupt lines allowing the synthesizer gate arrays (e.g., gate array 1001) to assert an interrupt to the host computer. In addition, circuitry is provided on the synthesizer gate arrays to allow the host computer to communicate command and data information to each gate array (e.g., 1001, 1002). As will be discussed in greater detail below with reference to Figure 11, each gate array comprises a CPU interface 1108 for receiving such information. The CPU interface 1108 comprises sufficient buffer memory to allow for typical communications between the host computer and the gate array. For example the host computer may wish to communicate a command to determine the current state of a line segment value or the host may communicate additional line segment information to the gate array. ^' These communications may be carried out by the gate array accepting the data into available buffer space and processing the command and/or storing data in RAMs 1014 during available clock cycles. Importantly, although the host computer is free to communicate commands and data at anytime, the gate array's processing of existing data and outputting of synthesized tones is not interrupted or delayed by this communication. Rather, as stated immediately above, the gate array processes information received from the host computer as time slices are available. In the event buffers in the CPU interface buffer are full, the gate array communicates to the host computer that it is momentarily unavailable to receive additional information by activating XBUSY line 1041.

OVERVIEW FLOW DIAGRAM OF A METHOD OF THE PRESENT INVENTION Figure 13(a) illustrates an overall flow diagram of a method of the present invention for accumulating and output of synthesized tones and is provided here to provide an overview description of a method of the present invention. Initially, the log base 2 of a frequency value (i.e., phase angle increment) is calculated block 1301, using the new value generation unit described below. The frequency value is obtained through an anit-log table look-up process, block 1302, and the anti-log value is added to the previous phase angle value, block 1303. This sum is used as an address to look-up a waveform value in a waveform memory, block 1304. This function is carried out by synthesizer unit 1102, the circuitry of which will be described in greater detail below. After calculation of the frequency value and lookup of the waveform value, blocks 1301-1304, the new value generation circuitry is utilized for calculation of an amplitude value, block 1305. The amplitude value calculation follows the frequency value calculation by approximately 150 nanoseconds and is likewise supplied to the synthesizer unit 1102. After both the waveform and amplitude values are received by the synthesizer unit, the values are effectively multiplied together, block 1306. (It will be discussed in greater detail that these values are preferably represented as the logarithm base 2 of the actual values and are effectively multiplied by adding the logarithmic values and looking up the anti-LOG of the sum in a look-up table.) The result of the "multiplication" is then added to the value in a sample accumulator, also preferably included in the synthesizer unit 1102, and the result is added back into the sample accumulator, block 1307. When 64 sub-samples have been added in this manner, their sum is strobed into a holding latch (in serial data generator 1104) in preparation for output from the gate array to a digital-to-analog converter, block 1308. The sample accumulator is then cleared in preparation for the next 64 sub-samples. Referring now to Figure 13(b), the calculation of the base 2 logarithm of the frequency and amplitude values (blocks 1301and 1305 of Figure 13(a)) is described in greater detail. It is worth stating that as one aspect of the present invention, an implementation is described in which the same circuitry is utilized to calculate both frequency values and amplitude values. This results in a considerable reduction of circuitry and thus, a considerable savings in cost The particular circuitry will be described in greater detail below. However, in the following description, the calculation of these values will be discussed genetically with the understanding that this process is utilized in the preferred embodiment for calculation of both frequency and amplitude values. First the current value (i.e., current frequency or amplitude), increment value (again, frequency or amplitude), target value (frequency or amplitude), line segment interval control value, and offset value are read from memory, block 1321, and applied to the new value generation unit 1101. Each of these values will be defined in greater detail below. Before calculating the frequency or amplitude value, a check is performed to determine if the line segment should be updated during this cycle, block 1322. This check is performed based on a value termed the "line segment update interval" or "line segment interval control" which will be discussed in greater detail below. If a new frequency or amplitude value is not to be calculated during this interval, the current value is written back to memory, block 1331; otherwise, the value is calculated by performing the steps which will be discussed in further detail below. The new value generation unit acts to compare the current value to the target value to determine if the current value must go up or down to reach the target, block 1323. The increment is then either added, block 1326, or subtracted, block 1325, from the current value and the result is compared to the target value, block 1327. If the target has not been reached, the new value is written to the current value, block 1328, and is supplied to synthesizer unit 1102 as will be described. In the event the target value has been reached, the target value is written as the new current value, block 1329, and the target value is also supplied to the synthesizer unit 1102. Line segment pointers are also updated to point to the next line segment in memory, block 1330. An offset value may optionally be added to the result, block 1332. ADDΓΠVE SYNTHESIZER (GATE ARRAYS OVERVIEW The synthesizer of the present invention may be understood in greater detail with reference to Figure 11 which illustrates the preferred gate array in block diagram form. The timing generator 1103 accepts a master clock signal, operating at a 33.869 MHz rate, as its primary input from which it generates the necessary control signals for controlling the new value generator 1101, synthesizer unit 1102, serial data generator 1104, look-up table memory address generator 1105, RAM address and control generator 1106, and timer 1107 which provides timing information to the CPU interface 1108. This timer 1107 preferably provides timer interrupts every 46.44 milliseconds by causing the associated pin of the gate array to go to a logic high. The interrupt is cleared by a low to high transistion of a timer bit in the command register of the gate array. The ramp new value generator 1101 accepts the following input values: 12-bit frequency/amplitude slope increments, 16-bit current frequency/amplitude values, 16-bit frequency/amplitude targets and 4-bit frequency/amplitude line segment update control. The unit has two 16-bit output signals: new amplitude value and new frequency value; both signals are available to RAM (not shown) for temporary storage. The synthesizer unit 1102 incorporates the exponentiation, logarithmic conversion and accumulator functions thus requiring as inputs from RAM previously stored values for the phase angle (and optionally, an FM value) and from look-up table memory, values for log-sine, and antilog. It produces as its output: 20-bit new phase angle values and 16-bit FM values to RAM and values to the serial data generator 1104. The serial data generator 1104 performs the final synthesizer accumulation and produces as output: data from the accumulator in synthesizer unit 1102, two channel serial data, and Audio Engineering Society (AES) standard formatted serial data. The CPU interface 1108 controls the flow of data, in and out, on the CPU data bus, provides the necessary address pointers and control signals for the RAM address and control generator 1106 and the auto address generator 1109 associated with the RAM address and control generator 1106, and provides a software reset to the reset generator 1112. The RAM address and control generator 1106 provides addressing infoimation to the memory 1014. Utilizing on-board address and control generation, the system of the preferred embodiment can provide for writing data to memory in a burst mode during which the control computer first supplies beginning address information and may then transmit an entire block of data for storage in memory 1014. The auto-address generator 1109 provides for addressing and control of the memory 1014 during burst mode write transactions. Importantly, it is now understood that the circuit of the preferred embodiment provides for addressing of memory 1014 through an address generator on board the gate array — thus, addressing of the memory 1014 is external to the control computer supplying the data to be stored in the memory 1014. This offers a number of advantages including allowing use of relatively low-cost single ported memory integrated circuits for memory 1014 and relieving the control computer from responsibility and overhead for addressing the memory 1014. In the prefeired embodiment, the control computer is coupled through host computer interface 1009 to the gate array (e.g., gate array 1001) to provide line segment and pointer information to CPU interface 1108. The RAM address circuitry 1106 provides for addressing the memory 1014 as data is fed from the control computer. It should also be noted that the RAM address generator 1106 also controls reading of memory 1014 to allow line segment information to be input to new value generator 1101. RAM address generator 1106 may be controlled to allow inputs to be fed to new value generator 1101 or synthesizer unit 1102 while simultaneously writing a new line segment information to memory 1014. In this way, amplitude and frequency line segment data can be communicated between the control computer and memory 1014 while tones are being produced by the disclosed circuit

GENERATION OF FREQUENCY AND AMPLITUDE VALUES (The new value generation uniri Figure 12 illustrates the new value generator of the preferred embodiment in greater detail. It is worth again stating that the new value generator is utilized to generate new frequency and amplitude values based on the current value (e.g., current frequency value or current amplitude value, respectively), slope value (frequency or amplitude, respectively), and target value (again, frequency or amplitude, respectively). The output is, in the prefeired embodiment, the logarithm base 2 of the new value. The new value generator preferably includes as inputs the following data: current slope (frequency or amplitude) latch 1201 which stores the absolute magnitude of the slope increment to be used in current calculations; current frequency value latch 1202 which stores the current frequency ramp value; current amplitude value latch 1203 which stores the current amplitude ramp value; current target (frequency or amplitude) latch 1204 which stores the current target value for the new frequency or amplitude ramp to be generated; and line segment update control circuit 1205 which will be described in greater detail below. It is worth noting that, in the preferred embodiment, separate latches 1202 and 1203 are utilized for input of frequency and amplitude values. It is understood that during a first cycle of the new value generation unit, the described circuit uses frequency data and during a second cycle the described circuit uses amplitude data. Therefore, in alternative emrκκliments, a single latch could be utilized. However, due to the particular memoiy structure of the preferred embodiment it has been determined that efficiencies are gained by including a separate latch 1203 along with multiplexors 1207 and 1208 to allow selection of the output of latch 1202 during the first cycle and selection of the output of latch 1203 during the second cycle. The particular memoiy structure is described in greater detail below with reference to Table 2. As can be seen, both the current frequency and current amplitude data are stored at the same address location, in separate banks, in memory 1014. Thus, both frequency and amplitude data can be read during a single memory cycle. Latch 1203 allows latching the amplitude data until it is needed in the subsequent cycle of new value generation unit 1101. line segment update interval control register 1205 stores data for controlling whether or not the current frequency or current amplitude value is to be repeated for the purpose of generating ramps with finer effective slope or increment value then would be possible for the fixed number of bits, 12 bits in this case, assigned to the slope increment function. In other words, by repeating ramp values at selected intervals, the effective slope is decreased fractionally. "Hie current frequency or amplitude 16-bit value (whichever is appropriate at a particular time) is selected by selector 1208 and is stored in latch 1209. The output of latch 1209 is made available to the adder 1210 through selector 1211. When the magnitude comparator 1216 indicates that the current target is greater than or equal to the current value, then the current slope (in latch 1201) is applied directly to adder 1210 via input 1 of selector 1212. If the target is less than the current value then the negative of the slope is applied via input 2 of the selector 1212. The 12-bit positive slope value stored in latch 1201 has its sign extended by forcing the four most significant bits to low (GND) and extending the field to 16 bits. A third input to adder 1210 provides the necessary carry-in for properly negating the two's complement coded signal whenever the ouφut of inverter 1213 is selected by selector 1212. This carry-in signal from logic network 1214 also supplies selector 1212 control signals. Thus, logic network 1214 in conjunction with selector 1212, inverter 1213 and adder 1210 allows the current slope value in latch 1201 to be either added to or subtracted from the value presented at the first input to adder 1210. The input to logic network 1214 is provided via pipeline register 1215. The input to register 1215 is die A<B output of the 16 bit magnitude comparator 1216 which compares the current amplitude or frequency value presented to input B by selector 1207 with the amplitude or frequency target presented to input A by current target latch 1204. When the comparison is made between a current frequency value presented on input 0 or a current amplitude value presented on input 1 of selector 1207, a determination is made by logic network 1214 to add or subtract the current slope value in latch 1201 to/from the current value stored in latch 1209 and selected by selector 1211. In this manner, a rising or falling ramp may be generated based upon current ramp, slope increment and target values. Upon completion of the add cycle in adder 1210, the new current frequency or amplitude value is applied to input B of comparator 1216 and is compared with the current target value at input A. The new value select logic network 1206 in conjunction with the line segment update interval control logic 1205 determines if the current amplitude or frequency value is to be updated during this cycle. If not, then the previous current value at input 1 of selector 1218 is chosen as the new value. Otherwise, new value select logic network 1206, having stored the comparator 1216 results, prior to the last add/subtract operation, determines if the target value is met or exceeded if not, network 1206, through mux selector latch 1217 selects input 0 of selector 1218, which is connected to die output of adder 1210; otherwise, the mux control logic selects the contents of current target latch 1204 connected to selector 1218 input 2 and latches that value in the new value latch 1219. The output of latch 1219 is made available to the adder 1210 through selector 1211 and to RAM directly from the output of latch 1219 for storage of new frequency ramp values, or through pipeline buffers 1220 and 1221 for storage of the new amplitude values. Provision is also made to add the value stored in new value latch 1219 and an offset value provided by RAM to shift the new value of amplitude or frequency by a constant given by the offset Latches 1222 and 1223 provide the necessary pipelining delay for the offset value as an input to the 0 input of selector 1212. The offset is added to the output of selector 1211 by adder 1210, thereby creating a new value at a minimum cost in processing effort. Logic network 1224 produces an output control signal CTS from the 2 bit mux control signal in latch 1217 which is asserted when the current target latch value is selected by selector 1218. It is used for incrementing the current line segment pointer when writing to RAM. Before further explaining the circuit of Figure 12, it is worth mentioning the RAM 1014, illustrated in Figure 10, is organized in 8 bit bytes. The slope value is a 12 bit number thus using two 8-bit bytes. The upper 4 bits of the second byte of storage are made available as an update interval control value. Thus, when the current slope value is accessed by the RAM address and control generator 1106 of Figure 11 , the lower 12 bits are stored in latch 1201 while the upper 4 bits are stored in the line segment update interval control register 1205, the output of which is made available to mux control logic unit 1206. The output of adder 1210 is also pipelined buffered to the synthesizer unit 1102 of Figure 11 through register 1226 (and also through latch 1227, in the case of amplitude values), and through selector 1228. Control is provided to select the double buffered output of latch 1227 connected to input 0 for amplitude values and the single buffered output of register 1226 at input 1 for frequency ramp data. Thus, the new value generator output signal is made available to the synthesizer unit 1102.

THE EXPONENTIAΉON. LOGARΓTHMIC CONVERSION AND ^' ACCUMULATOR FUNCTIONS (The Synthesizer Unirt It is now useful to describe the circuitry of the synthesizer unit 1102 in greater detail This may be accomplished widi reference to Figure 14 which is a circuit diagram of the preferred embodiment of this unit In addition, the flow diagram of Figure 13(c) is provided to enhance an understanding of the synthesizer circuitry as it is utilized for (1) looking up a waveform value in waveform memoiy (using waveform value lookup circuitry 1401), (2) synthesizing (multiplying) the waveform value and amplitude value (using waveform/amplitude multiplication circuit 1402), and (3) adding the result of those values to an accumulator (using accumulator circuit 1403). It thus can be understood that blocks 1341-1345 relate to the waveform value lookup circuit 1401; block 1350 relates to the wavefoim/amplitude multiplication circuit 1402; and blocks 1351 and 1361 relate to the accumulator circuit 1403.

Overview of the synthesizer unit functions Although considerable detail and description is provided herein with regard to the circuitry of Figure 14, it may initially be useful to discuss the circuit in terms of the three separate stages which have been briefly mentioned in the preceding paragraph, i.e., the (1) waveform value lookup stage 1401; (2) amplitude multiplication stage 1402; and (3) accumulator stage 1403. The function of these three logically separate stages may be understood with simultaneous reference to Figure 13(c) and to Figure 14. Initially, during the waveform value lookup stage 1401, it is desired to determine the anti-log of the phase angle increment (new frequency value), block 1341. Specifically, the low order 12 bits from the new value unit input (at this stage representing the base 2 logarithm of a phase angle increment) are passed through adder 1429 and pipeline latch 1431 and are used as an address input to anti-log lookup memory 1432. The adder 1429 is, in fact, designed to combine the log of the amplitude with me log of the waveform table value in a subsequent cycle. However, in the prefeired embodiment, Λe phase angle increment is passed through the adder 1429 and a zero value is added to it (selector 1430 is controlled during this stage to select line 0 which inputs a zero value to adder 1429 as its second input). In this way, certain savings are enjoyed in the number of gates required to implement die circuitry of the present invention; specifically, this stage may use the same anti-log circuitry 1432 and shift logic circuitry 1434 as used in the subsequent logical stage. The output of the anti-log look-up memory 1432 is shifted by shift logic 1434 by the amount given in the upper 4 bits of the logarithm, giving the phase angle increment expressed as a linear quantity, thus completing block 1341. Next, the phase angle increment (in linear form) is added to die previous phase angle (read from RAM) by adder 1440, block 1342. As will be seen, this phase angle sum will be used to address the waveform look-up memory 1442. Li die preferred embodiment, the waveform look-up memory 1442 is implemented utilizing read-only memories; however, it will be obvious to one of ordinary skill in the art that in alternative embodiments, other types of memory may be utilized (e.g., read/write memories). The waveform memory 1442 is, in fact, preferably implemented in the ROM illustrated as ROM 1015 of Figure 10. In addition, in the preferred embodiment, waveform look-up memory 1442 is utilized to store the base 2 logarithm of a sine wave. Again, it will be obvious that in alternative embodiments other waveforms may be stored; the particular waveform, of course, affecting the output of the circuit The system of the preferred embodiment is preferably configurable by the control processor to allow use of either 2K x 8 ROMs or 8K x 8 ROMs. Use of 8K x 8 ROMS yield an increase of 10-12 decibals in the signal-to-ratio. ROM configuration is accomplished by die control computer setting a bit in the command register of the gate array. In addition to being utilized to address memoiy 1442, the phase angle sum is also written back to the RAM (via new phase angle latch 1446) for use in the next sample period for this particular sub-sample. It is worth noting that adder 1440 performs different functions depending on which stage (1401, 1402 or 1403) die computation cycle is in. Multiplexors 1436 and 1444 are provided to control the inputs to adder 1440 during each stage. At this point, circuitry is provided to optionally add a frequency modulation (FM) value to the phase angle sum, block 1343. Prior to addressing line segment memory 1442, the summed phase angle passes through inverter 1448 which is controlled to invert (reverse all bits) of the summed value whenever die phase angle points to the second or fourth quadrents of a unit circle, block 1344. This inversion allows the design to take advantage of die symmetry of the sine function resulting in the waveform table size being reduced by a factor of 4. The waveform memoiy 1442 is then addressed by the summed phase angle value (either inverted or not inverted) and the base 2 logarithm of a sine value is read from the memory 1442, block 1345.

Detailed description of the synthesizer unit Having provided the above overview, it now may be useful to describe in greater detail the operations of die synthesizer unit Initially, the new value unit provides a positive valued input signal on line 1410. (In a first cycle this value represents the new frequency, in a second cycle, the value represents the new amplitude). The least significant 12 bits of this value are treated as die fractional mantissa portion of a base two logarithm while the upper 4 bits are treated as the integer characteristic value. The fractional value lower 12 bits are provided as the first input to adder 1429 while the upper 4 bit characteristic is stored in the upper portion of die 21 bit pipeline latch 1431. The second 12 bit input to adder 1429 is similarly obtained from die lower 12 bits of the 16 bit output from selector 1430 so that the sum appears at the ouφut of adder 1429 as a 12 bit signal and is stored in the lower part of pipeline latch 1431. φuring a first cycle, a zero value is added to the frequency, as explained above; during the second cycle, the log of die waveform value derived during die first cycle is added to the log of the amplitude.) The upper4 bit part is also stored unchanged in pipeline latch 1431. Because die sum of two 12 bit numbers may result in an overflow, the carry out bit is also stored in latch 1431. The pair of 4 bit characteristic values are summed by adder 1437 and the carry out bit from adder 1429 (communicated dirough latch 1431) is applied as a carry-in bit to adder 1437. L this manner, the proper base two characteristic value appears at the output of adder 1437 and is stored in shift count latch 1438. The lower 12 bits in latch 1431 are applied as a read address to anti-log (exponentiating) look-up table 1432 to produce a corresponding 16 bit exponentiated value which is stored in pipeline register 1433. (It should be noted that look-up table 1432 is illustrated as circuitry included witiiin the synthesizer engine for sake of convenience and clarity. However, in die preferred embodiment, the look-up table is implemented in a ROM shown as ROM 1015 on Figure 10). Latches 1438 and 1433 respective outputs are applied to shift logic unit 1434 for integer value exponentiating or binary scaling in accordance witii the 5 bit characteristic value represented by latch 1438 output signal. Because of this, a substantially smaller anti-log look-up table memory may be employed for exponentiating in much the same manner as floating point representation of numbers allows a greater range of values to be represented by a given number of bits. Thus, adder 1437, latch 1438, anti-log memory 1432, register 1433 and shift logic unit 1434 constitute an embodiment of a floating point anti-log or exponentiating means. On the first cycle, die ouput from die exponentiating means represents the phase angle increment The phase angle increment passes, unmodified through control inverter 1435 and on tiirough selector 1436 to adder 1440 where it is added to the previous phase angle obtained from latch 1445 via input 0 of selector 1444. The result is placed into die new phase angle latch 1446 where it is available for writing back to RAM and where it is also available, via input 1 of selector 1444, to be added to die FM value obtained from latch 1455 via input 1 of selector 1436. The result is then passed to controlled inverter 1448. As can be seen, in die preferred embodiment, adder 1440 is provided witii a variety of inputs, each of which are used in different stages of the computation of a sub-sample value. This multiplexed use of the adder, while conceptually complex, results in a significant reduction in circuit cost The control signal for controlled inverter 1448 is obtained from the second most significant bit of the phase angle value. This bit indicates die quadrant of the phase angle and causes die inversion of die phase angle whenever it is in the second or fourth quadrants. The most significant bits of the ouφut from the controlled inverter 1448 are stored temporarily in pipehne latch 1449 and are then used as the address for the log-sine waveform look-up table 1442. The value read from the ROM 1442 arrives via input 1 of multiplexor 1430 as one input to adder 1429 in time to be added to logarithm of the new amplitude value arriving from the new value generation unit 1101. The result of this addition (the addition of the two logarithms) is the logarithm of the product of the wavefoim sample value and the amplitude value, block 1350 (also previously shown as block 1304). At this point the antilog is taken of the logarithmic value and the result of the antilog function is passed through inverter 1435, block 1351. The inverter 1435 is controlled to invert the product whenever the phase angle points to either quadrant three or four of a unit circle (i.e., where the waveform value is negative). Finally, the finished value is added to the value stored in sample accumulator latch 1447 using adder 1440, block 1361 (previously also shown as block 1307). After 64 sub-samples (one for each oscillator on the gate array) have been accumulated die sum in the sample accumulator is ouφut from the gate array to the D-to-A converter, block 1308. It should be noted again that waveform memory 1442 may contain a representation of any periodic function exhibiting die following symmetries: odd symmetry between me first two quadrants and the last two quadrants; even symmetry between the first and second quadrants; and even symmetry between the third and fourth quadrants. Even though the prefeired embodiment takes advantage of such symmetry in order to reduce look-up table memory requirements, it is recognized that larger look-up table memories could be employed for waveforms which may not have the required symmetry. Two additional ouφut paths from adder 1440 are provided: an ouφut accumulator path including detection network 1450, accumulator 1447 and shift register 1451; and, a frequency modulation accumulator feedback patii including detection network 1452, and fin accumulator latch 1453. Detection circuits 1450 and 1452 perform the same basic function of detecting if an overflow or underflow occurred during the addition process in adder 1440 and, if so, the detection circuits replace the value with the maximum (saturation) positive or negative value. Overflow in two's-complement occurs whenever two numbers of the same sign (same msb) when added together cause a change in sign in the adder ouφut. Thus, if two 20 bit input numbers are represented by A<0: 19> and B<0: 19>, and die 20 bit adder ouφut by SUM<0: 19>, then the following logical relationships between die sign bits, A<19>, B<19>, and SUM<19>, defines overflow and underflow:

A<19> • B<19> • SUM < 19 > = UNDERFLOW

A < 19 > . B < 19 > . SUM<19> = OVERFLOW The operation of detection networks 1450 and 1452 may be described by the truth table, Table 1, in combination widi die above definitions.

Table 1.

The two right-hand columns represent the ouφut states of die msb, SUM<19>, and die lesser 19 bits, SUM<0: 18>. If neither underflow or overflow occurs, the ouφut bits, SUM<0: 19>, are unchanged; if overflow occurs, SUM<19>, is set to zero and all 19 lesser bits, SUM<0: 18>, are set to one; if underflow occurs, SUM<19> is set to one and bits, SUM<0: 18>, are set to zero; and because botii overflow and underflow can not simultaneously occur, the ouφut states are undefined. Angle modulation may also be introduced by means of selector switch 1454 and its associated ouφut latch 1455, die ouφut of which is made available to adder input selector 1436 and to RAM for storage. Selector 1454 provides the means to select the source of modulation from eitiier RAM or die ouφut of control inverter 1435. Either way, a previously synthesized value may be used as the modulating signal. A further improvement in economy and performance is effected by die look-up table memory rounding network 1456. As was previously mentioned, the look-up table memory may have either two 8Kx8 memories organized as an 8Kxl6 memory or two 2Kx8 memories organized as 2Kxl 6 memory; die latter choice being desirable when costs are to be minimized. In either event it is recognized by die present invention that if the least significant address bits are simply ignored the waveform memory address may be in error by an amount equal to its lowest bit position. This error may be reduced by looking at the discarded bits and rounding up or down in accordance with a chosen rounding rule, e.g., in die preferred embodiment die rule used is to round up if the discarded bits have a value equal to or greater than 1/2 of the retained address least significant bit Therefore, as one inventive aspect of the present invention, waveform memoiy rounding network 1456 adds a bit to the least significant addressing bit if die discarded most significant bit is on, thereby rounding up die value retained by die reduced field of addressing bits. The waveform rounding network is coupled to receive the low order bits from the address information. The waveform rounding network is further coupled to provide a one-bit input to adder 1440. If the most significant discarded bit is a one, waveform rounding network 1456 provides a one ouφut If die most significant discarded bit is a zero, waveform rounding network 1456 provides a zero ouφut Of course, the particular bit position regarded by waveform rounding network as the most significant discarded bit will vary depending on die memoiy configuration installed. RANDOM ACCESS MEMORY (RAM! ORGANIZATION It is now appropriate to again refer to Figure 10 which illustrates a system level block diagram of the preferred embodiment of die present invention. In particular, it is useful to discuss in greater detail the particular organization of the memory storage of RAM 1014 so that the reader will have a better appreciation of die data structures employed by the present invention. As can be seen, the RAM 1014 is preferably organized as eight banks of 2K x 8 static RAMs. The memory is organized in accordance with the memory map of Table 2 below: ADDRESS BNK O BNK 1 BNK 2 BNK 3 BNK BNK 5 BNK 6 BNK 7

0 TO 63 FR. AMP PHASE ANGLE CURRENT CURRENT LS. LS. FREQUENCY AMPLITUDE 1 1 - - -

64 TO 127 FM FREQUENCY FM DATA SLAVE SERIAL PTR OFFSET DATA DATA

128 TO 191 COMMAND AMPLITUDE WORD OFFSET

^■ i ^•i

1024 TO 2047 FREQUENCY FREQUENCY AMPLITUDE AMPLITUDE TARGET SLOPE TARGET SLOPE

I 1 1

I O 0-7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 DATA LINES

Table 2

The various items making up the contents of RAM 1014 are defined as follows: FR. L.S.: Current frequency line segment pointer for each of the 64 oscillators. This is a 4 bit quantity and it occupies the lower four bits of this byte.

AMP. L.S.: Current amplitude line segment pointer for each of the 64 oscillators. This is a 4 bit quantity and it occupies the upper four bits of this byte.

Phase Angle: Current Phase angle for each of the 64 oscillators. This is 20 bit quantity so the most significant 4 bits in bank 3 are not used. Current Frequency: Current frequency value for each of the 64 oscillators. Current Amplitude: Current amplitude value for each of the 64 oscillators. FM PTR: Frequency modulation pointer for each of the 64 oscillators. This is only a 6 bit quantity so the most significant 2 bits in this byte are don't cares. Frequency Offset: Current frequency offset for each of the 64 oscillators. This is a signed twos-complement number. FMData: Current frequency modulation value for each of the 64 oscillators. This is a signed twos-complement number. Command Word: Current α>mmand wOTd for each of the 64 oscillators. The command word may be updated under die control of the control processor, for example, the control processor may update the oscillator active bit to inactivate a particular oscillator when parameters are being loaded for that oscillator. After die parameters are loaded, die control processor may then activate die oscillator to allow the synthesizer to begin operations on die new parameters. In this way, potential problems associated with beginning processing of parameters before all parameters are loaded can be avoided, h addition, addressing information (bits 5-0) is provided for allowing pointing to parameters for a different oscillator. Using tiiis addressing information and by enabling the next oscillator amplitude pointer (AP) and/or next oscillator frequency pointer (FP), any particular oscillator can be set to utilize parameters of another oscillator. This feature offers the inventive advantage of allowing a single oscillator's rjarairietere to be loaded and diose parameters to be used by multiple oscillators where, for example, a number of partials have the same envelope shape. Finally, control bits are included to optionally allow the sample to be added to die frequency modulation accumulator (PA); to allowing clearing of the FM accumulator (CP); and to control die source for die FM value (PS). Using these control bits, die control computer can control die synthesizer to use the sum of the current values for any arbitrary set of oscillators as the FM source for any subsequent oscillator. The command word has the following format, where the numbers below each bit indicate RAM data line used

- „ Oscillator Active Bit 0=lnactive, l=Active. P: FM cycle enable bit 0=FM disabled 1=FM enabled. PA: Add sample to FM accumulator. 0=No add, l=Add. SA: Add sample to sample accumulator. 0=No add, l=Add. CP: Clear FM accumulator. 0=No clear, l=Clear. PS: FM value source. 0=Use accumulator, l=Use RAM. X: Unused bits. AP: Next oscillator amplitude pointer enable. 0=Disabled, l=Enabled. FP: Next oscillator frequency pointer enable. 0=Disabled, l=Enabled. 5-0: Next oscillator pointer to use for amplitude and frequency values. 5 is die most significant bit Amplitude Offset: Current amplitude offset for each of the 64 oscillators. This is a signed twos-complement number. Frequency Target: Current frequency target for each line segment of each oscillator (16 line segments per oscillator). Frequency Slope: Current frequency line segment slopes for each line segment of each oscillator. Amplitude Target: Current amplitude target for each line segment of each oscillator ( 16 line segments per oscillator). Amplitude Slope: Current amplitude line segment slopes for each line segment of each oscillator. MASTER/SLAVE CONFIGURATION It has been previously mentioned that as one aspect of die present invention, a particular implementation may utilize a plurality of gate arrays (specifically, the preferred embodiment provides for use of up to 8 gate arrays in a single system). As has been discussed one gate array in a particular implementation is designated as the master gate array and die remaining (zero to seven) are designated as slave gate arrays. The particulars of this implementation will now be discussed with initial emphasis on circuitry for controlling designation (master or slave) of a particular gate array and then emphasis on discussing particulars of communication of information between gate arrays in the system. Control of designation of gate arrays (master or slave) Each particular system is configured to have one master gate array and up to seven slave gate arrays. The designation of a particular gate array as die master gate array is accomplished by die host computer setting a "master" bit in a register of die CPU interface 1108, All other gate arrays in the particular implementation will have the "master" bit cleared. It is also worth noting that in the prefeired embodiment dip switches 1051 are provided. The dip switches 1051 may be set to indicate whetiier me system is to be configured in a stereo or mono configuration. Signals from the dip switches on hne 1052 operate to control stereo/mono switching circuit 1053. In addition, dip switches 1051 provide signals on line 1055 indicative of die number of gate arrays employed in the particular system. Of course, in an alternative embodiment, odier means may be used to indicate die number of gate arrays and whetiier ouφut is to be in stereo or mono. For example, the host computer may act to set registers indicative of the number of gate arrays and whether it is desired to have stereo or mono ouφut. Communication and control of data between gate arrays The tone data of each slave gate array is communicated, on a time sliced basis, through stereo/mono switch 1053 to tristate buffer 1054. Tristate buffer 1054 is controlled by the ouφut enable control signal on line 1012 from die state machine and timing generator 1103 of the master unit gate array 1001. The master gate array is coupled to receive, on dual purpose line 1058, data from die slave gate arrays. The data from the slave gate arrays is provided to serial data generator 1104 on line 1121. Serial data generator is responsible for summing, in a bit-serial manner, die input data from the master gate array and die (up to seven) slave gate arrays. Of course, in an alternative embodiment, the above-mentioned summation step may be performed in a parallel mode. The master gate array tiien controls die latch 1021 and sample and hold circuit 1026 to accept the summed ouφut data. As was discussed, die number of effective ouφut lines of switch 1053 and die order of enabling (for purposes of configuring the system to ouφut in stereo or mono) is controlled by dipswitch unit 1051. The dipswiteh unit 1051 settings also control die address decode logic unit 1057 that steers the CPU addressing data to the proper syntiiesizer unit The summation of data from die master and slave gate arrays is perhaps better understood with reference to Figure 15. Figure 15 is a functional block diagram of the serial data converter 1104 with die addition of showing, in the upper left region, a portion of synthesizer unit 1102. The syndiesized data consisting of up to 64 tones is accumulated in sample accumulator latch 1520. The 16 most significant bits of the data in accumulator latch 1520 are parallel fed to and latched in shift register 1521 by a control signal on tine 1523. Data is shifted out of shift register 1521 on line 1525, least significant bit first, into master latch 1524. The ouφut of latch 1524 is coupled to present to input 2 of selector 1531 four identical parallel bits for each ouφut synthesizer bit stored in shift register 1521. The ouφut of shift register 1521 is also available for use as local serial data and is recirculated to allow die reuse of each ouφut sample word. When tiiere is a single gate array operating in the system or when a gate array is operating as a slave gate array, selector 1531 is set at input 2 thus allowing the four bit ouφut of shift latch 1524 to be fed to die input of 4-bit serial adder 1501 causing the ouφut signal of the adder to be the sum of four identical syntiiesizer ouφut signals. The ouφut is latched into register 1502. This arrangement allows die same adder to be used whetiier the gate array is operating in a single gate array mode or as a master in a master-slave configuration. In die case of a gate array operating as die master in a master-slave configuration, up to eight separate synthesizer ouφuts may be summed by means of four bit left channel latch 1560 and right channel latch 1561. Each of die latches 1560 and 1561 obtain die required 4 channel serial data from the slave data input lines 1121. It is noted that these slave data input lines 1121 are dual purpose lines as illustrated by Figure 10 and are also used by die gate array when accessing RAM 1014. Selector 1531 alternately connects left channel latch 1560 and then right channel latch 1561 to selector 1531 input 0 and input 1, respectively when die gate array is configured for master mode and at least one slave gate array is present Li tiiis way serial adder 1501 is beneficially multiplexed for efficiency. The ouφut signal from register 1502 is made available to AES converter 1570 for converting die serial data received from register 1502 to the Audio Engineering Society AES 3-1985 (ANSI 54.40-1985) format The ouφut signal from register 1502 is also coupled to serial converter 1571 for converting the data received from register 1502 to serial data straight format Straight serial converter 1571 converts the ouφut of register 1502 into two serial data formats and also produces clock and control signals.

Thus, what has been described is a new and improved means for synthesizing musical and otiier tones.

Claims

CJ- JMS What we claim is:

1. A system for performing synthesis of signals comprising: a host computer interface for communicating information witii a host computer, audio ouφut circuitry for providing syndiesized ouφut signals; a master synthesizer circuit coupled with said host computer interface to receive input signals from a host computer through said host computer interface and to provide ouφut signals to said audio ouφut circuitry; a slave syntiiesizer circuit coupled witii said host computer interface to receive input signals from a host computer through said host computer interface and further coupled to said master syntiiesizer to provide ouφut signals to said master syntiiesizer, and summation means for summing ouφut signals of said master synthesizer and said slave synthesizer.

2. The system for performing synthesis of signals of claim 1 further comprising control buffer means coupled for buffering ouφut of said slave syntiiesizer and for providing said buffered ouφut to said master syntiiesizer.

3. The system for performing synthesis of signals of claim 1 wherein said summation means comprises a serial bit adder for adding infoimation received from said master synthesizer and said slave synthesizer.

4. The system for performing synthesis of signals of claim 3 wherein said summation means further comprises a first input for receiving synthesized ouφut information of said master syntiiesizer and second input for receiving synthesized ouφut information of said slave syntiiesizer.

5. The system for performing syntiiesis of signals of claim 1 further comprising first memory means coupled to said master synthesizer to store frequency and amplitude information.

6. The system for performing syntiiesis of signals of claim 5 further comprising second memory means coupled to said slave synthesizer to store frequency and amplitude information.

7. The system for performing synthesis of signals of claim 1 fiirther comprising a system clock coupled to provide clocking signals to said master synthesizer.

8. The system for performing synthesis of signals of claim 7 wherein said slave synthesizer is further coupled to receive clocking signals from said system clock.

9. The system for performing synthesis of signals of claim 1 wherein said master syntiiesizer and said slave synthesizer are coupled under control of a common clock signal generator.

10. The system for performing synthesis of signals of claim 1 wherein said signals are representative of musical tones.

11. The system for performing synthesis of signals of claim 10 wherein summation means comprises a first input for receiving first signal inputs representative of musical tones for a first ouφut channel and further comprising a second input for receiving second signal inputs representative of musical tones for a second ouφut channel.

12. The system for performing syntiiesis of signals of claim 11 wherein said summation means comprises serial data ouφut circuits.

13. The system for performing synthesis of signals of claim 11 wherein said summation means comprises AES/EBU format ouφut circuits.

14. The system for performing synthesis of signals of claim 1 wherein said master synthesizer is embodied in a gate array.

15. The system for performing syntiiesis of signals of claim 1 wherein said slave synthesizer is embodied in a gate array.

16. A circuit for syntiiesizing a musical tone comprising: a first memory for storing data representative of a first component and a second component of said musical tone; first means coupled for receiving certain of said stored data representative of said first component and said second component at a given sample ouφut time and for providing as a first data ouφut an accumulated synthesized ouφut representative of said first component and said second component; a second memory for storing data representative of a third component and a fourth component of said musical tone; second means coupled for receiving certain of said stored data representative of said diird component and said fourth component at a given sample ouφut time, said second means coupled to said first means for providing as a second data ouφut an accumulated synthesized ouφut representative of said tiiird component and said fourth component; third means coupled to receive said first data ouφut and coupled to receive said second data ouφut, said third means for providing a summed ouφut representative of said musical tone.

17. The circuit of claim 16 wherein said first component, said second component, said tiiird component and said fourth component are representative of frequency components of said musical tone.

18. The circuit of claim 16 wherein said circuit further comprises a host computer interface for receiving said first component, said second component, said tiiird component and said fourth component.

19. The circuit of claim 18 further comprising circuitry for providing feedback to a host computer over said host computer interface.

20. A system for synthesizing musical tones comprising: first data storage means for storing first data representative of a first linear segment of a frequency component of said musical tone, said first data storage means further for storing second data representative of a second linear segment representative of a amplitude component of said musical tone; second data storage means for storing data representative of a waveform, said data representative of a waveform stored as a plurality of logarithmic values; a first circuit coupled to said first data storage means to receive data representative of a portion of said first linear segment, said first circuit providing as a first ouφut a value representative of a position on said first linear segment, said first ouφut provided as a logarithmic value, said first circuit further coupled to said first data storage means to receive data representative of a portion of said second linear segment, said first circuit providing as a second ouφut a value representative of a position on said second linear segment, said second ouφut provided as a logarithmic value; a second circuit coupled to receive said first ouφut, said second circuit applying a representation of said first ouφut as an address value to look-up a corresponding value in said waveform memory, said waveform memory being read at said address to provide a look-up value; said second circuit further coupled to receive said second ouφut, said second ouφut including adding means for adding said second ouφut and said look-up value, said adding means providing as an ouφut a summed value; said second circuit further comprising anti-log means, said anti-log means coupled to receive said summed value and to provide as an ouφut an anti-log of said summed value.

21. The system for synthesizing musical tones of claim 20 wherein said first data representative of a first linear segment of a frequency component of said musical tone is represented as die log of said first linear segment.

22. The system for synthesizing musical tones of claim 20 wherein said waveform is representative of a sine wave.

23. The system for synthesizing musical tones of claim 20 wherein said anti-log means is further coupled to receive said first ouφut and to provide as an ouφut a look-up value address.

24. A computer controlled digital music synthesizer system comprising: a) first ramp generator means for generating a linear ramp responsive to the frequency parameters provided by a control computer, representing a linear ramp with specified initial value, sample increment and target value; b) first exponentiating means, coupled to die ouφut of said first ramp generator means, for converting said linear ramp into an exponential ramp, representative of a phase function; c) log-sine converter means, coupled to die ouφut of said first exponentiating means, for converting said phase function into a log-sine function representative of the logarithm of the magnitude of a sinusoid witii said phase function as its argument and for generating a signum flag to indicate polarity; d) second ramp generator means for generating a linear ramp, responsive to die amplitude parameters provided by said control computer, representing a linear logarithmic ramp witii specified initial value, sample increment and target value; e) adder means coupled to die ouφut of said log-sine converter means and of said second ramp generator, for producing the sum of said amplitude ramp value and said log-sine function value representative of the logarithm of the product of an exponential amplitude ramp function value, whose logarithm is said amplitude ramp value; and f) second exponentiating means coupled to the ouφut of said adder means for forming the anti-logarithm of said adder ouφut and applying polarity in accordance with said signum flag.

25. The synthesizer system of claim 24 further comprising: a) angle modulating accumulator means, for accepting and accumulating an angle modulating signal; and b) second adder means connected to die ouφut of said modulating accumulator and to die ouφut of said first exponentiating means, for producing an angle modulated phase function, the ouφut of said second adder means connected to die input of said log- sine converter means.

26. A system for synthesizing a musical tone wherein said musical tone is represented by data defining a plurality of line segments, said system comprising: a memory for storing information representative of a plurality of line segments; a control computer coupled to provide said memory witii said plurality of line segments; a synthesizer circuit for synthesizing musical tones based on said plurality of line segments, said synthesizer circuit coupled to read said stored information from said memory, said synthesizer unit further coupled witii said control computer to provide feedback to said control computer, said feedback indicative of the status of said reading said stored information from said memory.

27. The system for synthesizing a musical tone of claim 26 wherein said synthesizer unit is further coupled to receive control information from said control computer.

28. The system for synthesizing a musical tone of claim 27 wherein said control information comprises addressing information for addressing said memory.

29. The system for syntiiesizing a musical tone of claim 28 wherein said control information is coupled with said synthesizer unit to provide addressing information to address line segment information representive of up to 64 separate components of said musical tone.

30. The system for synthesizing a musical tone of claim 28 wherein said memory is coupled to receive line segment information representative of up to 64 separate harmonic components of said musical tone.

31. The system for syntiiesizing a musical tone of claim 26 wherein said information representative of a line segment comprises a current slope value and a current frequency value.

32. The system for synthesizing a musical tone of claim 31 wherein said syntiiesizer unit further comprises circuitry for generating a new frequency value based on said current slope value and said current frequency value.

33. The system for synthesizing a musical tone of claim 32 wherein said synthesizer unit further comprises comparison means for comparing said current frequency value with a target value, said comparison means for determing if said current slope value is to be added or substracted from said current frequency value to compute said new frequency value.

34. The system for synthesizing a musical tone of claim 33 wherein said current slope and said current frequency value are 16-bit values.

35. The system for synthesizing a musical tone of claim 32 wherein said synthesizer unit further comprises comparison means for comparing said new frequency value witii a target value.

36. Li an apparatus for producing a synthesized musical tone from stored data representative of lines segments of a first waveform component of said musical tone, said apparatus including a control computer for supplying line segment information to a synthesizer circuit, said synthesizer circuit having a first memory for storing said data and a processing portion coupled to receive said data from said first memory, said processing portion- for processing said data, an improvement wherein said syntiiesizer circuit further comprises: -

(a) address generation circuitry coupled for providing address information to said first memory, said address generation circuity coupled to receive control information from said control processor, and

(b) an interface coupled to receive blocks of said data from said control computer and to supply said data to said first memory under control of said address generation circuitry.

37. The improvement of claim 36 wherein said waveform component is a frequency component.

38. The improvement of claim 37 wherein said line segment infoimation comprises information on an initial frequency value, a target frequency value and a slope for each line segment transfeired from said control computer to said first memory portion.

39. The improvement of claim 36 wherein said synthesizer circuit further comprises a second memory portion for storing waveform information.

40. The improvement of claim 39 wherein said processing portion comprises circuitry for configuring access to said second memory portion, said processing portion configurable to access either memories of a first capacity or memories of a second capacity.

41. The improvement of claim 40 wherein said memories of a first capacity are 2K by 8 ROMS.

42. The improvement of claim 41 wherein said memories of a second capacity are 8K by 8 ROMS.

43. The improvement of claim 34 wherein said synthesizer circuit is capable of simultaneously storing and accessing a second waveform component of said musical tone.

44. The improvement of claim 43 wherein said synthesizer circuit produces a first ouφut based on said first waveform component and a second ouφut based on said second wavefoπn component

45. The improvement of claim 44 wherein said synthesizer circuit utilizes said first ouφut as a frequency modulated input for calculation of said second ouφut.

46. The improvement of claim 43 wherein said syntiiesizer circuit produces both a first ouφut based on said first waveform component during a first time period and a second ouφut based on said first waveform component during said first time period.

47. A system for synthesizing musical tones comprising a host computer for supplying line segment approximations of components of tones to be synthesized over a host computer interface to a gate airay, said host computer coupled with said gate array through said host computer interface, said system further comprising a memory for storing said line segement approximations, said memory coupled with said gate array, said gate array comprising: circuitry for receiving said line segment approximations from said host computer interface; and memory interface circuitry for supplying said line segment approximations received from said host computer to said memory.

48. The system of claim 47 wherein said memory comprises single ported memory integrated circuits.

49. The system of claim 48 wheren said memory comprises random access memories.

50. In an apparatus for producing a syndiesized musical tone from stored data representative of lines segments of a first wavefoim component of said musical tone, said apparatus including a control computer for supplying line segment information to a synthesizer circuit, said syntiiesizer circuit having a first memory for storing said data, an improvement wherein said synthesizer circuit further comprises:

(a) a processor for processing said data, said processor coupled to receive said data from said first memory;

(b) address generation circuitry coupled for providing address information to said first memory, said address generation circuity coupled to receive control information from said control processor, said address generation circuitry further coupled to receive control information from said processor, and

(c) an interface coupled to receive said data from said control computer and to supply said data to said first memory under control of said address generation circuitry, said interface operable to receive data from said control computer while said processor is processing data.

1. An apparatus for synthesizing tones comprising: (a) a control computer for providing information representative of said tones;

(b) a synthesizing means for synthesizing tones from said information, said syntiiesizer coupled with said control computer;

(c) a first memoiy means for storing information representative of said tones, said first memory means coupled with said synthesizing means; and

(d) a second memory means for storing waveform information, said second memory means coupled with said synthesizing means;

(e) said synthesizing means having an addressing means for addressing said second memory means, said addressing means including a rounding network for rounding addresses supplied by said addressing means, said addressing means coupled with said second memoiy means.

52. The apparatus as recited by claim 50 wherein said syntiiesizing means is coupled under control of said control computer to provide addresses from said addressing means for either high capacity second memoiy means or for low capacity second memory means.

53. The apparatus as recited by Claim 52 wherein said high capacity second memory means comprise 8K by 8 ROMs.

54. The apparatus as recited by Claim 53 wherein said low capacity second memory means comprise 2K by 8 ROMs.

55. An apparatus for synthesizing musical information comprising:

(a) a first synthesizer for synthesizing musical information, said first synthesizer providing a first ouφut on a first line;

(b) an ouφut circuit for ouφut of synthesized musical information, said ouφut circuit having a latch coupled for receiving said syndiesized musical information on said first tine, said latch coupled under the control of said first syntiiesizer; (c) a second syntiiesizer for synthesizing musical information, said second syntiiesizer coupled to provide an ouφut over said first line to said first syntiiesizer, said first synthesizer controlling said latch to latch infoimation on said first line during periods when said first synthesizer is receiving said ouφut from said second synthesizer and not to latch information on said first line during periods when said first synthesizer is ouφutting information on said first line.

56. An apparatus for synthesizing musical tones including a control computer for supplying line segment information representative of musical tones, a memory for storing said line segment infoimation and a syntiiesizer for syntiiesizing musical tones from said line segment information, said synthesizer including a new value generation unit for generating new line segment information, said new value generation unit coupled to receive, as inputs from said memoiy, current line position, desired increment and target values, said new value generation unit comprising:

(a) an adder for adding the value of die current line position to the value of desired increment and providing a result;

(b) a first comparator for comparing the value of the result and the target value; and

(c) write-back circuitry for writing line position data back to said memory, said write-back circuitry comprising a multiplexor coupled to receive said result and said target values, said write-back circuitry further comprising control circuitry for controlling said multiplexor based on die ouφut of said first comparator.

57. A system for synthesizing a musical tone wherein said musical tone is represented by data defining a plurality of line segments, said system comprising: a memory for storing information representative of a plurality of line segments; a control computer coupled to provide said memory with said plurality of line segments; a synthesizer circuit for synthesizing musical tones based on said plurality of line segments, said syntiiesizer circuit coupled to read said stored infoimation from said memory, said syntiiesizer unit further coupled witii said control computer to provide continuous, periodic timer interrupts to said control computer.

58. The system as recited by claim 57 wherein said control computer provides timer interrupts every 46.44 milliseconds to said control computer.

59. The system as recited by claim 58 wherein said system performs additive synthesis of musical tones.

60. An apparatus for producing synthesized musical tones comprising:

(a) a memory for storing line segment infoimation representative of said musical tones;

(b) a control processor for supplying said line segment infoimation to said memory;

(c) a synthesizer for synthesizing musical tones from said line segment information, said synthesizer coupled with said memory to receive said line segment information, said synthesizer having storage means for storing control information for said synthesizer, said control information including control for enabling and disabling functions of said synthesizer.

61. The apparatus as recited by claim 60 wherein said control processor is coupled with said syntiiesizer to allow updating of said control infoimation.

62. An apparatus for producing synthesized musical tones comprising:

(a) a memory for storing line segment information representative of said musical tones;

(b) a control processor for supplying said line segment information to said memory;

(c) a synthesizer for synthesizing musical tones from said line segment information, said synthesizer comprising a first oscillator and a second oscillator, said first oscillator having associated therewith a first control word, said first control word including addressing infoimation for allowing addressing of parameters for said second oscillator.

63. The apparatus as recited by claim 62 wherein said control processor is coupled with said syntiiesizer to allow updating of said control first control word

64. An apparatus for producing syndiesized musical tones comprising:

(c) a syntiiesizer for synthesizing musical tones from said line segment information, said syntiiesizer comprising a first oscillator, a second oscillator and a third oscillator, said synthesizer having an accumulator for accumulating ouφuts of said first and second oscillators, said third oscillator having associated therewitii a first control word, said first control word including control information for controlling said third oscillator to utilize a value stored in said accumulator as frequency modulation source.

65. An apparatus for synthesizing musical tones including a control computer for supplying a plurality of sets of line segment infoimation representative of musical tones, a memory for storing at least a first set of said line segment information and a second set of said line segment infoimation, and a synthesizer for synthesizing musical tones from said line segment information, said synthesizer including:

(a) means for receiving and repositioning a current line position, associated with said first set, to a new line position;

(b) a first comparator for deterπώiing when said means for receiving and repositioning has completed processing of said first set; and

(c) when said means for receiving and repositioning has completed processing of said first set, beginning processing of said second set

66. A syntiiesizer for producing musical tones from stored infoimation, said stored information including amplitude data and frequency data, said syntiiesizer comprising:

(a) waveform/amplitude multiplication means coupled to receive, in a first cycle, said frequency data, said frequency data being represented as a logarithmic value, said waveform amplitude multiplication means comprising an anti-log circuitry for converting said frequency data represented as a logarithmic value to frequency data represented as fixed number;

(b) waveform lookup means coupled to receive said frequency data represented as a fixed number and to provide as an ouφut a waveform value, said waveform value being represented as a logarithmic value; and

(c) said waveform/amplitude multiplication means further coupled to receive in a second cycle said waveform value represented as a logarithmic value and to receive an amplitude value represented as a logarithmic value, said waveform/amplitude multiplication means further comprising means for effecting multiplication of said waveform value and said amplitude value producing a result, said result being converted by said anti-log circuitry to a fixed number.

67. An apparatus for synthesizing musical information comprising:

(a) a first synthesizer for synthesizing musical information, said first synthesizer providing an ouφut on a first line;

(b) an ouφut circuit for ouφut of synthesized musical information, said ouφut circuit having a latch coupled for receiving said synthesized musical information on said first line, said latch coupled under die control of said first syntiiesizer,

(c) said first synthesizer controlling said latch to select information on said first line during periods when said first synthesizer is ouφutting said synthesized musical infoimation.

68. A method for producing synthesized musical tones comprising the steps of:

(a) a synthesizer reading data from a memory on a first line during a first period, said synthesizer ouφutting on said first tine a first portion of an audio ouφut signal during a second period;

(b) said synthesizer reading data from said memory on said first line during a third period, said synthesizer ouφutting on said first tine a second portion of said audio ouφut signal during a second period.

69. An apparatus for synthesizing musical tones including a synthesizer for synthesizing musical tones, said synthesizer comprising:

(a) waveform lookup circuitry for looking up a waveform value based on a frequency value input;

(b) waveform amplitude multiplication circuitry for multiplying said waveform value by a amplitude value input, said waveform/amplitude multiplication circuitry providing a result;

(c) accumulator for accumulating said result from each of a plurality of clock cycles and storing an accumulated sum; and (d) overflow detection means for detecting when said accumulated sum exceeds a threshold level, said overflow detection means replacing said accumulated sum with - a maximum value when said accumulated sum exceeds said threshhold level.

70. An apparatus for synthesizing musical tones including a synthesizer for synthesizing musical tones, said synthesizer comprising:

(b) waveform/amplitude multiplication circuitry for multiplying said wavefoim value by a amplitude value input, said waveform/amplitude multiplication circuitry providing a result;

(c) accumulator for accumulating said result from each of a plurality of clock cycles and storing an accumulated sum; and

(d) underflow detection means for detecting when said accumulated sum underflows a threshold level, said underflow detection means replacing said accumulated sum witii a minimum value when said accumulated sum underflows said threshhold level.

71. A method for communicating data in a system for producing synthesized musical tones, said system comprising a plurality of oscillators, said method comprising the steps of:

(a) storing first information in a memory, said first information representatative of a portion of a musical tone;

(b) controlling a first oscillator utilizing said first information;

(c) controlling a second oscillator utilizing said first information.

72. A method for communicating data in a system for producing syndiesized musical tones, said system comprising a host computer, a host computer interface coupled to communicate information with said host computer, a synthesizer coupled to communicate information with said host computer interface, and an ouφut circuit coupled to receive data representative of synthesized musical tones from said host computer, said method comprising the steps of:

(a) said host computer communicating first information to said host computer interface for processing by sa'd synthesizer,

(b) said host computer interface communicating said first infoimation to said synthesizer,

(c) said synthesizer receiving said first information;

(d) said synthesizer processing said first information;

(e) said host computer communicating second information to said host computer interface for processing by said syntiiesizer,

(f) said host computer interface communicating said second information to said synthesizer,

(g) said synthesizer receiving said first information into a buffer memory;

0ι) said synthesizer continuing to process said first information after having received said second infoimation into said buffer memory; (i) said synthesizer processing said second information.

73. The method as recited by claim 72 wherein said second information is a command to read data from a first memory coupled with said synthesizer.