Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/50—Overload detection or protection within a single switching element
  • H04L49/505—Corrective measures
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/02—Details
  • H04L12/16—Arrangements for providing special services to substations
  • H04L12/18—Arrangements for providing special services to substations for broadcast or conference, e.g. multicast
  • H04L12/1886—Arrangements for providing special services to substations for broadcast or conference, e.g. multicast with traffic restrictions for efficiency improvement, e.g. involving subnets or subdomains
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/20—Support for services
  • H04L49/201—Multicast operation; Broadcast operation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/20—Support for services
  • H04L49/201—Multicast operation; Broadcast operation
  • H04L49/203—ATM switching fabrics with multicast or broadcast capabilities
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/30—Peripheral units, e.g. input or output ports
  • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/30—Peripheral units, e.g. input or output ports
  • H04L49/3009—Header conversion, routing tables or routing tags

Definitions

• the present invention relates to the provision of multicasting or broadcasting capability within a fast packet switched (FPS), asynchronous transfer mode (ATM) or similar communications network.
• FPS fast packet switched
• ATM asynchronous transfer mode
• BACKC3RCXJND in the course of switching packetised data, it is often desirable to enable a single data stream comprising one or more packets to be sent to more than one address. This is known as multicasting. If all destinations are addressed, it is termed a broadcast.
• One means of providing such a facility is to simply insert many packets into the switch inputs, each addressed to a desired output but carrying the same data. This creates a large demand on switching capacity for what is, essentially, one data stream.
• the present invention comprises a packet switching network comprising switching means having a plurality of inputs and a plurality of outputs, and port control means associated with each output and with each input, wherein packets comprise a header including an address, and a payload, characterised in that each header further comprises a type indicator, such that each packet having a first type indicator is switched to a one of said outputs defined by the address portion, and is then communicated directly to the port control means associated with the addressed output, and each packet having a second type indicator is switched to a single one of said outputs, and is then communicated via a separate communications connection to one or more of said port control means.
• the present invention comprises a method of multicasting within a packet switching network, said network comprising switching means having a plurality of inputs and outputs, port control means associated with each output, and means for communicating independent of said switching means connecting a defined output of said switching means and a plurality of said port control means, said packets comprising a header including a type indicator and an address, and a payload, wherein packets having a unicast type indicator are switched by said switching means to an output defined by the respective address and then to the respective port control means, and packets having a multicast type indicator are switched by said switching means to said defined output and communicated via said means for communicating to a set of output port control means defined by the respective address.
• Figure 1 is a schematic block diagram of one embodiment of the inventive arrangement
• Figure 2 shows one suitable packet format for the inventive arrangement
• FIG. 3 illustrates in block form an output switch port controller.
• this illustrates a 4-port system 10 capable of switching 4 inputs to any of 4 outputs, via switching Fabric unit (SFU) 20.
• SFU switching Fabric unit
• the exact switching fabric implementation except in so far as it must be capable of the functions defined below, is not an essential element of the invention.
• a 4-port unit is illustrated only from the point of view of simplicity: practical switching units generally involve at least 16 x 16 units, and may be of much greater complexity, indeed, the present invention becomes more advantageous as complexity is increased.
• SFU 20 has 4 ports 0 - 3, each with an associated switch port controller (SPC) 300 - 303.
• SPC's provide an interface between various data formats and the packetised data switched by SFU 20.
• the SFU 20 is adapted to switch fixed- length packets, although the present invention is also applicable to variable length packets.
• SPC's 300 - 303 also control the input and output packet flows to and from SFU 20.
• Each SPC according to this embodiment of the invention has at least 2 connections to the SFU 20: a multicast address connection, and a unicast address connection. The exception is SPC 300, in which these connections may share the same physical connection.
• SPC's 301 - 303 are connected to unicast addressed ports by connections 25, and to multicast output from the switch by connections 28.
• Each packet comprises a payload 12 and header 13, the header including a tag bit indicating whether the packet has a unicast or multicast address (U/M), and an address field.
• U/M unicast or multicast address
• SPC's 300 - 303 generate a header 13 for each incoming packet as described so as to facilitate switching according to the present invention.
• This header 13 is generated by reference to a look-up table and the existing header and address of the external packet.
• the table includes instructions as to whether header 13 should have a unicast or multicast tag bit.
• the meaning of the address depends upon the setting of the U/M bit. If the U/M bit indicates unicast, the address is the binary value of the destination switch port. In the multicast case each bit of the address will indicate that a particular switch port is addressed.
• a packet with a U/M tag indicating unicast address of 2 is input by SPC to SFU 20, where it is switched to port 2, to the unicast port of SPC 302, and then outputs.
• a packet with a U/M tag indicating a multicast address in which bits 0 and 2 are set is input by an SPC to SFU 20. All packets with a multicast address tag are switched by SFU to port 0, and presented by multicast connection 28 to the multicast ports of each SPC. Each SPC 300 - 303 sees the packet on the multicast connection 28 and reads it in only if there is a match between the number of the SPC and a bit set in the multicast address. SPC's 300 and 302 therefore read in the packet and send it to their respective outputs.
• SPC 300 is preferably chosen to be a port having comparatively low levels of traffic, as it receives any packets which are unicast to it, and the link between port 0 and SPC 300 additionally carries all multicast addressed traffic. SPC 300 only reads packets unicast to it or packets with a multicast address in which bit 0 is set.
• FIG 3 illustrates the output part of an SPC, such as SPC 301 : what we may term the output switch port controller (OSPC) 30, as it handles packets output by SFU 20 from a port.
• OSPC output switch port controller
• FIFO 40 receives unicast addressed packets over the unicast connection 25 from a port of SFU 20.
• FIFO 41 receives multicast addressed packets via multicast connections 28 from port 0.
• connections 25 and 28 are joined at the input to the OSPC 30.
• Each packet arriving at FIFO 40 is forwarded to comparator 44 which checks that the packet contains a write address which matches the SPC number contained in register 45. If so, the input is accepted and sent to the corresponding output.
• Each packet arriving at FIFO 41 is forwarded to comparator 42, which checks that the packet contains a multicast address, and that there is a match between the bit specified in register 43 as designating that port and the corresponding address bit.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Data Exchanges In Wide-Area Networks (AREA)
• Electronic Switches (AREA)
• Prostheses (AREA)
• Media Introduction/Drainage Providing Device (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=3775139

Family Applications (1)

Country Status (6)

Cited By (3)

Families Citing this family (2)

Citations (4)

Family Cites Families (2)

• 1991
  • 1991-12-11 EP EP92900538A patent/EP0561888A1/en not_active Withdrawn
  • 1991-12-11 WO PCT/AU1991/000574 patent/WO1992010898A1/en not_active Ceased
  • 1991-12-11 JP JP4501606A patent/JPH07505262A/ja active Pending
  • 1991-12-11 CA CA002098110A patent/CA2098110A1/en not_active Abandoned
  • 1991-12-11 AU AU90711/91A patent/AU9071191A/en not_active Abandoned
• 1993
  • 1993-06-11 KR KR937001783A patent/KR930703775A/ko not_active Withdrawn

Patent Citations (4)

Non-Patent Citations (1)

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