WO1992010851A1 - Twin-tub fabrication method - Google Patents
Twin-tub fabrication method Download PDFInfo
- Publication number
- WO1992010851A1 WO1992010851A1 PCT/CA1991/000441 CA9100441W WO9210851A1 WO 1992010851 A1 WO1992010851 A1 WO 1992010851A1 CA 9100441 W CA9100441 W CA 9100441W WO 9210851 A1 WO9210851 A1 WO 9210851A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- conductivity type
- impurity
- oxide layer
- tubs
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930701761A KR930703698A (en) | 1990-12-12 | 1991-12-11 | Tub pair manufacturing method |
JP4501624A JPH06503445A (en) | 1990-12-12 | 1991-12-11 | Twin tab formation method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA2,032,073 | 1990-12-12 | ||
CA002032073A CA2032073A1 (en) | 1990-12-12 | 1990-12-12 | Twin-tub fabrication method |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1992010851A1 true WO1992010851A1 (en) | 1992-06-25 |
Family
ID=4146636
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CA1991/000441 WO1992010851A1 (en) | 1990-12-12 | 1991-12-11 | Twin-tub fabrication method |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0561909A1 (en) |
JP (1) | JPH06503445A (en) |
KR (1) | KR930703698A (en) |
CA (1) | CA2032073A1 (en) |
WO (1) | WO1992010851A1 (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4435896A (en) * | 1981-12-07 | 1984-03-13 | Bell Telephone Laboratories, Incorporated | Method for fabricating complementary field effect transistor devices |
EP0135163A1 (en) * | 1983-08-26 | 1985-03-27 | Siemens Aktiengesellschaft | Method of producing highly integrated complementary circuits of MOS field effect transistors |
WO1985004984A1 (en) * | 1984-04-17 | 1985-11-07 | American Telephone & Telegraph Company | Cmos integrated circuit technology |
EP0178440A2 (en) * | 1984-10-15 | 1986-04-23 | International Business Machines Corporation | Process of making dual well CMOS semiconductor structure |
EP0181501A2 (en) * | 1984-10-18 | 1986-05-21 | Matsushita Electronics Corporation | Method for making complementary MOS integrated circuit |
-
1990
- 1990-12-12 CA CA002032073A patent/CA2032073A1/en not_active Abandoned
-
1991
- 1991-12-11 WO PCT/CA1991/000441 patent/WO1992010851A1/en not_active Application Discontinuation
- 1991-12-11 JP JP4501624A patent/JPH06503445A/en active Pending
- 1991-12-11 KR KR1019930701761A patent/KR930703698A/en active IP Right Grant
- 1991-12-11 EP EP92900803A patent/EP0561909A1/en not_active Ceased
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4435896A (en) * | 1981-12-07 | 1984-03-13 | Bell Telephone Laboratories, Incorporated | Method for fabricating complementary field effect transistor devices |
EP0135163A1 (en) * | 1983-08-26 | 1985-03-27 | Siemens Aktiengesellschaft | Method of producing highly integrated complementary circuits of MOS field effect transistors |
WO1985004984A1 (en) * | 1984-04-17 | 1985-11-07 | American Telephone & Telegraph Company | Cmos integrated circuit technology |
EP0178440A2 (en) * | 1984-10-15 | 1986-04-23 | International Business Machines Corporation | Process of making dual well CMOS semiconductor structure |
EP0181501A2 (en) * | 1984-10-18 | 1986-05-21 | Matsushita Electronics Corporation | Method for making complementary MOS integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
CA2032073A1 (en) | 1992-06-13 |
KR930703698A (en) | 1993-11-30 |
EP0561909A1 (en) | 1993-09-29 |
JPH06503445A (en) | 1994-04-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4554726A (en) | CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well | |
US4272880A (en) | MOS/SOS Process | |
US4382827A (en) | Silicon nitride S/D ion implant mask in CMOS device fabrication | |
US4209349A (en) | Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching | |
US6362038B1 (en) | Low and high voltage CMOS devices and process for fabricating same | |
US4761384A (en) | Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing | |
US4717683A (en) | CMOS process | |
US4697332A (en) | Method of making tri-well CMOS by self-aligned process | |
US6069054A (en) | Method for forming isolation regions subsequent to gate formation and structure thereof | |
US4575925A (en) | Method for fabricating a SOI type semiconductor device | |
JPH0754825B2 (en) | Partial dielectric isolation semiconductor device | |
JPH05347383A (en) | Manufacture of integrated circuit | |
JPH0697665B2 (en) | Method of manufacturing integrated circuit structure | |
US4808555A (en) | Multiple step formation of conductive material layers | |
JP2929419B2 (en) | Method for manufacturing semiconductor device | |
KR100189739B1 (en) | Method of forming well for semiconductor wafer | |
GB2111305A (en) | Method of forming ion implanted regions self-aligned with overlying insulating layer portions | |
US5001081A (en) | Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide | |
US4535529A (en) | Method of making semiconductor devices by forming an impurity adjusted epitaxial layer over out diffused buried layers having different lateral conductivity types | |
JP3165118B2 (en) | Semiconductor device | |
US5179031A (en) | Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide | |
US4586243A (en) | Method for more uniformly spacing features in a semiconductor monolithic integrated circuit | |
KR930004125B1 (en) | Semiconductor isolation manufacture method | |
WO1992010851A1 (en) | Twin-tub fabrication method | |
EP0182876B1 (en) | Tri-well cmos technology |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): DE GB JP KR US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FR GB GR IT LU MC NL SE |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1992900803 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1992900803 Country of ref document: EP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
WWR | Wipo information: refused in national office |
Ref document number: 1992900803 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1992900803 Country of ref document: EP |