CA2032073A1 - Twin-tub fabrication method - Google Patents
Twin-tub fabrication methodInfo
- Publication number
- CA2032073A1 CA2032073A1 CA002032073A CA2032073A CA2032073A1 CA 2032073 A1 CA2032073 A1 CA 2032073A1 CA 002032073 A CA002032073 A CA 002032073A CA 2032073 A CA2032073 A CA 2032073A CA 2032073 A1 CA2032073 A1 CA 2032073A1
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- Canada
- Prior art keywords
- substrate
- conductivity type
- impurity
- implanting
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000007943 implant Substances 0.000 claims abstract description 31
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 3
- 230000000873 masking effect Effects 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 235000012431 wafers Nutrition 0.000 description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 11
- 229910052796 boron Inorganic materials 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229920004482 WACKER® Polymers 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000035899 viability Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0191—Manufacturing their doped wells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
Landscapes
- Element Separation (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Thermistors And Varistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A method is disclosed for forming self-aligned twin tubs of opposite conductivity type in a semiconductor substrate.
The method comprises the steps of implanting an impurity of one conductivity type in said substrate, masking said substrate to expose a selected region thereof, etching said substrate in said exposed region to remove at least most of the initial implant from the substrate in said exposed region with at least most of said initial implant removed therefrom, implanting an impurity of the opposite conductivity type in said exposed region of said substrate, and thermally diffusing the implanted impurities to the required depth.
A method is disclosed for forming self-aligned twin tubs of opposite conductivity type in a semiconductor substrate.
The method comprises the steps of implanting an impurity of one conductivity type in said substrate, masking said substrate to expose a selected region thereof, etching said substrate in said exposed region to remove at least most of the initial implant from the substrate in said exposed region with at least most of said initial implant removed therefrom, implanting an impurity of the opposite conductivity type in said exposed region of said substrate, and thermally diffusing the implanted impurities to the required depth.
Description
~32~7~
This invention relates to a method of forming self-aligned lined twin tubs in a semiconductor substrate.
CMOS technology has been wid(ely adopted in very large scale integrated circuits, in part due to its low power characteristics, which allow very high component densities to be achieved, especially using two micron technology. In the classic CMOS process, an n channel transistor is formed in a p tub, which is diffused into a moderately doped n-substrate, in which an associated P channel transistor is to be formed.
The doping level of the p tub must approximately an order of magnitude greater than the doping level of the n substrate to provide an adequate degree of control. As the scale of the technology decreases, the doping in the n substrate must be increased to support the voltage in the shorter channel length p channel transistors, and consequently the p tub doping must be raised proportionately. This results in the n channel transistor suffering from excessive source/drain to p tub capacitance.
The twin-tub CMOS process was designed to overcome these problems in small scale processes by providing separately optimized tubs and hence a lower capacitance n channel transistor than could be obtained with the classic process.
In the twin-tub process, a pair of tubs of opposite conductivity type, in which the p channel and n channel transistors are ultimately formed, are first formed in the silicon substrate. In the conventional process, first the silicon substrate is covered with a thin oxide layer, on which in turn is deposited a nitride layer. A photoresist layer is then deposited on the nitride layer, exposed, and developed to mask a portion of the nitride layer over one of the regions that is to form one of the tubs. Through the window in the mask, the exposed nitride layer and underlying oxide layer are etched away to expose the surface of the silicon substrate.
This invention relates to a method of forming self-aligned lined twin tubs in a semiconductor substrate.
CMOS technology has been wid(ely adopted in very large scale integrated circuits, in part due to its low power characteristics, which allow very high component densities to be achieved, especially using two micron technology. In the classic CMOS process, an n channel transistor is formed in a p tub, which is diffused into a moderately doped n-substrate, in which an associated P channel transistor is to be formed.
The doping level of the p tub must approximately an order of magnitude greater than the doping level of the n substrate to provide an adequate degree of control. As the scale of the technology decreases, the doping in the n substrate must be increased to support the voltage in the shorter channel length p channel transistors, and consequently the p tub doping must be raised proportionately. This results in the n channel transistor suffering from excessive source/drain to p tub capacitance.
The twin-tub CMOS process was designed to overcome these problems in small scale processes by providing separately optimized tubs and hence a lower capacitance n channel transistor than could be obtained with the classic process.
In the twin-tub process, a pair of tubs of opposite conductivity type, in which the p channel and n channel transistors are ultimately formed, are first formed in the silicon substrate. In the conventional process, first the silicon substrate is covered with a thin oxide layer, on which in turn is deposited a nitride layer. A photoresist layer is then deposited on the nitride layer, exposed, and developed to mask a portion of the nitride layer over one of the regions that is to form one of the tubs. Through the window in the mask, the exposed nitride layer and underlying oxide layer are etched away to expose the surface of the silicon substrate.
2~3207~
A first ion implantation of one conductivity type is performed into the exposed substrate. A thick thermal oxidation layer is then formed over the implanted substrate and the remaining photoresist layer stripped away. Next, the remaining nitride is stripped from the thin oxide layer overlying the region that is to form a second tub, and a second implantation is performed through the exposed thin oxide layer into the underlying substrate. The implanted impurities are then thermally diffused to the required depth to form the p and n type tubs respectively.
A problem with this method is that it is relatively complicated, time-consuming to carry out and furthermore has a tendency to introduce crystal defects into the substrate.
An object of the invention is therefore to alleviate the aforementioned disadvantages of the conventional process.
According to the present invention there is provided a method of forming self-aligned twin tubs of opposite conductivity type in a semiconductor substrate. The method comprises the steps of implanting an impurity of one conductivity type in said substrate, masking said substrate to expose a selected region thereof, etching said substrate in said exposed region to remove at least most of the initial implant from the substrate in said exposed region with at least most of said initial implant removed therefrom, implanting an impurity of the opposite conductivity type in said exposed region of said substrate, and thermally diffusing the implanted impurities to the required depth.
By selectively removing the initial implant from the region that is to form the second tub, the method according to the invention becomes considerably shorter and simpler than the method according to the prior art, and furthermore it has been found that it leads to significantly fewer crystal defects than were found in the prior art method.
20320~3 Preferably, the substrate is of silicon and the thin oxide layer is formed on the substrate prior to implanting the impurity of one conductivity type, for example n type.
In this case, the n type impurity is implanted through the thin oxide layer. However, if the rapid thermal oxidation method is used to grow very thin initial oxide, the thin oxide layer can be formed after the initial implant of the n type impurity, the latter occurring on the bare silicon.
The mask is applied by conventional techniques. A
photoresist layer is first deposited, exposed through a photo mask, and subsequently developed. After developing, windows are formed in the exposed regions of the photomask, through which the etch can subsequently be formed. If the initial oxide is thick enough, the photoresist can be stripped from the substrate prior to performing the second implantation of the other conductivity type.
The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:-Figures la to lc illustrate diagrammatically a conventional process for forming twin tubs;
Figures 2a to 2c show diagrammatically a process for forming twin tubs in accordance with the invention; and Figures 3a to 3j are maps showing the sheet resistance of various experimental wafers.
In the conventional process as shown in Figures la to lc, a thin silicon dioxide (SiO2) layer 2 is grown or deposited on silicon substrate i. A Silicon nitride (Si3N4) layer 3 is deposited on the thin oxide layer 2. The two layers are then covered in a photoresist layer (not shown) which is exposed and developed to form a window exposing 2~32073 surface region 4 of the substrate 1.
An n type ion implantation is performed into the exposedportion 4 to form an implanted zone 5 underneath the surface of the exposed substrate region 4 and in the silicon nitride layer 3.
A thick thermal oxidation on the exposed region 4 is performed to form thermal oxidation layer 6. Subsequently the residual nitride layer 5 is stripped from the substrate.
A p type ion implantation, for example with boron, is then performed to form p type zone 7 underneath the thin oxide layer 2 and in the thermal oxidation layer 6. The implanted impurities are thermally diffused to form the respective p type and n type tubs 8 and 9 with a uniform overlying oxide layer 10. The upper level of the thick oxide layer, which lS contains the boron 7, is removed.
As can be seen, this process requires a substantial number of steps. It also suffers from the disadvantage that it is liable to cause crystal defects in the substrate.
In the process according to the invention, a thin oxide layer 2 is thermally grown on the silicon substrate 1. A
first n type implantation is performed over the whole of the surface of the substrate through the thin oxide layer 2. A
photoresist layer is deposited on the thin oxide layer, exposed and developed to form a window region 4 over the part of the substrate that is to become the n tub. The oxide layer 2 and the surface region of the substrate containing at least most of the n type implant 5 is etched away, and a subsequent p type implant is performed to produce p type zone 5 as shown in Figure 2b. Finally, the two remaining implanted zones are thermally diffused to form p and n tubs 8 and 9 overlaid by thin oxide layer 2.
The described process requires fewer steps than the 203207~
prior art process while maintaining an accurate self alignment with two micron technology.
If a rapid thermal oxidation process is used to grow the thin oxide layer 2, the first two steps may be reversed. The initial p type implant can be performed on bare silicon, and the thinner oxide layer grown subsequently.
If the initial thin oxide layer 2 is made thick enough, the photoresist layer 11 can be stripped prior to the second implantation of the n type conductivity impurity. In this case, the initial thin oxide layer 2 will serve as the mask for the second implantation.
Examples of twin tub wafers made in accordance with the inventive process will now be given.
Polished slices of silicon wafer were processed according to the twin tub method based on Mitel Corporation,s CS220A 2 micron process from initial oxidation to p well diffusion. The silicon etch depth was varied by varying the silicon etch time, and the spreading resistance profile and four point probe mapping were used to investigate how much of the initial implant was removed with the silicon etch.
The processing was carried out as follows: All slices were 100 mm diameter, SEMI standard prime polished, and oriented as supplied by Wacker Siltronics. The n type slices had a resistivity of 10 to 15 ohm centimeter and the p type had a resistivity 32.34 to 36.74 ohm centimeter. The initial oxidation was carried out under standard CS2Q0 A conditions (approximately 30 minutes at 950 degrees C.) to give an oxidation layer of approximately 200 Angstroms thick. The initial implant was carried out by ion implantation with 1.9 E 12 phosphorus singly charged at 40 kv through the 200 Angstrom initial oxide layer.
2~32~73 The mask was formed on the pattern wafers using the DH
18 test structure with positive resist. The silicon etch process was identical to the CS200A process, except the etch time was varied as follows:
Si depth target Etch time Angstroms min.
1000 0.28 1500 0.41 2000 0.55 The p well implant was 1.9 E 12 boron, singly charged at 50 kv (standard CsZOOA process). The p well diffusion was then carried out under standard conditions for the CS200A
process (400 minutes in pure oxygen at 1175 degrees C.).
In order to confirm the viability of the process, the silicon etch step was measured with a DEKTAK (trade mark) surface profilometer at the wafer centre in accordance with CSA200A process requirements. The sheet resistance was mapped with a prometrix four probe system on blank wafers at 49 points per wafer and 6 mm. edge exclusion. The result~ were a~ follow~:
SILICON ETCH DEPTH
Si depth target Etch time (t) Actual Sl average Ang~trom~ min depth (D) Angstromc 1000 0.28 1168 1500 0.41 1589 2000 0.55 2135 D = a + bt a = 149, b = 3586 and r = 0.9986 (~orrelation coefficient).
2~3207~
SHEET RESISTANCE MAPPING
Wafer Simulated Nominal Sheet re~istance # Structure Si etch Mean (M) Stdev (S) Depth ~D) Ang~troms KOhm/~q % of mean 01 Actual ~well 1168 90.09 36.57 02 Actual Pwell 1168 94.21 35.17 03 Actual Pwell 1589 29.81 14.35 04 Actual Pwell 1589 30.54 14.85 05 Actual Pwell 2135 22.32 6.16 06 Actual Pwell 2135 23.21 6.54 07 Ideal Pwell Infinite 16.45 1.30 08 Ideal Pwell Infinite 16.64 1.23 On all the actual P well ~tructures, au uhown in Figure~ 3a to 3j, the cheet re~istance pattern wa~ characterized by an almo~t perfectly radial ~ymmetry, with a qtrong negative radial gradient (i.e. reRi~tance higher at the centre than at the edge). Thece obcervation~ correlate with an actual etch rate lower at the centre than at the edge.
For the actual P well ~tructurec:
Log(S) = a = bD, where (with the Rame unit~ a~ above) a = 2.43, b = -7.722E-04 and r = -0.9948 (correlation coefficient).
Extrapolating thi~ curve to S - 1.3~ (value for the ideal P well), a depth of 2750 Angctrom~ i~ obtained. Thic cugge~t~ that the LSL for thi~ procesn ~hould be about 2750 Ang~trom~ at the wafer centre.
, ' ' , 2032~73 NET CARRIER PROFILE
Wafer Simulated Nominal Pwell junction # Structure Si etchDepth Sheet Angstroms um resistivity ROhm/gq 01C Actual Pwell 1168 2.55 155.91 01E Actual Pwell 1168 2.70 136.36 03C Actual Pwell 1589 3.45 29.55 03E Actual Pwell 1589 3.60 26.03 05C Actual Pwell 2135 3.75 20.45 05E Actual Pwell 2135 3.75 19.98 07C Ideal Pwell Infinite 4.05 14.36 The above results and observations prove that the implanted ~pecies was indeed partially removed from the selectively etched silicon areas.
They also show that the etch was too shallow to make the residual implant dose negligible. The self-aligned twin-tub process based on an N-well technology therefore requires the optimization of the following parameters, which can be determined by experiment in each case:
P/P+ epitaxial silicon wafer~
Epi layer thickness and resistivity affect~ Latch-up, ESD, electrical parameters Substrate re~istivity affects Latch-up, ESD
Initial oxide thickness If the oxide layer i9 too thin, poor substrate protection against photore~ist contamination during strip results. Too thick an oxide layer mask~ too much of the initial implant Initial Boron Implant energy and do~e 2~32~7~
Too low energy cau~e~ poor transmisaion through the initial oxide, whereas too high energy cau~es the implant dose to reach too deep in the silicon to be removed efficiently by the Si etch N-well phosphorus implant energy and dose The implant dose affect3 the electrical parameters Silicon etch depth Too ~hallow etch depth results in poor removal of the initial Boron implant. Too deep etch depth results in photo or step coverage problems.
Uniformity and repeatability are critical: a non-contact step measurement system i~ probably nece~sary for monitoring (some commercial apparatus based on a dynamic laser focusing are available).
N-well phosphorus implant energy & dose:
Dose and energy affect electrical parameters.
N-well diffu~ion Cycle temperature, duration and atmosphere affect electrical parameters, ~ubstrate boron outdiffusion.
If the technology is n-well, the subatrate must be p-type, which mean~ that the inLtial implant ~hould al~o be P-type. The implanted impurity would therefor normally be Boron, which ~ince it is a very light element penetrate~ deeper into the silicon than heavier elements such as pho~phorua (n-type dopant) for the same implant energy. The standard implant energy for Mitel's CS200A proce~s for the Boron Pwell implant is 50Kev.
qince the shallower the implant, the shallowes the silicon etch required to remove it, experiments were performed to determine how low the initial boron implant energy could be before the uniformity of the p-well sheet re~istivity wa~ degraded. Also if n-well diffusion is carried out in pure oxygen, as sis the case in the CS200A process, a considerable _ 9 _ ~03207~
fraction of boron become~ incorporated in the oxide during the diffusion cycle.
Two expsrimental lots were made, each with 6 n-type 10-15 ohm-cm poliqhed slice~. The wafer~ were proce~ed through initial oxidation (200~), a boron implant at l.9E12/cm2, and a ~hort p-well diffu~ion for two hundred minutes in pure oxygen at 1175~C. The oxide layer (about 3500A) wa~ ~tripped and the ~heet resi~tivity mapped as described above.
The re~ult~ were a~ follow~:
Lot Wafer Implant Sheet recistance ST dev.
# # Energy Mean KOhm/~q % of Mean T979 01 50 15.97 0.81 T979 02 50 15.94 0.89 T979 03 50 16.00 0.83 T981 01 50 15.66 1.11 T981 02 50 15.49 1.16 T981 03 50 15.43 1.27 Mean 50 15.75 1.01 Stdev 0 0.25 0.l9 T979 04 25 16.36 0.88 T979 05 25 16.25 0.94 T979 06 25 n/a nla T981 04 25 15.25 0.68 T981 05 25 15.49 0.88 T981 06 25 15.43 1.06 Mean 25 15.85 0.89 Stdev 0 0.25 0.13
A first ion implantation of one conductivity type is performed into the exposed substrate. A thick thermal oxidation layer is then formed over the implanted substrate and the remaining photoresist layer stripped away. Next, the remaining nitride is stripped from the thin oxide layer overlying the region that is to form a second tub, and a second implantation is performed through the exposed thin oxide layer into the underlying substrate. The implanted impurities are then thermally diffused to the required depth to form the p and n type tubs respectively.
A problem with this method is that it is relatively complicated, time-consuming to carry out and furthermore has a tendency to introduce crystal defects into the substrate.
An object of the invention is therefore to alleviate the aforementioned disadvantages of the conventional process.
According to the present invention there is provided a method of forming self-aligned twin tubs of opposite conductivity type in a semiconductor substrate. The method comprises the steps of implanting an impurity of one conductivity type in said substrate, masking said substrate to expose a selected region thereof, etching said substrate in said exposed region to remove at least most of the initial implant from the substrate in said exposed region with at least most of said initial implant removed therefrom, implanting an impurity of the opposite conductivity type in said exposed region of said substrate, and thermally diffusing the implanted impurities to the required depth.
By selectively removing the initial implant from the region that is to form the second tub, the method according to the invention becomes considerably shorter and simpler than the method according to the prior art, and furthermore it has been found that it leads to significantly fewer crystal defects than were found in the prior art method.
20320~3 Preferably, the substrate is of silicon and the thin oxide layer is formed on the substrate prior to implanting the impurity of one conductivity type, for example n type.
In this case, the n type impurity is implanted through the thin oxide layer. However, if the rapid thermal oxidation method is used to grow very thin initial oxide, the thin oxide layer can be formed after the initial implant of the n type impurity, the latter occurring on the bare silicon.
The mask is applied by conventional techniques. A
photoresist layer is first deposited, exposed through a photo mask, and subsequently developed. After developing, windows are formed in the exposed regions of the photomask, through which the etch can subsequently be formed. If the initial oxide is thick enough, the photoresist can be stripped from the substrate prior to performing the second implantation of the other conductivity type.
The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:-Figures la to lc illustrate diagrammatically a conventional process for forming twin tubs;
Figures 2a to 2c show diagrammatically a process for forming twin tubs in accordance with the invention; and Figures 3a to 3j are maps showing the sheet resistance of various experimental wafers.
In the conventional process as shown in Figures la to lc, a thin silicon dioxide (SiO2) layer 2 is grown or deposited on silicon substrate i. A Silicon nitride (Si3N4) layer 3 is deposited on the thin oxide layer 2. The two layers are then covered in a photoresist layer (not shown) which is exposed and developed to form a window exposing 2~32073 surface region 4 of the substrate 1.
An n type ion implantation is performed into the exposedportion 4 to form an implanted zone 5 underneath the surface of the exposed substrate region 4 and in the silicon nitride layer 3.
A thick thermal oxidation on the exposed region 4 is performed to form thermal oxidation layer 6. Subsequently the residual nitride layer 5 is stripped from the substrate.
A p type ion implantation, for example with boron, is then performed to form p type zone 7 underneath the thin oxide layer 2 and in the thermal oxidation layer 6. The implanted impurities are thermally diffused to form the respective p type and n type tubs 8 and 9 with a uniform overlying oxide layer 10. The upper level of the thick oxide layer, which lS contains the boron 7, is removed.
As can be seen, this process requires a substantial number of steps. It also suffers from the disadvantage that it is liable to cause crystal defects in the substrate.
In the process according to the invention, a thin oxide layer 2 is thermally grown on the silicon substrate 1. A
first n type implantation is performed over the whole of the surface of the substrate through the thin oxide layer 2. A
photoresist layer is deposited on the thin oxide layer, exposed and developed to form a window region 4 over the part of the substrate that is to become the n tub. The oxide layer 2 and the surface region of the substrate containing at least most of the n type implant 5 is etched away, and a subsequent p type implant is performed to produce p type zone 5 as shown in Figure 2b. Finally, the two remaining implanted zones are thermally diffused to form p and n tubs 8 and 9 overlaid by thin oxide layer 2.
The described process requires fewer steps than the 203207~
prior art process while maintaining an accurate self alignment with two micron technology.
If a rapid thermal oxidation process is used to grow the thin oxide layer 2, the first two steps may be reversed. The initial p type implant can be performed on bare silicon, and the thinner oxide layer grown subsequently.
If the initial thin oxide layer 2 is made thick enough, the photoresist layer 11 can be stripped prior to the second implantation of the n type conductivity impurity. In this case, the initial thin oxide layer 2 will serve as the mask for the second implantation.
Examples of twin tub wafers made in accordance with the inventive process will now be given.
Polished slices of silicon wafer were processed according to the twin tub method based on Mitel Corporation,s CS220A 2 micron process from initial oxidation to p well diffusion. The silicon etch depth was varied by varying the silicon etch time, and the spreading resistance profile and four point probe mapping were used to investigate how much of the initial implant was removed with the silicon etch.
The processing was carried out as follows: All slices were 100 mm diameter, SEMI standard prime polished, and oriented as supplied by Wacker Siltronics. The n type slices had a resistivity of 10 to 15 ohm centimeter and the p type had a resistivity 32.34 to 36.74 ohm centimeter. The initial oxidation was carried out under standard CS2Q0 A conditions (approximately 30 minutes at 950 degrees C.) to give an oxidation layer of approximately 200 Angstroms thick. The initial implant was carried out by ion implantation with 1.9 E 12 phosphorus singly charged at 40 kv through the 200 Angstrom initial oxide layer.
2~32~73 The mask was formed on the pattern wafers using the DH
18 test structure with positive resist. The silicon etch process was identical to the CS200A process, except the etch time was varied as follows:
Si depth target Etch time Angstroms min.
1000 0.28 1500 0.41 2000 0.55 The p well implant was 1.9 E 12 boron, singly charged at 50 kv (standard CsZOOA process). The p well diffusion was then carried out under standard conditions for the CS200A
process (400 minutes in pure oxygen at 1175 degrees C.).
In order to confirm the viability of the process, the silicon etch step was measured with a DEKTAK (trade mark) surface profilometer at the wafer centre in accordance with CSA200A process requirements. The sheet resistance was mapped with a prometrix four probe system on blank wafers at 49 points per wafer and 6 mm. edge exclusion. The result~ were a~ follow~:
SILICON ETCH DEPTH
Si depth target Etch time (t) Actual Sl average Ang~trom~ min depth (D) Angstromc 1000 0.28 1168 1500 0.41 1589 2000 0.55 2135 D = a + bt a = 149, b = 3586 and r = 0.9986 (~orrelation coefficient).
2~3207~
SHEET RESISTANCE MAPPING
Wafer Simulated Nominal Sheet re~istance # Structure Si etch Mean (M) Stdev (S) Depth ~D) Ang~troms KOhm/~q % of mean 01 Actual ~well 1168 90.09 36.57 02 Actual Pwell 1168 94.21 35.17 03 Actual Pwell 1589 29.81 14.35 04 Actual Pwell 1589 30.54 14.85 05 Actual Pwell 2135 22.32 6.16 06 Actual Pwell 2135 23.21 6.54 07 Ideal Pwell Infinite 16.45 1.30 08 Ideal Pwell Infinite 16.64 1.23 On all the actual P well ~tructures, au uhown in Figure~ 3a to 3j, the cheet re~istance pattern wa~ characterized by an almo~t perfectly radial ~ymmetry, with a qtrong negative radial gradient (i.e. reRi~tance higher at the centre than at the edge). Thece obcervation~ correlate with an actual etch rate lower at the centre than at the edge.
For the actual P well ~tructurec:
Log(S) = a = bD, where (with the Rame unit~ a~ above) a = 2.43, b = -7.722E-04 and r = -0.9948 (correlation coefficient).
Extrapolating thi~ curve to S - 1.3~ (value for the ideal P well), a depth of 2750 Angctrom~ i~ obtained. Thic cugge~t~ that the LSL for thi~ procesn ~hould be about 2750 Ang~trom~ at the wafer centre.
, ' ' , 2032~73 NET CARRIER PROFILE
Wafer Simulated Nominal Pwell junction # Structure Si etchDepth Sheet Angstroms um resistivity ROhm/gq 01C Actual Pwell 1168 2.55 155.91 01E Actual Pwell 1168 2.70 136.36 03C Actual Pwell 1589 3.45 29.55 03E Actual Pwell 1589 3.60 26.03 05C Actual Pwell 2135 3.75 20.45 05E Actual Pwell 2135 3.75 19.98 07C Ideal Pwell Infinite 4.05 14.36 The above results and observations prove that the implanted ~pecies was indeed partially removed from the selectively etched silicon areas.
They also show that the etch was too shallow to make the residual implant dose negligible. The self-aligned twin-tub process based on an N-well technology therefore requires the optimization of the following parameters, which can be determined by experiment in each case:
P/P+ epitaxial silicon wafer~
Epi layer thickness and resistivity affect~ Latch-up, ESD, electrical parameters Substrate re~istivity affects Latch-up, ESD
Initial oxide thickness If the oxide layer i9 too thin, poor substrate protection against photore~ist contamination during strip results. Too thick an oxide layer mask~ too much of the initial implant Initial Boron Implant energy and do~e 2~32~7~
Too low energy cau~e~ poor transmisaion through the initial oxide, whereas too high energy cau~es the implant dose to reach too deep in the silicon to be removed efficiently by the Si etch N-well phosphorus implant energy and dose The implant dose affect3 the electrical parameters Silicon etch depth Too ~hallow etch depth results in poor removal of the initial Boron implant. Too deep etch depth results in photo or step coverage problems.
Uniformity and repeatability are critical: a non-contact step measurement system i~ probably nece~sary for monitoring (some commercial apparatus based on a dynamic laser focusing are available).
N-well phosphorus implant energy & dose:
Dose and energy affect electrical parameters.
N-well diffu~ion Cycle temperature, duration and atmosphere affect electrical parameters, ~ubstrate boron outdiffusion.
If the technology is n-well, the subatrate must be p-type, which mean~ that the inLtial implant ~hould al~o be P-type. The implanted impurity would therefor normally be Boron, which ~ince it is a very light element penetrate~ deeper into the silicon than heavier elements such as pho~phorua (n-type dopant) for the same implant energy. The standard implant energy for Mitel's CS200A proce~s for the Boron Pwell implant is 50Kev.
qince the shallower the implant, the shallowes the silicon etch required to remove it, experiments were performed to determine how low the initial boron implant energy could be before the uniformity of the p-well sheet re~istivity wa~ degraded. Also if n-well diffusion is carried out in pure oxygen, as sis the case in the CS200A process, a considerable _ 9 _ ~03207~
fraction of boron become~ incorporated in the oxide during the diffusion cycle.
Two expsrimental lots were made, each with 6 n-type 10-15 ohm-cm poliqhed slice~. The wafer~ were proce~ed through initial oxidation (200~), a boron implant at l.9E12/cm2, and a ~hort p-well diffu~ion for two hundred minutes in pure oxygen at 1175~C. The oxide layer (about 3500A) wa~ ~tripped and the ~heet resi~tivity mapped as described above.
The re~ult~ were a~ follow~:
Lot Wafer Implant Sheet recistance ST dev.
# # Energy Mean KOhm/~q % of Mean T979 01 50 15.97 0.81 T979 02 50 15.94 0.89 T979 03 50 16.00 0.83 T981 01 50 15.66 1.11 T981 02 50 15.49 1.16 T981 03 50 15.43 1.27 Mean 50 15.75 1.01 Stdev 0 0.25 0.l9 T979 04 25 16.36 0.88 T979 05 25 16.25 0.94 T979 06 25 n/a nla T981 04 25 15.25 0.68 T981 05 25 15.49 0.88 T981 06 25 15.43 1.06 Mean 25 15.85 0.89 Stdev 0 0.25 0.13
Claims (7)
1. In a method of forming self-aligned twin tubs of opposite conductivity type in a semiconductor substrate, the improvement wherein the method comprises the steps of implanting an impurity of one conductivity type in said substrate, masking said substrate to expose a selected region thereof, etching said substrate in said exposed region to remove at least most of the initial implant from the substrate in said exposed region with at least most of said initial implant removed therefrom, implanting an impurity of the opposite conductivity type in said exposed region of said substrate, and thermally diffusing the implanted impurities to the required depth.
2. A method as claimed in claim 1, wherein a thin oxide layer is formed on said substrate prior to implanting said impurity of one conductivity type, and said impurity of one conductivity type is implanted therethrough.
3. A method as claimed in claim 1, wherein a thin oxide layer is formed on said substrate subsequent to implanting said impurity of said one conductivity type.
4. A method as claimed in claim 1, wherein said thin has a thickness sufficient to mask said substrate alone during implantation of said impurity of said second conductivity type, and said mask is removed prior to implanting said impurity of said other conductivity type.
5. A method as claimed in claim 1, wherein said thin oxide layer is formed by rapid thermal oxidation.
6. A method as claimed in claim 1, wherein said method employs a 2µ fabrication process.
7. A method as claimed in claim 1, wherein the silicon is etched to a depth of about 1,000 to 2,500 A to remove most of the initial impurity implant in the exposed region.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002032073A CA2032073A1 (en) | 1990-12-12 | 1990-12-12 | Twin-tub fabrication method |
| JP4501624A JPH06503445A (en) | 1990-12-12 | 1991-12-11 | Twin tab formation method |
| KR1019930701761A KR930703698A (en) | 1990-12-12 | 1991-12-11 | Tub pair manufacturing method |
| PCT/CA1991/000441 WO1992010851A1 (en) | 1990-12-12 | 1991-12-11 | Twin-tub fabrication method |
| EP92900803A EP0561909A1 (en) | 1990-12-12 | 1991-12-11 | Twin-tub fabrication method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002032073A CA2032073A1 (en) | 1990-12-12 | 1990-12-12 | Twin-tub fabrication method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2032073A1 true CA2032073A1 (en) | 1992-06-13 |
Family
ID=4146636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002032073A Abandoned CA2032073A1 (en) | 1990-12-12 | 1990-12-12 | Twin-tub fabrication method |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0561909A1 (en) |
| JP (1) | JPH06503445A (en) |
| KR (1) | KR930703698A (en) |
| CA (1) | CA2032073A1 (en) |
| WO (1) | WO1992010851A1 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4435896A (en) * | 1981-12-07 | 1984-03-13 | Bell Telephone Laboratories, Incorporated | Method for fabricating complementary field effect transistor devices |
| DE3330851A1 (en) * | 1983-08-26 | 1985-03-14 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING HIGHLY INTEGRATED COMPLEMENTARY MOS FIELD EFFECT TRANSISTOR CIRCUITS |
| US4554726A (en) * | 1984-04-17 | 1985-11-26 | At&T Bell Laboratories | CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well |
| US4558508A (en) * | 1984-10-15 | 1985-12-17 | International Business Machines Corporation | Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step |
| JPS6197859A (en) * | 1984-10-18 | 1986-05-16 | Matsushita Electronics Corp | Manufacturing method of complementary MOS integrated circuit |
-
1990
- 1990-12-12 CA CA002032073A patent/CA2032073A1/en not_active Abandoned
-
1991
- 1991-12-11 KR KR1019930701761A patent/KR930703698A/en not_active Abandoned
- 1991-12-11 EP EP92900803A patent/EP0561909A1/en not_active Ceased
- 1991-12-11 JP JP4501624A patent/JPH06503445A/en active Pending
- 1991-12-11 WO PCT/CA1991/000441 patent/WO1992010851A1/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| EP0561909A1 (en) | 1993-09-29 |
| KR930703698A (en) | 1993-11-30 |
| JPH06503445A (en) | 1994-04-14 |
| WO1992010851A1 (en) | 1992-06-25 |
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| Date | Code | Title | Description |
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| FZDE | Discontinued |