WO1992007352A1

WO1992007352A1 - Control circuit for matrix-type readout devices and signal decoder for such circuit

Info

Publication number: WO1992007352A1
Application number: PCT/FR1991/000822
Authority: WO
Inventors: Léopold Albert HARWOOD; Dora Plus
Original assignee: Thomson S.A.
Priority date: 1990-10-19
Filing date: 1991-10-18
Publication date: 1992-04-30

Abstract

A system for applying brightness signals to the columns of a display device having a display cell-matrix arranged in columns and in rows comprises a comparator for each display cell column. Each comparator receives a brightness signal and a reference ramp signal. When the brightness signal is greater than the reference ramp, the output is at one logic level. As the display cell is charged, and when the reference ramp attains the level of the brightness signal, the output of the comparator goes to the other logic level and the associated display cell no longer receives a charge.

Description

The present invention relates to control circuits for display devices of the matrix type and also to a digital decoder for such a control circuit.

Many display devices, such as liquid crystal displays, consist of a matrix of pixels arranged horizontally in rows and vertically in columns. The data to be displayed is applied in the form of brightness signals to data lines which are individually associated with each of the pixel columns. The rows of pixels are scanned sequentially and the pixels within the activated row are loaded at different levels of gray scale depending on the levels of the brightness signals applied to each column. In a color liquid crystal display, each pixel is composed of at least three pixel elements which emit one of the three primary colors of light, red, green or blue. In an active matrix display, each pixel element is composed of a liquid crystal which is associated with a switching device making it possible to activate or deactivate each of the liquid crystal cells. Typically, the switching device is a semiconductor device such as a thin film transistor (TFT) and receives video information, or lumina informaion of a set of signal processing circuits which is typically also a set of semiconductor circuits. All the control circuits for the liquid crystal display cells must be able to charge all the display cells to the voltage levels necessary for the desired brightness, and this within the time available to generate a frame. image. A color television display can have 250,000 to 750,000 liquid crystal cells and it is a daunting task to charge such a quantity of liquid crystal cells in the available frame time. A control circuit for a liquid crystal display is described in US Patents Nos. 4,766,430 and 4,742,346. The system described in these patents uses the voltages representative of the desired brightness levels to preset counters to different count values which represent brightness levels. An analog ramp is applied sequentially to the horizontal selection lines and all the liquid crystal cells inside the selected horizontal line, which are associated with a pass-through transfer gate, are loaded simultaneously by the analog ramp. The counters make the transfer doors pass or block them so that the level at which the cells liquid crystal are charged, is determined by the count values preset in the counters. When a counter counts to zero or to its pre-selected count value, the transfer door associated with it is blocked and the liquid crystal cell is charged at the brightness level depending on the count value preset in the counter. This system is satisfactory for the goal to be achieved, but it has drawbacks because the meters consist of bulky and complex logic gates which require a large area on the substrate on which the circuit assembly is made. The aim sought in the industry is to manufacture the set of control circuits around the periphery of the substrate which carries the liquid crystal cells and their associated transfer gates. The area required for meters is therefore a major drawback. The operating speed is also one of the drawbacks of the counter technique, in particular when the transfer doors and the circuit assembly are made of amorphous silicon, whose low carrier mobility makes it extremely difficult to carry out all the processing operations. of signals in the available horizontal temp-line which is 60 microseconds. For these reasons, there is a need for a control circuit which eliminates the need for meters, which lowers costs. and the area required for all the control circuits and which can be used with all technologies, including polycrystalline silicon and low mobility amorphous silicon technologies. The present invention meets this need.

A system for applying different voltage levels of a data ramp to individual columns of display cells in a display device having an array of display cells arranged in columns and in rows has a plurality of transfer means of signals arranged to apply the data ramp voltage individually to the columns of display cells. A plurality of comparator means pass and block said signal transfer means individually so that the data ramp is applied to the display cells when the transfer doors are passing. A reference ramp generator applies a reference ramp to the voltage comparators. A data voltage is also applied to the comparator. The comparator makes the transfer gates passable when the data voltage exceeds the reference ramp and blocks said transfer gates when the reference ramp reaches the data voltage.

The present invention can be used with that described in the PCT application filed at the same date, having as inventors Dora Plus and Leopold A. Harwood, entitled "System for applying luminosity signals to a display and comparator for such a system" and claiming priority from US application No. 600,046.

FIG. 1 represents a preferred embodiment of a control circuit for a liquid crystal display.

FIG. 2 represents a preferred embodiment of a digital comparator circuit intended to be used in the preferred embodiment of FIG. 1.

In FIG. 1, a set of analog circuits 11 receives an analog information signal representative of the data to be displayed coming from an antenna 12. When the input signal is a television video signal, the set of analog circuits 11 resembles that of a conventional television of known type. The set of analog circuits 11 provides a signal carrying analog data on a line 13 as the input signal of an analog-digital converter (A / D) 14. When the input signal is intended to be used with a graphic display on computer, it is probably already digital, and the A / D converter 14 can be eliminated.

The television signal from all of the analog circuits 11 is intended to be displayed on a liquid crystal array 16 consisting of a large number of liquid crystal cells, such as the liquid crystal cell 16a, arranged horizontally in rows and vertically in columns. In a color display having a gray scale capability, each pixel has at least three liquid crystal cells 16a, one for each of the three primary colors of light. In such a display, each of the liquid crystal cells is typically called "pixel element": and thus, the terms "liquid crystal cells" and "pixel element" as they are used in this document are interchangeable. The liquid crystal network 16 comprises several data lines 17, one for each of the vertical columns of liquid crystal cells 16a, and several selection lines 18, one for each of the horizontal rows of liquid crystal cells. The A / D converter 14 includes an output bus 19 for supplying brightness levels, or gray scale codes, to digital storage means 21 having several output lines 22. The output lines 22 of the storage means digital 21 apply the voltages to the data lines in column 17 for the columns of the liquid crystal cells 16a via latching circuits 23, comparators 24 and transfer gates 26. Each of the output lines 22 therefore provides the level of voltage which is applied to the liquid crystal cell 16a in a given column when an associated transfer gate 26 is on, and this as a function of the scanning of the selection lines 18. A preferred embodiment of the digital storage means 21 under the form of a shift register is described in US Patents Nos. 4,766,430 and 4,742,346, the lessons of which are incorporated into the present application. A reference ramp generator 33 provides a reference ramp to m comparators 24. In the preferred embodiment shown, the reference ramp generator 33 is digital and provides a plurality of digital words which individually represent different voltage levels. The use of a digital ramp requires the use of digital comparators. When using an analog comparator, the comparators 24 are also analog. The number n of bits in the digital words determines the number of gray scale levels. In other words, the number of gray scale levels n is 2. The digital words are provided on an output line 27 which is coupled across a line 32 to the comparator 24 for each of the columns of liquid crystal cells. A data ramp generator 34 provides an analog data ramp to the columns of liquid crystal cells by connecting an output line 28 to each of the transfer doors 26. In the preferred embodiment shown, the transfer doors 26 are thin film transistors, the gate electrodes of which are individually coupled to the output lines 29 of the comparators 24.

During operation, the digitized brightness signals coming from the digital storage means 21 are applied by output lines 22 to the latch circuits 23, the outputs of which are connected to an input of a comparator 24 by an output line 31 The reference ramp generator 33 provides a reference ramp to the other input of each of the comparators 24. While the reference ramp is applied to the comparators 24, the data ramp is applied to the transfer gates 26. The time delay and the possible delays of the reference ramp and of the data ramp are a function of the technology used, and are within the reach of those skilled in the art. All data lines are set high early in the line time period. When the brightness signal from the locking circuit 23 is greater than the voltage of the reference ramp, the output line 29 of the comparator 24 remains at the high level and the transfer gate 26 remains on. The data ramp on line 28 of the data ramp generator 34 is therefore applied to the liquid crystal cells in the activated row of liquid crystal cells to charge the cells. liquid crystal. All the cells of the activated row which are associated with the pass-through transfer doors 26 are, therefore, loaded simultaneously. When the level of the reference ramp voltage reaches the level of the brightness signal coming from the locking circuit 23, the output line 29 of the comparator 24 goes to low level and blocks the associated transfer gate 26. The liquid crystal cell associated with the blocked transfer door is therefore charged at the level established by the brightness signal coming from the associated locking circuit 23.

In FIG. 2, the comparator 24 is digital and includes a plurality of logic gates 36 to 41 which, in the preferred embodiment shown, are exclusive NOR gates (XNOR). Each of the gates 36 to 41 receives an input signal from a digital ramp generator 33a and another input signal from a latch circuit 23. The latch circuits 23 are multi-bit circuits and provide a bit for each of the XNOR gates 36 to 41. Each bit of the digital ramp signal coming from the digital generator 33a is compared with the corresponding bit of the data input received from the digital storage circuit 21 (FIG. 1). The output terminals of the XNOR doors 36 to 41 are applied to an OR gate 42, the output terminal of which is coupled to a locking circuit 43 which can be reset. The output of the locking circuit 43 is connected to the control electrode of a transfer gate 26 by the line 29. Therefore, when at least one of the bits of the digital ramp coming from the digital ramp generator 33 is different from the corresponding bit of the data word coming from the locking circuits 23, the logic output level of one of the XNOR gates is high, the output level of the OR gate 42 is therefore also high, and the gate of associated transfer 26 is maintained in the state passing through the locking circuit 43. In this condition, the output ramp from the analog data ramp generator 34 available on line 28 is applied to the liquid crystal cell 16a of the associated column of liquid crystal cells through the transfer gate 26 and across the line 17. When all the bits from the digital ramp generator 33 are matched to the corresponding data bits of the word d onnées applied by the locking circuits 23, the logic levels of the outputs of the XNOR gate are low and the output of the OR gate 42 goes low. The locking circuit 43 then puts the line 29 at the low level and blocks the associated transfer door 26. The analog ramp coming from the data ramp generator 34 is then no longer applied to the liquid crystal cell 16a of the associated column. of crystals liquids. As a result, the level at which the liquid crystal cell 16a is charged is determined by the adjustment of the locking circuits 23 as a function of the data input provided by the digital storage mechanism 21. The locking circuit is returned to the high level early in the next row-time to make transfer doors 26 passable again. In the preferred embodiment shown, six-bit digital words are used and, therefore, the comparator 24 includes six logic circuits (XNOR gates), and 64 gray scale levels are available. In the case where 256 gray scale levels have to be used, these can be obtained simply by using eight-bit digital words, and eight XNOR gates in the comparator 24.

Claims

1. System for applying different voltage levels of a data ramp to the individual columns of display cells in a display device having a matrix of display cells arranged in columns and in rows, characterized in that it comprises:

- a plurality of signal transfer means arranged to activate said columns individually to apply said data ramp individually to said display cells;

- A plurality of comparator means associated individually with said signal transfer means to turn on and to block said signal transfer means so that said data ramp is. applied to said display cells when said transfer doors are on;

- reference ramp generating means for applying a reference ramp to said comparators; and

- Means for applying said signals to said comparators, each comparator making the associated transfer gate passable when said data signal exceeds said reference ramp and blocking said transfer gate when said reference ramp reaches said data signal.

2. The system of claim 1, characterized in that said transfer means are semiconductor devices, each of said semiconductor devices having a control electrode responsive to one of said comparators to turn on and to block said semiconductor devices.

3. The system of claim 2, characterized in that said signal transfer means are thin film transistors.

4. The system of claim 3, characterized in that said thin film transistors are made of amorphous silicon.

5. The system of claim 3, characterized in that said thin film transistors are made of polycrystalline silicon.

6. Has a decoder for decoding a digital signal representative of an analog signal comprising:

- means for providing said digital signal in the form of a plurality of data bits;

- means for providing a digital ramp having a plurality of digital ramp signals, each of said digital ramp signals having a plurality of digital ramp bits equal in number to said ramp bits;

means for receiving said data bits and said digital ramp bits in parallel and for comparing said data bits with the corresponding digital ramp bits to provide an output at a logic level when said bits are comparable and an output at another logic level when said bits are not comparable.

7. The decoder of claim 6, characterized in that said receiving means comprise a plurality of logic gates, each of said logic gates individually comparing one of said data bits and one of said ramp bits.

8. The decoder of claim 6, characterized in that said logic gates are exclusive NOR gates.

9. A system for transforming digital data values composed of n bits into analog signals representative of the brightness levels for a display device having a matrix of pixel elements comprising:

- means for supplying said n-bit digital data values;

- Means for providing a digital ramp composed of a plurality of digital levels with n bits n representative of 2 analog voltage levels;

- digital comparator means for receiving said digital data values and said digital levels and supplying logic signals having a level when said digital data values and said digital levels are comparable and another level when said digital data values and said digital levels are not comparable, said comparator comprising n logic circuits for individually comparing said digital data values and said digital levels and providing said logic signals on n individual logic lines, and logic means responsive to said logic lines for providing switching signals to the individual data lines.

The system of claim 9 further comprising switchable storage means disposed between said storage means and said individual data lines.

11. The system of claim 10, characterized in that said exclusive logic gates are exclusive NOR gates.

12. The system of claim 11, characterized in that said means for supplying switching signals consist of an OR gate.

13. The system of claim 9, characterized in that it further comprises transfer doors individually sensitive to said data lines to pass through and to block said data lines selectively to couple said data lines to said pixels inside said display device, and means for providing an analog ramp to said transfer doors for charging said pixels to the levels established by said data inputs.

14. The system of claim 13, characterized in that said logic circuits are exclusive logic gates.

15. A system for applying brightness signals to the individual columns of a display device having a matrix of display cells arranged in columns and in rows, characterized in that it comprises:

- respective sources of a ramp signal of Q data and of a reference ramp signal associated with said columns;

- individual sources of said brightness signals for individually applying said brightness signals to said columns; 5 - a plurality of transfer gates individually associated with said column lines for applying said data ramp signal to said column lines; and

a plurality of comparator means for individually controlling said transfer doors, each of said comparator means being sensitive to said reference ramp signal and to one of said brightness signals to make one of said transfer doors conductive and non-conductive in function relative values of said reference ramp signal and said brightness signal.