WO1992001987A1 - Systeme d'interface autorisant le transfert de donnees vers un peripherique eloigne independamment du raccordement arriere du processeur hote - Google Patents

Systeme d'interface autorisant le transfert de donnees vers un peripherique eloigne independamment du raccordement arriere du processeur hote Download PDF

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Publication number
WO1992001987A1
WO1992001987A1 PCT/US1991/005006 US9105006W WO9201987A1 WO 1992001987 A1 WO1992001987 A1 WO 1992001987A1 US 9105006 W US9105006 W US 9105006W WO 9201987 A1 WO9201987 A1 WO 9201987A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
host
host processor
adapter
remote system
Prior art date
Application number
PCT/US1991/005006
Other languages
English (en)
Inventor
Daryl B. Elam
Original Assignee
Tekstar Systems Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tekstar Systems Corporation filed Critical Tekstar Systems Corporation
Publication of WO1992001987A1 publication Critical patent/WO1992001987A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G06F9/3881—Arrangements for communication of instructions and data

Definitions

  • the invention relates to a means and method for bypassing standard computer interface backplanes in order to increase the data transfer rate between the host computer and a remote system.
  • PCs personal computers
  • the backplane bus bandwidth is the most significant factor in restricting the usefulness of high-speed add-in system components which require use of the backplane to communicate with a system central processing unit (CPU) .
  • Such components are most efficient when data transfer can be accomplished at the data transfer rate of the CPU rather than at the transfer rate of the backplane.
  • the bandwidth limitations are most pronounced when there is a large discrepancy between the peak data transfer rate capabilities of the system CPU and the backplane bus. Over the years, this discrepancy has become greater and greater, as new generations of new CPUs are introduced far more often than new generations of backplane buses. As CPU capability and speed increase, the backplane becomes the limiting factor in using the CPU with add-in systems to perform more complex tasks.
  • the present invention is intended to permit a wide variety of add-in systems to operate at a high data transfer rate by bypassing the backplane of the host processor without the requirement that the add-in system be physically located on the CPU board.
  • the invention takes advantage of the availability of the functional signals connected to and available at sockets generally provided in the standard CPU board.
  • the invention uses the available sockets to permit development of a communications interface to shunt around the backplane bus.
  • An adapter and data processing logic are connected to a selected data access point to provide a data transfer path for connecting the host CPU with the add-in systems.
  • the data transfer rate can be increased by a factor approaching a magnitude over the capability of the backplane.
  • the present invention comprises a means and method for circumventing the limitations of the data communications speed of standard computer interface buses.
  • the backplane bus restricts the usefulness of a certain class of add-in system components, generally in the form of add-in circuit boards, which use the backplane bus to communicate with the system CPU. This class is characterized primarily by the desirability to tranfer data to and/or from the system CPU as quickly and efficiently as possible.
  • the invention utilizes the standardization of the signal connections in the system CPU and/or other peripheral sockets in the CPU board as a convenient location to access the required signals and shunt around the system backplane bus.
  • the interface includes dedicated interface logic which duplicates the protocol and accessing schemes of the host CPU or the f displaced ' chip. ' This permits direct communication between the host CPU and the adapter circuitry without the use of the displaced chip " .
  • the adapter provides a hard wired system which electrically connects the required signals available at the selected data access point to a remote add-in system to provide a high speed data transfer bus.
  • the only additional electrical connections required other than those available at the selected socket may be the DC power and ground lines which can be taken directly from the standard backplane.
  • the standard PC backplane known as an Industry Standard Architecture (ISA) backplane, or alternatively, as the IBM PC-AT bus, provides a data path which is 16 parallel bits, the maximum recommended backplane clock speed being 8 megahertz (MHz) .
  • the fastest backplane transfers require 4 clock cycles, yielding a peak bandwidth of 4 megabytes per second.
  • Using the present invention with a 33 MHz clock speed requires the same 4 clock cycles per transfer as is standard.
  • the invention yields a data transfer rate of 33 megabytes per second, an over 8-fold improvement.
  • an Intel 80386 microprocessor is used.
  • the invention may be adapted to interface with most available microprocessors, numeric chips and other generally available sockets or access points, provided the CPU provides at the socket all signals required by the add-in board.
  • the adapters may be stacked or "piggy-backed" on top of one another to permit multiple add-in boards simultaneously utilizing the same socket.
  • the particular function of the add-in system is incidental to the invention as long as the signals required to operate the add-in system are available at the adapter socket.
  • Fig. 1 is a general block diagram of a host processor in combination with a special purpose high ⁇ speed function peripheral add-in and an interface unit incorporating the teachings of the present invention.
  • Fig. 2 is a detailed flow chart of the interface device illustrated in Fig. 1.
  • Fig. 3 is a diagram of a typical (prior art) state machine which may be an integral part of the interface device shown in Figs. 1 and 2.
  • Figs. 4-13 are a schematic diagram of a data transfer interface device made in accordance with the teachings of the present invention.
  • the present invention includes an adapter 20 and a data transfer device or circuit 50.
  • the CPU of a standard PC such as, by way of example, an IBM PC-AT compatible system having an Intel 80386 microprocessor 30, includes a standard memory interface 32 and main PC memory 34, typical onboard interfaces 36 and typical onboard peripherals 38.
  • a standard system backplane interface 40 is used to provide communication between the CPU 30 and the backplane 42 for providing data transfer to and from the add-in cards 44.
  • the PC will include numerous peripheral sockets such as, by way of example, the extended math chip (EMC) socket 46 adapted for receiving a standard numerics chip 48 such as, by way of example, the Weitek 3167 or the Intel 80387 math chip.
  • EMC extended math chip
  • the math chip interface logic circuitry 49 is also provided to control communication between the PC and the math chip.
  • the subject invention is specifically adapted for connecting the CPU 30 to special purpose high-speed function (SPHSF) add-in systems 60, bypassing the system backplane 42 by utilizing the direct connections to the full speed CPU signals via the math chip socket 46.
  • SPHSF high-speed function
  • the math chip socket of the CPU is a convenient place to gain access to the signals needed for the high-speed direct interface.
  • the adapter could also be placed directly on the CPU chip or at any other convenient location on the main CPU circuit board where direct " access to the required CPU signals can be gained.
  • adapter 20 includes a math chip socket adapter 22 which is connected directly to the math chip socket via a standard plug and socket arrangement which is designed to mate with the math chip socket 46 provided in the PC.
  • the adapter provides a direct communication link between the math chip socket and the data transfer device 50.
  • the adapter can physically be plug compatible with the math chip socket and coupled to ribbon cables or the like which are, in turn, in direct communication with the data transfer device 50.
  • the math chip 48 may be plug compatible with the adapter.
  • the math chip interface logic 24 may be located on the adapter 20 or may be remote and coupled via the cable.
  • the protocol and accessing schemes provided in the math chip is preserved in one of three alternative methods when in utilizing the present invention.
  • the math chip 48 is simply removed from the math chip socket and reinserted in the math chip socket adapter 22 in parallel with the data h t transfer logic device 50, whereby the PC continues to communicate directly with the math chip and the adapter "picks off" the signals in a passive or non-invasive manner and transmits them to the data transfer circuit 50.
  • the math chip interface signal emulation logic circuit 24 emulates the accessing and signal protocol scheme of the math chip to duplicate those of the math chip, whereby the CPU communicates with the adapter as if it were a math chip.
  • the math chip is only emulated to the degree necessary to permit communication with the CPU. The system has distinct interface characteristics, only emulating as much as necessary of the math chip to permit communication.
  • the physical configuration of the socket adapter is not critical to the function of the invention except for the requirement that the pin and socket arrangement of the adapter must be compatible with the selected data access point on the CPU board.
  • the adapter may be a structural part of the special purpose circuit board including the math chip interface signal emulation logic 24 and the data transfer logic 50, or it may be remote from the board and connected to it by using cables.
  • the SPHSF 60 may be plugged directly into the adapter and/or data transfer board or may be plugged into a socket which then communicates via cable with the data transfer board.
  • the signals to be transmitted from the host CPU 30 to the SPHSF 60 are communicated to the data transfer device 50 via the adapter 20.
  • the signals to be transmitted from the SPHSF 60 to the CPU 30 are communicated to the data transfer device 50 directly from the SPHSF 60.
  • Data exchange buffers 54 receive the data at the rate it is generated and supply it to the receiving processor on demand at the rate it can be used. This permits use of asynchronous CPUs and SPHSF
  • the data exchange interface logic device 56 provides interfacing and control logic for controlling the buffer function in response to the CPU 20 and SPHSF 60.
  • FIG. 2 An expanded diagram of the data exchange circuitry 50 is illustrated in Fig. 2. As there shown, three primary communication paths exist between the adapter 20 and the data exchange circuitry 50. The first is a host PC data bus 25 which directly links the CPU signals present at the math socket with the exchange circuitry 50.
  • the host PC control bus 26 provides a path for communication of the various control signals between the CPU 30 and data exchange interface logic 56.
  • PC address bus 27 and "selected" signal line 28 provide for the address and selection signals to be transmitted between the PC and the data exchange circuitry via adapter 20.
  • the data transfer and control signals between the data exchange circuit 50 and the SPHSF 60 are provided at buses 51 and 52 and 33, respectively.
  • the data transfer rate is at the respective processing rate of the SPHSF 60 and the host CPU 30.
  • DTR data transfer rate
  • R the bus clock rate in megahertz
  • W the width of the data bus in bits
  • L the loss due to refresh
  • the invention provides an increase in data transfer rate of
  • the data exchange circuit 50 operates as a buffer for storing data produced by the host CPU 30 and the SPHSF 60.
  • the buffers 54 collect information as quickly as it is produced and release it on demand, as needed.
  • the interface logic 56 monitors the SPHSF 60 and the buffers 54 to determine when the buffers are ready to receive data and when the buffers have data available to transfer relative to the SPHSF.
  • the host CPU interface logic 57 communicates with the math chip socket adapter and through it with the host CPU 30 to similary monitor and determine when the buffers are ready to receive and/or transfer data relative to the host CPU.
  • the preferred embodiment employs two FIFO registers 100, 102.
  • the FIFO 100 receives data from the host CPU 30 via the adapter 20 and makes it available to the SPHSF 60.
  • the FIFO 102 receives data from the SPHSF 60 and makes it available to the host CPU 30 via the adapter 20.
  • the dual port RAM 104 which allows both the host CPU 30 via the socket adapter 20 and/or the SPHSF 60 to read and write data autonomously and asynchronously in at random addresses.
  • the dual port RAM provides substantial flexibility in the data exchange sequence.
  • the SPHSF for example, accesses stored data at random as needed, or can "look" at data in the RAM without deleting it.
  • the host can, for example, enter and change commands in the RAM whether or not the SPHSF ever accesses or utilizes the them.
  • the FIFOs are each one-way circuits, as their name implies, and whatever data goes in, comes out in the same order.
  • the host CPU is adaptable to provide instruction codes to the programmable component via the data exchange circuitry.
  • the data exchange circuitry is operable to transfer not only operand data but instruction codes and commands, as well.
  • the data exchange circuitry In order to make the transfer scheme functional when plugged into the math chip socket, the data exchange circuitry must be able to communicate with the host CPU 30. This can be accomplished by using one of the three following methods:
  • the numerics chip may be plugged into the adapter, whereby the CPU 30 continues to communicate directly with the numerics chip and the data available at the adapter is lifted from the chip socket for use by the data exchange circuitry and the SPHSF;
  • the math chip interface signal emulation logic circuitry 24 includes logic for duplicating / 2_ the protocol and accessing schemes of the numerics chip to simulate the identity of the numerics chip, permitting the host CPU 30 to function as if it were communicating directly with a standard numerics chip; or
  • the data exchange circuitry can have a distinct identity provided that specific signals present in the math chip are handled in a manner compatible with the host CPU, i.e., the interface emulates the selected, required minimum protocol of the math chip while ignoring superfluous signals not relevant to the SPHSF.
  • Fig. 3 is the architecture for a typical state machine for the Intel 80386 microprocessor is illustrated in Fig. 3.
  • the information for creating the state machine is directly available from the Intel 80386 Users Manual.
  • the state machine logic is loaded into PLD circuits provided in the math chip CPU control logic circuitry 108.
  • the math chip CPU control logic circuit communicates directly with the host CPU 30 through the math chip socket adapter 20 and emulates protocol and accessing schemes of a numerics chip, permitting the CPU 30 to function as if it were communicating with the numerics chip.
  • the math chip CPU control logic 108 communicates directly with the math chip socket to provide emulation.
  • the address decoder is standard decoder architecture similar to that used in the numerics chip or other add-in function peripherals and provides the required handshaking signals between the peripheral and the host CPU 30.
  • the SPHSF 60 can be any special purpose high ⁇ speed functional peripheral.
  • the SPHSF may include a CPU 120 which is adapted for receiving and sending data signals to and from the host CPU 30. In the prior art systems, the SPHSF would have to communicate directly with the host processor through the standard backplane. Where the SPHSF was capable of providing high-speed functions, the system efficiency was entirely dependent upon the speed of the backplane.
  • the data exchange circuitry can receive data between the SPHSF 60 and the host CPU 30 at the speed it is generated and supply on demand, as needed.
  • the peak data transfer rate is the data utilization rate of the SPHSF.
  • the SPHSF interface logic circuit 56 in the data exchange circuitry would be customized for each specific SPHSF.
  • the SPHSF may be expandable and adapted to include additional peripherals, as illustrated by DRAM control 122 and DRAM expansion board 124.
  • the use of the data transfer scheme of the present invention permits utilization of special purpose high-speed functional add-in peripherals with stand alone computer systems, wherein the rate of data transfer between the SPHSF and the host computer is limited only by the speed at which both the host processor and the add-in peripheral generate and utilize data, rather than being limited by standard backplane architecture.
  • This permits the user to buy a relatively inexpensive PC or other microprocessor based host system and add to it the data transfer system of the present invention for substantially less investment than required to purchase a mini-computer or a mainframe, permitting performance levels at mini-computer or mainframe speeds.
  • a PC having an Intel 386 microprocessor and an SPHSF includes an Intel 80860 microprocessor numerical processing sequences can be performed at about half the rate of a CRAY-1 supercomputer at less than 1% of the cost.
  • FIG. 4-13 A detailed schematic diagram of a data transfer interface device made in accordance with the present invention is illustrated in Figs. 4-13.
  • the cable connectors provide direct access to the host CPU signals and to other useful signals which can be utilized to provide the optimum interface between the host and the add-in SPHSF.
  • the upper PLD Ul implements a state machine which tracks the state machine of the host CPU (Fig. 3) by monitoring the signals available via the cable from the adapter.
  • the upper PLD also implements the required handshaking signals according to the host CPU's required protocol for the transfer of data to and from the host.
  • the lower PLD U2 implements the control signals used to interface with the data exchange buffers and other control logic.
  • the PLD U3 implements the control logic for the exchange of data from the host CPU's side of the data exchange buffers. In this case, they control reading from and writing to FIFO and random access dual port memories. The other side of the FIFOs and dual port memories is written to or read from by the SPHSF.
  • the PAL U4 performs the same functions as the PAL U3 except that this PAL performs it's functions on behalf of the SPHSF, and thus is connected to the logically opposite side of the various buffers and control circuits.
  • the four cable connectors P4, P5, P6 and P7 carry the host CPU data bus signals to and from the host CPU socket adapter.
  • the number of buffer logic chips would simply be adjusted to the required number to match the data bus width of the host CPU.
  • the signals on the right side of Fig. 6 are the latched data bus bits from the host CPU or the unlatched data bus bits from the data exchange buffers.
  • the FIFO circuits in Fig. 7 comprise the lower 32 bits of the SPHSF data bus, which are also the even 32 bit words of the host CPU. These FIFOs pass data unidirectionally from the host to the SPHSF.
  • the FIFO circuits in Fig. 8 comprise the upper 32 bits of the SPHSF data bus, which are also the odd 32 bit words of the host CPU. These FIFOs pass data unidirectionally from the host to the SPHSF.
  • the FIFO circuits in Fig. 9 comprise the lower 32 bits of the SPHSF data bus, which are also the even 32 bit words of the host CPU. These FIFOs pass data unidirectionally from the SPHSF to the host.
  • the FIFO circuits in Fig. 10 comprise the upper 32 bits of the SPHSF data bus, which are also the odd 32 bit words of the host CPU. These FIFOs pass data unidirectionally from the SPHSF to the host.
  • the dual port RAM chips U25 and U26 in Fig. 11, and U27 and U28 in Fig. 12 are each one megabit memories organized as 64K by 16 bits and are of the fully asynchronous dual ported variety. All signals on the left sides of the chips are connected to the host CPU and/or host interface control circuitry, and vise versa, all signals on the right side are connected to the SPHSF. This provides a random access memory for applications and algorithms not well suited for the sequential nature of FIFOs.
  • the dual port RAM chips U27 and U28 in Fig. 12 are , each one megabit memories organized as 64K by 16 bits and are of the fully asynchronous dual ported variety. All signals on the left sides of the chips are connected to the host CPU and/or host interface control circuitry, and vice versa, all signals on the right side are connected to the SPHSF unit. This provides a random access memory for applications and algorithms not well suited for the sequential nature of FIFOs.
  • the SPHSF shown in Fig. 13 is shown merely as an example and is a 64 bit high speed RISC processor which is to be used primarily as an accelerator for numerical computation intensive applications.
  • the high speed interface to the host could be utilized for virtually any special function which would benefit from high data transfer rates. Examples would be mass storage controllers, signal processing sub-systems, image processors and the like.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

L'invention se rapporte à un moyen et à un procédé permettant de contourner le bus de raccordement arrière standard (40) d'un ordinateur hôte (30) pour que la transmission des données puisse s'effectuer entre l'ordinateur hôte (30) et les systèmes additionnels internes à fonctions rapides spécialisées (60). Les données sont transmises à la cadence à laquelle elles sont générées par l'ordinateur hôte (30) et le periphérique additionnel interne (60).
PCT/US1991/005006 1990-07-16 1991-07-16 Systeme d'interface autorisant le transfert de donnees vers un peripherique eloigne independamment du raccordement arriere du processeur hote WO1992001987A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US55414090A 1990-07-16 1990-07-16
US554,140 1990-07-16

Publications (1)

Publication Number Publication Date
WO1992001987A1 true WO1992001987A1 (fr) 1992-02-06

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WO (1) WO1992001987A1 (fr)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0560020A2 (fr) * 1992-03-13 1993-09-15 International Business Machines Corporation Fonction de traitement de signaux numériques ressemblant à une pile FIFO
US5655090A (en) * 1992-03-13 1997-08-05 International Business Machines Corporation Externally controlled DSP with input/output FIFOs operating asynchronously and independently of a system environment
KR970062891A (ko) * 1996-02-29 1997-09-12 다까노 야스아끼 연산 실행 방법 및 연산 실행 장치
WO1998013767A1 (fr) * 1996-09-25 1998-04-02 Advanced Micro Devices, Inc. Controleur de donnees multimedia
WO1999008195A1 (fr) * 1997-08-05 1999-02-18 Advanced Micro Devices, Inc. Tampons isochrones pour microprocesseurs equipes d'une unite multimedia
WO2005010632A2 (fr) * 2003-06-17 2005-02-03 Pact Xpp Technologies Ag Dispositif et procede de traitement de donnees
US7693257B2 (en) 2006-06-29 2010-04-06 Accuray Incorporated Treatment delivery optimization
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US8869121B2 (en) 2001-08-16 2014-10-21 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9047440B2 (en) 2000-10-06 2015-06-02 Pact Xpp Technologies Ag Logical cell array and bus system
US9075605B2 (en) 2001-03-05 2015-07-07 Pact Xpp Technologies Ag Methods and devices for treating and processing data

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US4309754A (en) * 1979-07-30 1982-01-05 International Business Machines Corp. Data interface mechanism for interfacing bit-parallel data buses of different bit width
US4591973A (en) * 1983-06-06 1986-05-27 Sperry Corporation Input/output system and method for digital computers
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US4953930A (en) * 1989-03-15 1990-09-04 Ramtech, Inc. CPU socket supporting socket-to-socket optical communications

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US4246637A (en) * 1978-06-26 1981-01-20 International Business Machines Corporation Data processor input/output controller
US4309754A (en) * 1979-07-30 1982-01-05 International Business Machines Corp. Data interface mechanism for interfacing bit-parallel data buses of different bit width
US4591973A (en) * 1983-06-06 1986-05-27 Sperry Corporation Input/output system and method for digital computers
US4860244A (en) * 1983-11-07 1989-08-22 Digital Equipment Corporation Buffer system for input/output portion of digital data processing system
US4953930A (en) * 1989-03-15 1990-09-04 Ramtech, Inc. CPU socket supporting socket-to-socket optical communications

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0560020A3 (fr) * 1992-03-13 1995-01-11 Ibm
US5655090A (en) * 1992-03-13 1997-08-05 International Business Machines Corporation Externally controlled DSP with input/output FIFOs operating asynchronously and independently of a system environment
EP0560020A2 (fr) * 1992-03-13 1993-09-15 International Business Machines Corporation Fonction de traitement de signaux numériques ressemblant à une pile FIFO
KR970062891A (ko) * 1996-02-29 1997-09-12 다까노 야스아끼 연산 실행 방법 및 연산 실행 장치
WO1998013767A1 (fr) * 1996-09-25 1998-04-02 Advanced Micro Devices, Inc. Controleur de donnees multimedia
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
USRE45223E1 (en) 1997-02-08 2014-10-28 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
USRE45109E1 (en) 1997-02-08 2014-09-02 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
US5944801A (en) * 1997-08-05 1999-08-31 Advanced Micro Devices, Inc. Isochronous buffers for MMx-equipped microprocessors
WO1999008195A1 (fr) * 1997-08-05 1999-02-18 Advanced Micro Devices, Inc. Tampons isochrones pour microprocesseurs equipes d'une unite multimedia
US9047440B2 (en) 2000-10-06 2015-06-02 Pact Xpp Technologies Ag Logical cell array and bus system
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9075605B2 (en) 2001-03-05 2015-07-07 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US8869121B2 (en) 2001-08-16 2014-10-21 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
WO2005010632A3 (fr) * 2003-06-17 2005-07-07 Pact Xpp Technologies Ag Dispositif et procede de traitement de donnees
WO2005010632A2 (fr) * 2003-06-17 2005-02-03 Pact Xpp Technologies Ag Dispositif et procede de traitement de donnees
US7693257B2 (en) 2006-06-29 2010-04-06 Accuray Incorporated Treatment delivery optimization

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