WO1991020130A1

WO1991020130A1 - Output buffer circuit

Info

Publication number: WO1991020130A1
Application number: PCT/JP1991/000816
Authority: WO
Inventors: Katsuhiro Hisaka
Original assignee: Oki Electric Industry Co., Ltd.
Priority date: 1990-06-20
Filing date: 1991-06-19
Publication date: 1991-12-26
Also published as: KR920702576A

Abstract

An output buffer circuit having output terminals, a first and a second power supply, a transistor (Tr16), connected between the first power supply and the output terminal, and a transistor (Tr11) connected between the second power supply and the output terminal, in which a control signal (n13) whose potential level is shifted gradually from the potential level of the second power supply to the one of the first power supply in the delay period of time determined by a delay circuit (14) is fed to the gate electrode of the transistor (Tr11). Thereby, an output buffer circuit which can reduce noise suppressing the lowering of its high speed performance as small as possible can be offered.

Description

Specification

Output buffer circuit

Technical field

The present invention relates to an output buffer circuit, and is particularly suitable for use in a semiconductor integrated circuit for reducing unnecessary emission radio waves.

Background art

An output buffer circuit built in a semiconductor integrated circuit is required to be able to drive a relatively large load capacitance connected to an output terminal at a high speed. However, when an output buffer circuit with a large current driving capability is driven at high speed, a large current suddenly flows through the power supply line and the ground line when the load capacity is changed. Noise is likely to be generated on the wire and the ground wire. In particular, in the semiconductor circuit, the input signal level and the output voltage judgment level are close to the ground level, so that noise on the ground line is a problem.

In order to prevent such a problem from occurring, an output buffer circuit having a mirror capacitor C between the input and output of the output inverter circuit has been proposed in Japanese Patent Application Laid-Open No. 60-62725. Proposed in the gazette.

In this output buffer circuit, high-speed operation is difficult because the function of suppressing the rise and fall of the waveform by the mirror capacitance is always effective.

Disclosure of the invention

In view of the above problems, the present invention provides an output buffer circuit that can reduce noise while minimizing degradation in high-speed performance. The primary purpose is to provide.

A _second object of the present invention is to provide an output buffer circuit that focuses on changes in transistor characteristics due to temperature, power supply, and manufacturing variations, and makes it possible to keep the output response time constant even when conditions change. It is to be.

That is, a first invention provides an output buffer circuit having an output terminal, a first power supply, and a second power supply,

A first transistor connected between the first power supply and the output terminal, wherein the first transistor electrically connects the first power supply and the output terminal during a first predetermined period; ,

A second transistor connected between the second power supply and the output terminal, the second transistor having a control terminal for controlling an electrical connection between the second power supply and the output terminal. The evening and the ''

Coupled to a control terminal of the second transistor, outputting a first control signal of a first logic level during the first predetermined period, and outputting a first control signal of a first logic level for a second predetermined period after the first predetermined period Control means for outputting a first control signal of a second logic level to

Delay means for receiving the first control signal, receiving the first control signal at the second logic level, and outputting the delayed signal at the second logic level after a predetermined delay time Delay means;

Control signal supply means for receiving the first control signal and the delay signal, and providing a second control signal to the control terminal, wherein the predetermined delay time after the first predetermined period is: The second control signal, which gradually shifts from the first logic level to the second logic level, shifts to the second logic level relatively quickly after receiving the delay signal. And a control signal supply means for supplying the control signal to the control terminal.

According to a second invention, in an output buffer circuit having an output terminal, a first power supply, and a second power supply,

A first switch connected between the first power supply and the output terminal, the first switch electrically connecting the first power supply to the output terminal during a first predetermined period; And

A first field effect transistor (FET) having a first and a second ^ electrode and a control electrode, wherein the first electrode is connected to the second power source; The second electrode is a first FE connected to the output terminal,

A second 'FE having first and second electrodes and a control electrode

T, wherein the first electrode is connected to the second electrode of the first FET and a second FET,

A capacitor connected between the second electrode of the second FET and the control electrode of the first FET;

A first control means for applying a control signal to the control electrode of the first FET during a second predetermined period after the first predetermined period;

And a second control means for applying a voltage related to the first power supply to the control electrode of the second FET during the second predetermined period. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a circuit diagram of a first embodiment of the present invention,

FIG. 2 is a waveform diagram for explaining the circuit operation of FIG. 1, FIG. 3 is a circuit diagram of a second embodiment of the present invention,

FIG. 4 is a waveform diagram for explaining the circuit operation of FIG. 3, and FIG. 5 is a circuit diagram of a modification of the second embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows an output buffer circuit according to a first embodiment of the present invention, and FIG. 2 shows a waveform diagram for explaining the operation of the circuit shown in FIG. The tri-state output circuit 11 shown in FIG. 1 responds to the output buffer control signals S 11 and S 12, and outputs a low-level signal representing logic “0” and a high-level signal representing logic “1”. The output signal S10, which is a level signal and a "high impedance" signal, is output from the output terminal 17 via the node 16 and is connected between the voltage Vcc and the ground voltage Vss. A P-channel transistor (hereinafter referred to as PMOS) having a drain connected in common via a node 16 and an N-channel transistor for discharging output load capacitance ( Hereinafter, it is called NM NM S.) Tr 11 is connected to the it column.

A switch circuit 12 and a capacitor C 10 are connected in series between the gate of NMQSTr 11 of the tri-state output circuit 11 and the node 16.

The switch circuit 12 is configured by connecting two transistors Tr 12 and Tr 13 in parallel, and controls the on / off control of these transistors Tr 12 and Tr 13. Inver evening This is done in circuit 13. In the first embodiment, a delay circuit 14 in which four stages of inverters are connected in series is connected between the switch circuit 12 and the inverter circuit 13 and a transistor is connected. The polarity of these transistors is made different by using PM〇S for the transistor Tr12 and NM〇S for the transistor Tr13. The transistor Tr 12 is controlled by the output signal node n 11 of the delay circuit 14, and the output of the delay circuit 14 is inverted by the inverter circuit 15. The transistor Tr 13 is controlled by the generated signal node n 12.

Further, a fourth transistor Tr14 having the same polarity as that of the third transistor Tr13 is connected in parallel with the capacitor C10, and this transistor Tr14 is connected to the transistor Tr10. It is controlled by the output signal node n 1 1 of the ray circuit 14. In addition, a resistor R 1 ί) is connected between the inverter circuit 13 and the power supply, and a MOS transistor Tr having a polarity different from that of the third transistor Tr 13. 15 is connected in parallel with the resistor R10, and the on / off of this transistor Tr15 is controlled by the same node n12 as that of the third transistor Tr13. ing.

In the output buffer circuit of the first embodiment configured as described above, the input signal S 11 applied to the human electrode of the inverter circuit 13 at the time t 0 as shown in FIG. The output signal node n 13 of the inverter circuit 13 rises from the ground level to the power level as shown in FIG. Go on. At this time, Since both the fourth transistor Tr14 and the fifth transistor Tr15 are off, the rise time of the node n13 is determined by the resistor R10 and the capacitor C10. As a result, the power E of the node n 13 slowly rises as shown in FIG. 2B.

At time t1 when a predetermined delay time set in the delay line 14 has passed, at time t1, as shown in FIGS. 2C and D, the node n 1 2 force The node η 11 rises from a low level to a high level as the level falls. As a result, at time t2, the switch circuit 12 is turned off, the capacitor C10 is disconnected from the output circuit, and the transistors Tr14, Tr15 are respectively turned on, and the resistance The upper and lower ends of the capacitor R10 and the capacitor C0 are short-circuited respectively. '

As a result, the mirror integration effect due to the action of the resistor R 10 and the capacitor C 10 was canceled, and the output signal S 10 was discharged at a stroke after the time t 2 as shown in FIG. 2E. It will be. That is, in the case of the output buffer circuit of the first embodiment, the discharge of the output load capacitance is gradually performed only during the delay time set by the delay circuit 14, and the output voltage is changed to the intermediate voltage. After that, the battery must be discharged at once. As a result, the peak current IV ss 10 flowing through the output transistor Tr 11 of the tri-state output circuit 11 can be dispersed, so that noise to the ground line can be reliably reduced. Supine And the speed sacrifices can be minimized.

By the way, in the above-mentioned embodiment, the fourth transistor Tr 14 is provided, and when the switch circuit 12 is turned off, the capacitor C 10 is short-circuited. This is to prevent n 14 from exceeding the gate level of the second transistor Tr 12, and by doing so, Tr 12 and Tr 13 It is possible to configure the switch circuit 12 using such a MOS transistor.

In the first embodiment, the present invention can be similarly applied to the power supply side described only when the present invention is applied to the transistor on the ground side.

As described above, in the first embodiment of the present invention, a series circuit composed of a capacitance component and a switch circuit is provided between an input terminal and an output terminal of a transistor for a transistor provided in a circuit of an output stage. In addition to connecting the circuit, a delay circuit that operates the switch circuit after a predetermined time has elapsed is provided, and the switch circuit is turned off when a predetermined time has elapsed since the start of the operation. As a result, the capacitance component is separated from the discharge transistor, so that when the output is at a high level and the current consumption is large, the integration function can be used to reduce the gradient of the current change, and The load capacity can be discharged at a stretch after the output has dropped to an intermediate level, thereby suppressing unnecessary radiation and noise and achieving high-speed operation. Both Make it possible. Therefore, it is possible to provide an integrated circuit that can be used in an environment in which unnecessary radiation waves are regulated or in a device that performs high-density mounting without impairing its high-speed operation.

FIG. 3 is an output buffer circuit diagram showing a second embodiment of the present invention. An input terminal is an input of an inverter 31 for receiving an output buffer control signal S30. The output of the receiver 31 is input to the inverter 32, and its output (node n33) is connected to the gates of the discharge circuit transistors Tr32 and Tr33 of the output circuit. This transistor drives Tr32 and Tr33. On the other hand, the charge-up transistor Tr 31 is controlled by the output buffer control signal S 31.

Between the nodes n32 and n33, there are NMOS transistors connected in parallel, Tr34 and Tr35, and the quantity components

C 30 is connected in series, and the gate of Tr 34 is an inverted signal of the output of the inverter 31, and the power supply level is one n V t (in the figure, V cc — 2 V t, n is the number of stages of the load MOS transistor Tr37, and Vt is the level of the transistor Tr37 threshold). The gate of Tr 35 is

-Connected to node n32, the forward diode from node n32. In addition, an NM0S transistor Tr36 is connected between the power supply line Vcc and C30, and the output power of the inverter 31 is applied to the gate of the transistor Tr36. .

As shown in FIG. 4, first, at time t 0, the input terminal When the slave receives the signal S 30 at the “Low” level, the node n 33 becomes “L” and the output discharge transistor Tr 32, Tr 33 Is OFF and I

V s s 30 does not flow. At this time, the node n32 enters the fining state, and its level can be between 1 Vt and ∞. Therefore, the voltage rise is suppressed by the transistor Tr35 and the node 1134 Is set to the threshold Vt of the load MOS transistor Tr38, the node n32 does not become a negative voltage. At time t0, Tr36 is ON, and the capacitance component C30 is charged.

Next, when the input terminal ④ receives the signal S 30 that has changed to the “H” level, the node n 34 changes from V t to V c c— 2

V t rises, Tr 34 becomes 0 N state, Tr 36 becomes 0 FF, Tr 32 and Tr 33 become ◦N state, and the force flowing through IV ss 30 becomes At this time, the rise time of the node n33 is a value integrated by the action of the CN0 and the N3 resistor RTr34 of Tr34. As shown by the solid line in FIG. 4, when the power supply voltage V cc is a high voltage, for example, 5.5 V, the resistance of RT r 34 is low, and the mirror effect of C 30 is large. Become. On the other hand, when the supply voltage Vcc becomes low (5 V), RTr34 changes to high resistance, and the mirror integration effect decreases. Therefore, when the supply voltage is low and the influence of noise is small, the peak current IV ss30 is dispersed only at the high supply voltage where noise is likely to occur without sacrificing speed. Noise can be suppressed efficiently. Also, if the transistor threshold value Vt fluctuates due to manufacturing variations, if Vt is high, node n34 will be much lower than the supply voltage, and as a result RTr34 will be large. Therefore, the output response time is not delayed due to the reduction of the mirror effect, while when the Vt is low, the mirror effect becomes large and excessive high-speed switching is suppressed.

In addition, even when the output response time changes due to temperature dependence, at high temperatures, the mirror effect is reduced due to the decrease in the current driving force gm of Tr 34, and the delay in speed can be suppressed. it can. At low temperatures, the gm of Tr34 is improved, and the efficiency of the mirror effect is also improved, so that excessive high-speed switching can be suppressed.

As described above, according to the second embodiment of the present invention, when discharging the output load capacitance, the mirror is normally used only when the high voltage, the low temperature, and the low Vi at which the peak current is maximized. The effect is used, and the mirror effect is kept small in other cases, so that noise can be suppressed without sacrificing speed.

Also, as shown in Fig. 3, by using two stages of discharge transistors, Tr32 and Tr33, the effect of output load is made invisible, so that the mirror effect can be used efficiently. can do.

In the second embodiment, only the case where the present invention is applied to the transistors Tr32 and Tr33 on the ground side has been described above, but as shown in FIG. The same applies to the transistor Tr 31 on the power supply side. can do.

Industrial applicability

As described above in detail, according to the present invention, it is possible to provide an output buffer circuit capable of reducing noise while minimizing a decrease in high-speed performance.

Claims

The scope of the claims

In an output buffer circuit having an output terminal, a first power supply, and a second power supply,

A first transistor connected between the first power supply and the output terminal, wherein the first transistor electrically connects the first power supply to the output terminal for a first predetermined period; Evening and

A second transistor connected between the second power supply and the output terminal, the second transistor having a control terminal for controlling an electrical connection between the second power supply and the output terminal;

Coupled to a control terminal of the second transistor, outputs a first control signal of a first logic level during the first predetermined period, and outputs a first control signal of a first logic level during a second predetermined period after the first predetermined period; A control means for outputting a first control signal having a logic level of 2;

Delay means for receiving the first control signal, the delay means for receiving the first control signal of the second logic level, and outputting the delayed signal of the second logic level after a predetermined delay time Means,

A control signal supply means for receiving the first control signal and the delay signal and providing a second control signal to the control terminal, wherein the predetermined delay time after the first predetermined period is Changing the second control signal, which gradually shifts from the first logic level to the second logic level, to the second logic level relatively quickly after receiving the delay signal; An output buffer circuit, comprising: a control signal supply unit that supplies a second control signal to be shifted to the control terminal.

2. The output buffer circuit according to claim 1, wherein the first and second transistors are field effect transistors,

The output buffer circuit, wherein the control means is an inverter circuit connected between the first power supply and the second power supply.

3. The output buffer circuit according to claim 2, wherein an output of the inverter circuit is connected to the control terminal of the second transistor via a first node, and the control signal supply unit includes: A capacitor having a first terminal connected to the first node; first switch means connected between a second terminal of the capacitor and the output terminal; Second switch means connected between the first terminal and the first node; a resistor connected between the first power supply and the inverter circuit; and a second switch connected in parallel with the resistor. The first switch means is turned off in response to the delay signal of the second logic level, and the second and third switches are turned off. Responding to the delay signal at the second logic level, Output buffer circuit characterized by the following.

4. In an output buffer circuit having an output terminal, a first power supply, and a second power supply, A first switch connected between the first power supply and the output terminal, the first switch electrically connecting the first power supply and the output terminal for a first predetermined period; J and, ',

A first field-effect transistor (FET) having first and second electrodes and a control electrode, wherein the first electrode is connected to the second power supply; The first electrode is a first FET connected to the output terminal, and a second FET having first and second electrodes and a control electrode, wherein the first electrode is the first FET of the first FET. A second FET connected to the second electrode;

A capacitor connected between the second electrode of the second FET and the control electrode of the first FET; and a control electrode of the first FET, after the first predetermined period. Providing a control signal during a second predetermined period of the first control means;

An output buffer circuit comprising: a second control means for applying a voltage related to the first power supply to the control electrode of the second FET during the second predetermined period.

5. The output buffer circuit according to claim 4, wherein a second electrode of the first FET is connected to the output terminal via a third FET, and a control electrode of the third FET. Is an output buffer 7 circuit specially designed to receive the control signal.

6. The output buffer circuit according to claim 5, wherein the second electrode of the first FET, a capacitor, and And a fourth FET connected in parallel with the second FET, wherein the fourth F Τ control electrode is connected to the second electrode of the first FET. The output buffer circuit. ,

7. The output buffer circuit according to claim 6, further comprising: a fifth FET connected between the second electrode of the second FET and the first power supply, wherein the fifth FET is connected to the first FET. The output buffer circuit, wherein the output buffer circuit is in the 0 FF state for the second predetermined period.

8. The output buffer circuit according to claim 7, wherein the fifth F pin is in an ON state during the first period.

9. The output buffer circuit according to claim 4, wherein the second control means includes: a sixth FET connected to the first power supply; and a control electrode between the sixth FET and the second FET. An output buffer circuit, comprising: a connected resistor means; and wherein the sixth FET is turned on during the second predetermined period.

10. In the output buffer circuit in the range 9 claim of claim, 'leaving the sixth FET was Toku徵to become on purpose 0 FF shape to said first predetermined period ^birch: Tsu file circuit.