WO1991015059A1

WO1991015059A1 - Ecl circuit design providing improved noise margins

Info

Publication number: WO1991015059A1
Application number: PCT/US1990/003019
Authority: WO
Inventors: Kevin L. Mclaughlin
Original assignee: Cray Research, Inc.
Priority date: 1990-03-20
Filing date: 1990-05-30
Publication date: 1991-10-03

Abstract

An 75K ECK circuit provides a VOH (output voltage high) of an 10K ECL circuit and a VOL (output voltage low) of a 100K ECL circuit. The 100K ECL VOL is relatively invariant with changes in temperature as compared to 10K ECL. The 10K ECL VOH provides an increase in noise margin between the output high voltage and the reference voltage as compared to 100K ECL. The resulting 75K ECL circuit provides a unique combination of the most desirable attributes of both 10K ECL and 100K ECL circuits.

Description

ECL CIRCUIT DESIGN PROVIDING IMPROVED NOISE MARGINS

BACKGROUND OF THE INVENTION

1. Field Of The Invention

The present invention relates generally to the field of Emitter Coupled Logic (ECL) circuits, and specifically to a 75K ECL circuit that combines the voltage output low (V_0L) and temperature stability of 100K ECL with the voltage output high (V_0H) of 10K ECL.

2. Description of Related Art

The performance of 10K ECL circuits is affected by temperature. For example, both V_0H and V_0L in 10K ECL circuits tend to change with temperature, increasing as the temperature increases. A shift in voltage transfer characteristics can be troublesome in any system, especially if each of the 10K ECL devices has a different supply voltage and temperature. If logic levels of individual devices shift by different amounts, noise margins may be reduced.

The 100K ECL circuit was designed to solve these problems. A 100K ECL circuit is similar to the 10K ECL circuit, but the V_0H and V_0L of the 100K ECL circuit are made insensitive to temperature changes by means of a simple compensation network connected between the complementary outputs of the current switch and a bias network supplying the reference voltages. Although 100K ECL resolves the temperature problems associated with 10K ECL, other problems do exist.

One problem is that the dimensions of signal traces used to interconnect ICs are shrinking. Reduced line widths result in higher resistance traces. The increased resistance causes a voltage drop between source and receiving ICs, especially in parallel-terminated transmission line systems. The voltage drop is most prevalent when the output of the source IC is at V_0H, i.e., when current is flowing from the V_0H to a termination voltage (V^,) of typically -2.0 volts through a nominally 50 ohm resistance. The voltage drop reduces the noise margin between V_0H and V_BB for the receiving IC.

Another problem is that poly-emitter IC technology- exhibits higher emitter resistance, R_E, than prior technologies. The higher R_E requires larger emitter areas to reduce the resistance and to maintain the specified V_0H levels regardless of variations due to the fabrication process. The large emitter area brings with it increased capacitance, which in turn limits the speed at which the device will operate at a given gate current.

SUMMARY OF THE INVENTION To overcome limitations in the prior art described above and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention compensates for these technological shortcomings by improving the V_0H level, that is, by allowing V_0H to become more positive. The present invention discloses a new circuit design, termed a 75K ECL circuit, wherein a compensation network comprised of resistors and diodes is connected between the complementary outputs of a current switch. The 75K ECL circuit provides a V_0L and temperature stability similar to that obtained by 100K ECL and a V_0H similar to that obtained by 10K ECL. Thus, the ECL 75K circuit provides a unique combination of the most desirable attributes of both 10K ECL and 10OK circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, where like numerals refer to like elements throughout the several views:

Figure 1 is a schematic diagram of a prior art 10K ECL current switch; Figure 2 is a schematic diagram of a prior art 10OK ECL current switch; and

Figure 3 is a schematic diagram of an ECL 75K current switch according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

A schematic diagram of a prior art 10K ECL current switch circuit is shown in Figure 1. Two transistors, 10 and 12, form the current switch. Transistor 10 is the input transistor for the current switch. Transistor 12 is the reference transistor with a reference voltage V_BB at the base thereof. When transistor 10 is conducting and transistor 12 is off, most of the current flows through resistor 20. If the temperature increases, there is an increase in current through the current switch. The voltage at the base-emitter junction of transistor 14 decreases, tending to make V_0L increase. The voltage at the base-emitter junction of transistor 16 also decreases, tending to make V_0H increase.

The 10K ECL circuit is designed so that the output voltages V_0H and V_0L are symmetrical about the reference voltage V_BB. This ensures symmetrical noise margins for the logic high and logic low states. Typically, a temperature compensation network (not shown) in the reference voltage supply provides for variations with temperature, so that the reference voltage V_BB is centered with respect to the output voltages V_0H and V_0L even with changes of temperature.

In spite of the temperature compensation network, the performance of 10K ECL circuits is affected by any increase in temperature. If each of a the 10K ECL circuits in a system of circuits has a different supply- voltage and temperature, any shifts in voltages may reduce the noise margins in the system. The 10OK ECL circuit was designed to address the problem of temperature instability.

A schematic diagram of a prior art 10OK ECL current switch circuit is shown in Figure 2. When transistor 10 is conducting and transistor 12 is off, most of the current flows through resistor 20. If the temperature increases, there is an increase in current through current source 18. The voltage at the base-emitter junction of transistor 14 decreases, tending to make V_0L increase. The voltage at the base-emitter junction of transistor 16 also decreases, tending to make V_0H increase. The 100K ECL compensation network uses the increased current through the current source 18 to decrease the voltage at the bases of both transistors 14 and 16 to compensate for the decrease in voltage at the base-emitter junctions. Thus, both V_0L and V_0H are stabilized.

The 100K ECL circuit is similar to the 10K ECL circuit, except that output voltage levels in the 10OK ECL circuit are made relatively insensitive to temperature changes by a compensation network connected between the bases of the output transistors 14 and 16. The compensation network is comprised of two diodes, 24 and 26, and resistor 28, connected between the complementary outputs of the current switch.

To accomplish the stabilization of V_0L, the change in voltage at the base of transistor 14 must adjust for the decrease in voltage to the base-emitter junction of transistor 14. When most of the current flows through resistor 20, diode 24 is forward-biased and some of the current flows through resistors 28 and 22. The resistors 20, 28 and 22 cause the voltage at the base of transistor 14 to decrease. Thus, V_0L is stabilized.

To accomplish the stabilization of V_0H, the change in voltage at the base of transistor 16 must adjust for the decrease in voltage at the base-emitter junction of transistor 16. The change in voltage at the base of transistor 16 equals the change in voltage across resistor 28 plus the change in voltage across diode 24 plus the change in voltage at the base of transistor 14. However, the change in voltage at the base of transistor 14 complements the change in voltage across the diode 24. Therefore, to compensate for changes in V_0H, the change in voltage across resistor 28 must equal and complement the change in the voltage at the base-emitter junction of transistor 16. Thus, V_0H is stabilized.

Conversely, when transistor 12 is conducting and transistor 10 is off, the same relationships apply, except that most of the current flows through resistor 22, and diode 26 is forward-biased instead of diode 24.

Further, the reference voltages V_BB and V_cs are typically supplied by a bias network (not shown) and are relatively invariant to voltage and temperature changes in V_EE. Thus, V_0H and V_0L are also invariant with regard to changes in V_EE.

While both 10K ECL and 100K circuits do provide improved thermal response, neither provide the advantages of the present invention — the 75K ECL circuit. The 75K ECL circuit is similar to both the 10K ECL and 100K ECL circuits discussed earlier, except that it provides output voltage levels comprising the most desirable aspects of both. The 75K ECL circuit provides a V_0H whose temperature response is similar to the temperature response of the V_0H of the 10K ECL circuit. The 10K ECL V_0H provides an increase in the noise margin from the reference voltage V_BB as the temperature increases. The circuit also provides a V_0L whose temperature response is similar to the temperature response of the V_0L of the 10OK ECL circuit. The 100K ECL V_0L is relatively invariant with changes in temperature and supply voltage.

Figure 3 is a schematic diagram of an 75K ECL circuit according to a preferred embodiment of the present invention. When transistor 10 is conducting and transistor 12 is off, most of the current flows through resistor 20. If the temperature increases, there is an increase in current through current source 18. The voltage at the base-emitter junction of transistor 14 decreases, tending to make V_0L increase. The voltage at the base-emitter junction of transistor 16 decreases, tending to make V_0H increase.

The 75K ECL compensation network uses the increased current through the current source 18 to decrease the voltage at the base of transistor 14, thereby stabilizing V_0L. In the preferred embodiment, a 75K ECL compensation network is comprised of two diodes, 32 and 34, and resistor 30, connected between the complementary outputs of the current switch. Thus, when transistor 10 is conducting, diode 32 is forward-biased and some of the current flows through resistor 30.

To accomplish the stabilization of V_0L, the resistors 20 and 30 decrease the voltage at the base of transistor 14 to adjust for the decrease in voltage at the base- emitter junction of transistor 14. Thus, V_0L is stabilized.

Conversely, when transistor 12 is on and transistor 10 is off, the same relationships apply except that most of the current flows through resistor 22, and diode 34 is forward-biased instead of diode 32. No similar stabilization occurs for V_0H, which is allowed to increase as the temperature increases. Thus, the compensation network has no effect on V_0H. Rather, V_0H can increase as the temperature increases. Those skilled in the art will recognize that the compensation network of the present invention could be added to other ECL circuits without departing from the scope of the present invention.

Those skilled in the art will also recognize that the reference voltages V_BB and V_cs may be supplied by a bias network (not shown) as in 10OK ECL. Such a bias network would tend to make V_BB and V_cs relatively invariant to voltage and temperature changes in V_EE. Thus, V_0H and V_0L would be invariant with regard to changes in V_EE. In summary, a 75K ECL circuit has been described, which circuit has output voltage levels providing the most desirable aspects of the 10K ECL and 10OK ECL standards. The V_0L is constant over temperature and power supply, in a manner similar to 100K ECL. However, the V_0H increases as the temperature increases, in a manner similar to 10K ECL. Thus, the present invention provides a 10K V_0H and a 100K V_0L.

The foregoing description of the preferred embodiment of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

WHAT IS CLAIMED IS:

1. An ECL circuit providing improved 10K ECL V_0H and 100K ECL V_0L noise margins as temperature increases, the circuit comprising: (a) a current switch for steering current through a first and second conductor, wherein said first conductor is connected to a base of a first output transistor and said second conductor is connected to a base of a second output transistor; (b) means for providing the 10OK ECL V_0L at said first transistor and the 10K ECL V_0H at said second output transistor when current flows through said first conductor, whereby the 10OK ECL V_0L remains invariant and the 10K ECL V_0H increases as the temperature increases; (c) means for providing the 100K ECL V_0L at said second output transistor and the 10K ECL V_0H at said first output transistor when current flows through said second conductor, whereby the 10OK ECL V_0L remains invariant and the 10K ECL V_0H increases as the temperature increases.

2. The circuit of claim 1, where the means for providing the 100K ECL V_0L at said first output transistor and the 10K ECL V_0H at said second output transistor (b) comprises: (1) means for decreasing a voltage at said base of said first output transistor independently of said second conductor to compensate for a decrease in a voltage at said base-emitter junction of said first output transistor, said decrease in said voltage at said base- emitter junction due to the temperature increase, whereby said decrease in said voltage at said base causes said 10K ECL V_0L to stabilize.

3. The circuit of claim 2, wherein the means for decreasing comprises: (a) a first diode connected to said base of said first output transistor, said first diode forward-biasing when current flows through said first conductor to said base of said first output transistor; (b) at least one resistor connected to said first diode wherein current flows through said resistor when said first diode forward-biases;

(c) said resistor decreasing said voltage at said base of said first output transistor when said first diode forward-biases, thereby adjusting for said decrease in voltage at said base-emitter junction of said first output transistor caused by the temperature increase.

4. The circuit of claim 1, where the means for providing the 10OK ECL V_0L at said second output transistor and the 10K ECL V_0H at said first output transistor (c) comprises:

(1) means for decreasing a voltage at said base of said second output transistor independently of said first conductor to compensate for a decrease in a voltage at said base-emitter junction of said second output transistor, said decrease in said voltage at said base- emitter junction due to the temperature increase, whereby said decrease in said voltage at said base causes said 10K ECL V_0L to stabilize.

5. The circuit of claim 4, wherein the means for decreasing comprises:

(a) a first diode connected to said base of said second output transistor, said first diode forward- biasing when current flows through said second conductor to said base of said second output transistor;

(b) at least one resistor connected to said first diode wherein current flows through said resistor when said first diode forward-biases; (c) said resistor decreasing said voltage at said base of said second output transistor when said first diode forward-biases, thereby adjusting for said decrease in voltage at said base-emitter junction of said second output transistor caused by the temperature increase.

6. An ECL circuit providing improved 10K ECL V_0H and 10OK ECL V_0L noise margins as temperature increases, the circuit:

(a) means for providing the 10K ECL V_0H whereby the 10K ECL V_0H noise margin increases as the temperature increases; and

(b) means for providing the 10OK ECL V_0L whereby the 10OK ECL V_0L noise margin remains invariant as the temperature increases.