WO1991012531A1

WO1991012531A1 - Method and fast reacting switching circuit for controlling the rotational speed of rotating body

Info

Publication number: WO1991012531A1
Application number: PCT/IT1991/000006
Authority: WO
Inventors: Astorre Biondi; Massimo Casoni
Original assignee: Ducati Energia S.P.A.
Priority date: 1990-02-09
Filing date: 1991-01-30
Publication date: 1991-08-22
Also published as: IT1238990B; AU7149091A; IT9083327A1; IT9083327A0

Abstract

A method and a device to detect electronically the rotation speed of a rotor, particularly for motors, using a fast reacting switching circuit sensitive to the frequency of a pulse train generated by a transducer (1) connected to the rotor, characterized in that it includes: a 'latch' 'E' or any device able to act as a memory of monostable or bistable logic state, as comparison means between two signal characteristics, with at least a first input signal (G) and a second input signal (F), the last one being from said transducer (1) and at least one exit (H) for an output signal. A retriggerable monostable circuit (D) that is triggered by the responsible elaborated signal of the rotation regime (F) and, which exit (G) realizes the period (T) of reference for the 'latch' 'E'; said memory of logic state 'latch' 'E' and said retriggerable monostable circuit (D), are structured to compare continually the period of the signal in the first input (F) attained by said transducer (1), with the duration of the coming pulse from said monostable circuit 'D' (eventually quartzed); that the result of such composition is then memorized each time in said memory of logic state 'latch' 'E' for its utilization to the respective exit (H).

Description

Method and fast reacting switching circuit for controlling the rotational speed of rotating body

This invention has for object a commanded breaker in frequency with high intervention speed particularly to detect a rotation speed of a rotor,

One of the systems more utilized to detect electronically a rotation speed of a motor, is to measure the frequency of a generated signal from an electromechanic transducer (tension/voltage or current of a battery recharge coil, signal of a pick — up, etc.). The more immediate system to obtain a proportional electric signal to the frequency and namely to the turns number of the motor is to realize a converter frequency— voltage. Other systems, more precise, but often complicated and expensive, provide a complex of meters, partition and frequency references that unlikely can find an application in sectors where are required encumbers and limited costs. If we have necessity of one or more digital exit (ON — OFF), which state depends from the rotation regime, the more simple and functional method is to realize a converter frequency— voltage and compare the signal in exit with one or more reference signals.

A converter of frequency—voltage is represented in Figure 1 , in schematic way. According to this schema the analogic signal in input (1) which frequency is proportional to the turns number of the motor, is filtered before and opportunely leveled with one squarer (2). Once "cleaned", the signal is sent to a converter frequency— voltage (3), which gives a tension in proportional exit to the frequency in input (1). The tension in exit of the converter (3) is then compared with a reference tension (5). To the exit of the comparator (OUT) is so obtained, for example, a lower logic level until to a certain rotation regime of the motor, a high logic level from that regime. A system of this type can be used in different applications. It can be used to command a solenoid— valve, which intervention shall happen starting from a certain rotation regime of the motor. It can be used for disabling the ignition stage of a certain motor speed to realize a rotation — speed limiter. A strong limit of a circuit that uses an almost complex converter frequency — voltage is the one depending on the answer time of the system. In any converter F — V (Frequency — Voltage) in fact, the answer time and the conversion precision are two inversely proportional parameters. Once established which shall be the final precision of the circuit, the answer time will be consequential, the only way to make it more fast is to reduce the final precision. This is a strong limit mainly in forceful presence accelerations. In such cases, obviously, late intervention corresponds to an important error on the commutation regime of the breaker.

Scope of the present invention is to prevent said drawbacks.

This and other scopes are reached with the present innovation according to the characteristics of the annexed claims solving the exposed problems by means of a method to detect electronically the rotation speed of a rotor, particularly for motors by means of the use of a commanded breaker in frequency of a responsible signal of the rotation regime of the rotor generated by a transducer, characterized in that it includes: — a "latch" or any device able to act as a memory of monostable or bistable logic state, as comparison means between two signals characteristics, with at least a first and a second input of the signal, the last one being from said transducer and at least an exit of the responsible elaborated signal of the detected turns number; — a retriggerable monostable circuit which is triggered by the responsible elaborated signal of the rotation regime, which exit realizes the period of reference for the "latch" ; — being said memory of logic state "latch" and said retriggerable monostable circuit, structured to compare continually the period of the signal in the first input attained by said transducer, with the duration of the coming impulse from said monostable circuit (eventually quartzed); — that the result of composition be then memorized each time in said memory of logic state "latch" "E" for its utilization to the respective exit.

In such a way the frequency commanded breaker with high intervention speed is able to give high precisions unitedly with minimum answer times, with a lower realization cost and minimum encumber. Advantageously between the source of the signal coming from said transducer and said memory of logic state "latch" and monostable circuit retriggerable, partition frequency means are placed for the scope to increment the performances of the system.

This and other advantages will be understood with the following preferred solutions with the help of the enclosed drawings which particular of execution are not to be considered limitative. Figure 1 represents a block's schema of the device as converter of frequency — voltage in known type. Figure 2 represents a block's schema of a commanded breaker in frequency with high intervention speed according to present invention. Figure 3 represents the behavior signals of the breaker according to Figure 2. 1 Figure 4 represents a preferential schematic form of the breaker according to

2 the present invention.

3 Figure 5 represents an alternative schematic configuration of the breaker

4 according to the present invention.

5 Figure 6 represents a schematic configuration as further variant of the

6 breaker according to the present invention.

7 As disclosed in Figures 2 to 6 and in accordance with the description and

8 claims, according to present invention the device does not work with analogic

9 signals, other than with those eventually generated by the transducer.

I 0 According to Figure 2 the breaker includes:

I I A) an antijamming filter (eventual)

1 2 B) one signal squarer (eventual)

1 3 C) a frequency divisor (eventual)

1 4 D) a retriggerable monostable circuit (eventually quartzed)

1 5 E) a "latch" (or any device able to act by memory of logic state).

1 6 Both the input of retriggerable monostable circuit "D" and the input of a

1 7 "latch" "E", receiving the signal (F), are sensible to the front of the same

1 8 signal.

1 9 Premised that the reference signals can, depending of the exigencies, be 0 completely reversed, the circuit involves as reported in the diagram of Figure 1 3 ; 2 The diagram of Figure 3 represents the synchronism between the signals in 3 the points of: 4 — a first input (writing qualification) of the memory of logic state (E) 5 connected to the signal (F), after filtration (A), squaring (B) and division 6 (C) , 7 — a second input (given— data) to the memory of logic state (E) coming from 8 the exit (G) of the retriggerable monostable circuit (D) and 9 — an exit (H) from the memory of logic state (E). The climbed front of the signal in the first input "F" fixed to the exit of the "latch" "E" the state "H" corresponding to second input "G" of the memory of logic state (E) during the transition will retrigger the monostable circuit "D". For example in time t1 we have a lower passage > high of the signal F. So in the "latch" the lower level of the exit of the monostable in that instant is memorized. After a smallest retard (Nsec " =Nanoseconds" value) due to the t of propagation of the monostable also the impulse of the monostable of duration T starts. At the instant t2 a new lower transition > high of F memorizes in the "latch" the lower state of the exit of the monostable device. Again, being the monostable "T" minor than the period of the signal F a logic ø will came memorized in H. In t3, t4 and 15 the frequency of the signal is augmented but the period is again minor of the T of the monostable so in H a lower state is still present. After time t5 the frequency of "F" increases suddenly. At the lower transition > high value of F in time t6, the triggered monostable for the last time in t5 has not yet commuted in the ø stable state its exit G. This means that the period F is gone under the previously established time T and that so we have surpassed the threshold frequency that determines the commutation of the breaker. In fact in t6 the high state of G is memorized in H and the monostable is retriggered. The same happens in t7 and t8. After the instant — time tδ the frequency of F cheapens brusquely. In t9, the retriggered monostable device in t8 had the time to return to the stable situation so in H is memorized a ø. From the instant t6 to the t9, the exit signal H is translated to the high level, in correspondence of the augment of frequency of the first entry signal F. As we can observe the intervention retard of the exit signal in H is at the maximum value, the provided time corresponding of an oscillation of the first entry signal F and it is therefore very small. In the form of Figure 4 the circuit is sensible to the increasing front of the signal (F). The inputs R1 and B1 shall be connected to the potential V+ if not used , otherwise they can be used for other external commands. In the form of Figure 5 the circuit is sensible to the descended front of the signal (F). The input A1 shall be connected to GND and the R1 and V+ if not used; otherwise they can be used for external commands. In both the configurations, 1/2 lc(A ) is utilized as retriggerable monostable device (D) and 1/2 lc(B) is utilized as bistable device "latch E" ^* R2 can be utilized by an external command or can be connected to Q1 for the scope to reduce furthermore the answer time of the system in frequency input diminution phase and/or for the scope to increase the immunity to noises of 1/2 lc(B). With R2/C2 ( fig.6 ) we can obtain a retard to the deactivation of the breaker even if it can be necessary, R1 and C determine instead always the commutation frequency of the breaker. Obviously the systems can be supplied with intervention hysteresis. In variant to the fig.4 and 5, for example, we can also modify Ri and/or C on command of Q2 and/or Q2. Such systems can be used for the scope to realize rotation — speed detectors for motors that can intervene on the ignition plant, on solenoid — valves or on any other electric transducer.

Claims

1 CLAIMS

2 1. A method to detect electronically the rotation speed of a rotor, particularly

3 for motors by means of the use of a frequency breaker of a responsible signal

4 of the rotation regime of the rotor generated by a transducer (1 ),

5 characterized in that it includes:

6 — a "latch" "E" or any device able to act as a memory of monostable or bistable

7 logic state, as comparison means between two signals characteristics, with at

8 least a first input signal (G) and a second input signal (F), the last one being

9 from said transducer (1 ) and at least an exit (H) of the responsible

I 0 elaborated signal of the detected turns number;

I I — a retriggerable monostable circuit (D) that is triggered by the responsible 1 2 elaborated signal of the rotation regime (F) and which exit (G) realizes the 1 3 period (T) of reference for the "latch" "E";

1 4 — being said memory of logic state "latch" "E" and said retriggerable

1 5 monostable circuit (D), structured to compare continually the period of the

1 6 signal in the first input (F) attained by said transducer (1), with the

1 7 duration of the coming impulse from said monostable circuit "D" (eventually

1 8 quartzed);

1 9 — that the result of said composition is then memorized each time in said

20 memory of logic state "latch" "E" for its utilization to the respective exit (H). 2 1

22 2. A method to detect electronically the rotation speed of a rotor by means of

2 3 breaker and respective breaker according to claim 1., characterized in that

2 4 between the source of the coming signal from said transducer (1) and said

25 memory of logic state "latch" "E" and retriggerable monostable circuit (D),

2 6 partition places frequency means (C) are provided. 27

2 8 3. A method to detect electronically the rotation speed of a rotor by means of

2 9 breaker and respective breaker according to claim 1., characterized in that between the source of the coming signal from said transducer (1 ) and said memory of logic state "latch" "E" and retriggerable monostable circuit (C), a signal squarer means (B) is placed.

4. A method to detect electronically the rotation speed of a rotor by means of breaker and respective breaker according to claim 1., characterized in that between the source of the coming signal from said transducer (1) and said memory of logic state "latch" "E" and retriggerable monostable circuit (D), an antijamming filtering means (A) is placed.

5. A circuit device to detect electronically the rotation speed of a rotor according to claim 1., characterized in that said memory of logic state "latch" E" and said retriggerable monostable circuit (D) are structured and wire — connected according to schema of Figure 4.

6. A circuit device to detect electronically the rotation speed of a rotor according to claim 1., characterized in that said memory of logic state "latch" "E" and said retriggerable monostable circuit ( D ) are structured and wire— connected according to schema of Figure 5.

7. A circuit device to detect electronically the rotation speed of a rotor according to claim 1., characterized in that said memory of logic state "latch" E" and said retriggerable monostable circuit (D) are structured and wire — connected according to the schema of Figure 4 or 5 with the variant of Figure 6, the memory of logic state "latch" "E" becomes so of monostable type.

8. A circuit device to detect electronically the rotation speed of a rotor according to claim 1., characterized in that said memory of logic state "latch" (E) is a circuit device utilized as bistable memory with exclusion of the variant of fig.6 representing a monostable memory.

9. A circuit means to detect electronically the rotation speed of a rotor according to claim 1., characterized in that said memory of logic state "latch" "E" and/or said retriggerable monostable circuit (D) is/are supplied of intervention, hysteresis modifying the respective passive component in function of the exit signal (Ri and or C on command of Q2 and/or Q2).