WO1991007779A1 - Silicon bipolar junction transistors - Google Patents

Silicon bipolar junction transistors Download PDF

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Publication number
WO1991007779A1
WO1991007779A1 PCT/GB1990/001780 GB9001780W WO9107779A1 WO 1991007779 A1 WO1991007779 A1 WO 1991007779A1 GB 9001780 W GB9001780 W GB 9001780W WO 9107779 A1 WO9107779 A1 WO 9107779A1
Authority
WO
WIPO (PCT)
Prior art keywords
trench
bipolar junction
transistor
collector
silicon
Prior art date
Application number
PCT/GB1990/001780
Other languages
French (fr)
Inventor
Philip Aemonn Walker
Original Assignee
Lsi Logic Europe Plc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Europe Plc filed Critical Lsi Logic Europe Plc
Publication of WO1991007779A1 publication Critical patent/WO1991007779A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

Definitions

  • This invention relates to silicon bipolar junction transistors and to improved methods of manufacture of such products.
  • Fig. 1 of the accompanying drawings where a buried layer 10 is used. ⁇ This enables a collector resis ' tance of typically less than 100 ohms to be achieved, but is expensive.
  • the second technique which is shown in Fig. 2 of the drawings, is to use an inexpensive implant 11, but lack of control of the lateral dimension L due to silicon dioxide growth, limits the technique. Consequently, values of collector resistance achieved by the use of this latter technique are high, typically greater than 200 ohms.
  • a method of manufacturing a silicon bipolar junction transistor which comprises the steps of creating a trench in the silicon layer and subsequently providing a collector implant at the bottom of the trench.
  • a silicon bipolar junction transistor comprising a silicon layer in which is provided a trench with a collector implant at the bottom of the trench.
  • the • fabrication steps which characterise the present invention preferably involve only one photolithography step and a subsequent implant step in order to achieve the desired object.
  • Figs. 1 and 2 illustrate two known techniques for the manufacture of silicon bipolar junction transistors
  • Figs. 3a and 3b illustrate the two key steps in the fabrication process of the- present invention
  • Fig. 4 shows one structure of bipolar junction transistor incorporating the invention
  • Fig. 5 shows a second embodiment of bipolar junction transistor embodying the present invention.
  • FIGs. 3a and 3b show the two fabrication steps which undeili* the -present invention.
  • the first fabrication step which may be a photolithography step
  • a shallow trench 12 is etched in a silicon layer 14, using an etch mask 16.
  • the trench 12 has a width w and a depth D.
  • the second fabrication step shown in Fig. 3b, comprises the formation of a collector implant 18 at the bottom of the trench 12.
  • the implant 18 is self-aligned with the etch mask 14.
  • the depth D of-the trench is (a) the depth D of-the trench, (b) the width W of the trench, and (c) the value of the collector implant 18.
  • a depth D of about 0.5 ⁇ m and a width W of about 1.5 ⁇ m are preferred.
  • Values of collector resistance of less than 100 ohms can easily be achieved in this way.
  • the ratio of the width W to the depth D of the trench is of the order of 3 to 1, thus giving a generous aspect ratio and enabling the trench 10 easily to be filled in subsequent fabrication steps towards the creation of the final transistor. It is also important to note that the parameters (a) and (c) referred to above can be used to tailor the collector/base and the collector/emitter breakdown voltages. This provides a further element of design control.
  • Figs. 4 and 5 Two such possibilities are shown in Figs. 4 and 5 of the drawings.
  • the shallow trench is filled with an electrically insulating material 20 so that it is flush with the surface of the base 25, emitter 26 and collector 27.
  • the side walls of the trench are provided with an electrically insulating material 22 and the centre of the trench is formed as a conducting centre 24 which constitutes the collector of the device.
  • the customary fabrication techniques may be used for the formation of the base, emitter and collector, after the novel fabrication step of the present invention.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

A silicon bipolar junction transistor comprises a silicon layer (14) in which is provided a trench with a collector implant (18) at the bottom of the trench. This gives low, controllable collector resistance without the need for buried layers and without the use of silicon dioxide growth processes. The trench may be filled with electrically insulating material (20).

Description

SILICON BIPOLAR JUNCTION TRANSISTORS
SPECIFICATION
This invention relates to silicon bipolar junction transistors and to improved methods of manufacture of such products.
In the manufacture of silicon bipolar junction transistors it is desirable that the collector resistance should be low. There are currently two main techniques used to achieve low values of collector lesistance. The first and most common technique is shown in Fig. 1 of the accompanying drawings where a buried layer 10 is used. ^ This enables a collector resis'tance of typically less than 100 ohms to be achieved, but is expensive. The second technique, which is shown in Fig. 2 of the drawings, is to use an inexpensive implant 11, but lack of control of the lateral dimension L due to silicon dioxide growth, limits the technique. Consequently, values of collector resistance achieved by the use of this latter technique are high, typically greater than 200 ohms.
It is an object of the present invention to provide a fabrication process, and end product, which has some or all of the following advantages: a) values of collector resistance comparable with those using buried layer processes can be achieved, for example of the order of 100 ohms or less. b) precise control of collector resistance. c) a structure which is easier and less expensive to manufacture than using conventional processes. d) a structure which can be retrofitted on to many existing technologies. e) a structure which can be tailor-made to permit control of both collector resistance and collector/base breakdown voltage. f) a structure which can be tailor-made so that it does not adversely affect parasitic base/collector capacitance, small signal cut¬ off frequency, current gain or Early Voltage. Using the method and structure of the present invention one can achieve low, controllable collector resistance without the need for buried layers and without the use of silicon dioxide growth processes which are difficult to control. Additionally, fabrication of the structure according to the invention is straightforward and can be retrofitted on to many existing bipolar processes.
In accordance with the present invention there is provided a method of manufacturing a silicon bipolar junction transistor which comprises the steps of creating a trench in the silicon layer and subsequently providing a collector implant at the bottom of the trench.
Also in accordance with the present invention there is provided a silicon bipolar junction transistor comprising a silicon layer in which is provided a trench with a collector implant at the bottom of the trench.
The • fabrication steps which characterise the present invention preferably involve only one photolithography step and a subsequent implant step in order to achieve the desired object.
In order that the invention may be more fully understood, certain embodiments of the invention will now be described in more detail by way of example and with reference to the accompanying drawings, in which: Figs. 1 and 2 illustrate two known techniques for the manufacture of silicon bipolar junction transistors;
Figs. 3a and 3b illustrate the two key steps in the fabrication process of the- present invention; Fig. 4 shows one structure of bipolar junction transistor incorporating the invention; and,
Fig. 5 shows a second embodiment of bipolar junction transistor embodying the present invention.
Although the following description and the drawings show the use of npn transistors, it should be understood that the techniques are equally applicable to pnp transistors.
-Figs. 3a and 3b show the two fabrication steps which undeili* the -present invention. In the first fabrication step, which may be a photolithography step, a shallow trench 12 is etched in a silicon layer 14, using an etch mask 16. As illustrated, the trench 12 has a width w and a depth D. The second fabrication step,, shown in Fig. 3b, comprises the formation of a collector implant 18 at the bottom of the trench 12. The implant 18 is self-aligned with the etch mask 14.
With this technique there are three parameters which can be varied in order to achieve precise control of the collector resistance. These are (a) the depth D of-the trench, (b) the width W of the trench, and (c) the value of the collector implant 18. Preferably, a depth D of about 0.5 μm and a width W of about 1.5 μm are preferred. Values of collector resistance of less than 100 ohms can easily be achieved in this way.
Preferably, the ratio of the width W to the depth D of the trench is of the order of 3 to 1, thus giving a generous aspect ratio and enabling the trench 10 easily to be filled in subsequent fabrication steps towards the creation of the final transistor. It is also important to note that the parameters (a) and (c) referred to above can be used to tailor the collector/base and the collector/emitter breakdown voltages. This provides a further element of design control.
Using the fabrication technique described above one can then proceed to fabricate a wide variety of silicon bipolar junction transistors which have low, controllable collector resistance without the need for buried layers. Two such possibilities are shown in Figs. 4 and 5 of the drawings. In the structure .shown in Fig. 4, the shallow trench is filled with an electrically insulating material 20 so that it is flush with the surface of the base 25, emitter 26 and collector 27. In the second structure, shown in Fig. 5, the side walls of the trench are provided with an electrically insulating material 22 and the centre of the trench is formed as a conducting centre 24 which constitutes the collector of the device. The customary fabrication techniques may be used for the formation of the base, emitter and collector, after the novel fabrication step of the present invention.
As mentioned above, because of the generous aspect ratio of the trench which is relatively wide and. shallow, one can readily fill the trench in the subsequent fabrication steps towards the creation of the final product.

Claims

CLAIMS :
1. A method of manufacturing a silicon bipolar junction transistor which comprises the steps of creating a trench in the silicon layer and subsequently providing a collector implant at the bottom of the trench.
2. A method as claimed in claim 1, which includes etching the trench by photolithography.
3. A method as claimed in claim 1 or 2, which includes subsequently filling the trench with an electrically insulating material.
4. A method as claimed in claim 1 or 2, which includes subsequently lining the sides of the trench with an electrically insulating material and thereafter filling the core of the trench with an electrically conductive material.
5. A silicon bipolar junction transistor comprising a silicon layer in which is provided a trench with a collector implant at the bottom of the trench.
6. A transistor as claimed in claim 5 , having the trench filled with an electrically insulating material .
7. A transistor as claimed in claim 5 , having the sides of the trench covered with an electrically insulating material and the centre of the trench filled with an electrically conductive material.
8. A transistor as claimed in claim 5, 6 or 7, in which the depth of the trench is of the order of
0.5 μ .
9. A transistor as claimed in any of claims 5 to 8, in which the width of the trench is of the order of 1.5 μm.
10. A transistor as claimed in any of claims 5 to 9, in which the ratio of the width of the trench to the depth of the trench is of the order of 3 to 1.
PCT/GB1990/001780 1989-11-18 1990-11-19 Silicon bipolar junction transistors WO1991007779A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB898926415A GB8926415D0 (en) 1989-11-18 1989-11-18 Silicon bipolar junction transistors
GB8926415.4 1989-11-18

Publications (1)

Publication Number Publication Date
WO1991007779A1 true WO1991007779A1 (en) 1991-05-30

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WO (1) WO1991007779A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011053926A3 (en) * 2009-11-02 2011-06-30 Analog Devices, Inc. Bipolar transistor
US10199482B2 (en) 2010-11-29 2019-02-05 Analog Devices, Inc. Apparatus for electrostatic discharge protection

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2257148A1 (en) * 1974-01-03 1975-08-01 Motorola Inc
US4745087A (en) * 1987-01-13 1988-05-17 Advanced Micro Devices, Inc. Method of making fully self-aligned bipolar transistor involving a polysilicon collector contact formed in a slot with an oxide sidewall
US4933733A (en) * 1985-06-03 1990-06-12 Advanced Micro Devices, Inc. Slot collector transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2257148A1 (en) * 1974-01-03 1975-08-01 Motorola Inc
US4933733A (en) * 1985-06-03 1990-06-12 Advanced Micro Devices, Inc. Slot collector transistor
US4745087A (en) * 1987-01-13 1988-05-17 Advanced Micro Devices, Inc. Method of making fully self-aligned bipolar transistor involving a polysilicon collector contact formed in a slot with an oxide sidewall

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 21, no. 11, April 1979, NEW YORK US pages 4495 - 4497; N.G.Anantha: "Method of Making Isolation Contact to Integrated Circuit Substrate" see the whole document *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011053926A3 (en) * 2009-11-02 2011-06-30 Analog Devices, Inc. Bipolar transistor
US8058704B2 (en) 2009-11-02 2011-11-15 Analog Devices, Inc. Bipolar transistor
US8263469B2 (en) 2009-11-02 2012-09-11 Analog Devices, Inc. Methods of forming a bipolar transistor
US10199482B2 (en) 2010-11-29 2019-02-05 Analog Devices, Inc. Apparatus for electrostatic discharge protection

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Publication number Publication date
GB8926415D0 (en) 1990-01-10

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